JPH04134794A - Eeprom circuit - Google Patents

Abstract

PURPOSE:To improve defect rate by complimentarily storing the data of one bit at first and second transistors for storage, and reading it by differentials. CONSTITUTION:The data of one bit is complimentarily store in first and second transistors 11, 12 for storage through first and second transistors 13, 14 for selection. The gate of the transistor 11 for storage is connected to the source of the transistor 12 for storage, and is connected to a write-in circuit 20. Also, the control gate of the transistor 12 for storage is connected to the source of the transistor 11 for recording, and connected to a erase voltage supply line ERL. Then, by reading the storage data by differentials with the first and second transistors 13, 14 for selection, the life of the memory cell can be improved, and the defect of one of the first and second transistors 11, 12 for storage can be relieved by the other transistor. Thus, the rate of defect can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a highly reliable EEPRO-1 (electrically erasable/programmable read-only memory) circuit.

(Prior art) Conventionally, as a technology in this field, U.S. Patent No. 4.9
Specification No. 01,320 (Document 1) and JP-A-64-5
There was one described in Publication No. 9693 (Document 2).

The document 1 describes the principle and method of EEPROM error correction. As described in this document 1, an EEPROM memory cell, that is, a floating gate MO8 nonvolatile memory device, essentially has a first state indicating an erased state and a second state indicating a written state.
A third state other than the first and second states is assumed. Third
The following conditions are: - The shell has just been manufactured and has never been erased or written to, or has been written and erased multiple times and has reached the end of its service life, or has become defective for some reason. This is one of the states of the memory cell. Error correction is possible by utilizing such properties of the EEPRO-1 memory cells.

Further, the above-mentioned document 2 describes a technology of an EEPROM circuit that can operate at low voltage and low current. This EEP
In the ROM circuit, the number of charge pump circuit stages is increased,
By selectively driving the high voltage switches at low frequencies and by providing circuit means configured with appropriate constants, low voltage and low current operation is possible.

(Problem to be Solved by the Invention) However, in the circuit with the above configuration, even if these technologies are combined, it operates at low voltage and low current,
It has been difficult to construct a highly reliable EEPROM circuit that has a long life, has very few failures, and can detect failures in advance.

The present invention provides a more reliable EEPROM circuit.

(Means for Solving the Problem) In order to solve the above problem, the first invention (first invention) is an EEPROM circuit having a floating gate type memory cell, in which the memory cell is configured as follows. That is, the memory cell includes floating gate type first and second storage transistors, and first and second selection transistors connected to the drains of the first and second storage transistors, respectively. supplying a write voltage to the control gate of the first storage transistor and the source of the second storage transistor, and supplying an erase voltage to the source of the first storage transistor and the control gate of the second storage transistor. It is configured to supply voltage.

A second invention is the first invention, wherein the first and second
The memory cells are connected in the direction of the word line and the first . They are arranged in a hair array in the second bit line direction. The load of each memory cell is formed by a set of FET circuits including the first and second N lines.

A third aspect of the present invention is that in the first aspect, one or both of a write-in voltage-supplying circuit and an erase-voltage-supplying circuit are provided in the memory cell, and the first and second The supply of the write voltage and erase voltage is controlled by the voltage levels of complementary first and second bit lines connected to the drains of the selection transistors, respectively.

A fourth invention is the first invention, wherein the above-mentioned first and second
A readout circuit is connected to complementary first and second bit lines connected to the drains of the selection transistors of the first and second bit lines, respectively. When the voltage level of the second bit line is “111”,
The readout circuit is provided with means for detecting Roll or "□to, g"1".

A fifth invention is the first invention, wherein the first and second
complementary first and second bit lines connected to the drains of the selection transistors of the first and second bit lines, respectively. A means is connected for detecting the potential difference on the second bit line and reading it out as a logic level of 0°1° and 0°.

A sixth invention is the second invention, wherein the first and second
A readout circuit is connected to the bit line of the first bit line, and the voltage level of the second bit line is “11I t' 1lQ11 or O
”, “1” is provided in the readout circuit.

A seventh invention is the second invention, wherein the first and second
to the bit line of the first . A means for detecting the potential difference on the second bit line and reading it at a logic level of "1°"'O" is connected.

(Function) In the first and second inventions, the first invention. One pit of data is complementarily stored in the first and second storage transistors via the second selection transistor.

Then, the stored data is stored in the first. By reading differentially through the second selection transistor, the life of the memory cell can be significantly improved, and a defective state of either one of the first and second storage transistors can be read out differentially through the second selection transistor. Since it can be repaired using transistors, the defective rate can be reduced to 0.
I can figure out 1.

In the third invention, by controlling the supply of the write voltage of the write circuit and the erase voltage of the erase circuit at the voltage level of the first and second bit lines, the write operation and the erase operation are performed for each memory cell. can be done at the same time.

In the readout circuits of the fourth and sixth aspects of the invention, since a mismatch between the logic levels of the first and second bit lines is detected, it is possible to detect the deterioration or life span of a memory cell in advance.

In the fifth and seventh inventions, the first. Since the potential difference on the second bit line is read out in the form of "1FT, 440H", readout accuracy is improved.

Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a circuit diagram of an EEPROM circuit showing a first embodiment of the present invention.

This EEPROM circuit includes a memory cell 10, a read circuit 30 for reading memory cell data, and an erase circuit 40 for generating a high voltage for erasing and erasing the memory cell data. arranged in EEPR
An OM circuit is configured.

For example, the memory cell 10 and the readout circuit 30@
By repeatedly arranging memory cells 10 and erase circuits 40 in eight columns in the vertical direction, a memory cell array of 8 rows×8 rows=64 bits is constructed.

The memory cell 10 includes first and second storage transistors 11 and 12 of floating gate type, and first and second selection transistors 13 that are N-channel FETs.
．． 14 and a write circuit 20.

The gate of the storage transistor 11 is connected to the source of the storage transistor 12 and also to the write circuit 20 . A control gate of the storage transistor 12 is connected to the source of the storage transistor 11 and also to the erase voltage supply line ERL.

The drain of the storage transistor 11 is connected to the first bit line IBL via the selection transistor 13, and the drain of the storage transistor 12 is connected to the second bit line π via the selection transistor 14. The first and second bit lines BL.

One hundred pi are complementary bit line pairs.

The write circuit 20 is a circuit that supplies a high write voltage to the memory transistors 11 and 12, and includes transistors 21 and 22 that are N-channel FETs, and transistors 23, 26, and 2 that are zero-threshold FETs.
7) and capacitors 24 and 25. Here, the zero threshold FET is one in which the threshold voltage is controlled to around Ov (about 0+0.4V).

By using a zero threshold FET, efficient boosting with less voltage loss is possible.

The readout circuit 30 includes common load transistors 31 and 32 consisting of P-channel FETs having current/voltage conversion and differential amplification functions, and an N-channel FET that operates during erasing.
A transistor 33 consisting of ET and “Qll, 1
It is composed of a detection gate 34 for detecting g1P+ or "(TZd"0"), a write gate 35 consisting of an iF-1-t inverter, and a read gate 36 consisting of a tri-state buffer 1. .

The load transistors 31 and 32 are cross-connected to the bit lines BL and π, and their sources are connected to the power supply voltage VDD. The detection gate 34 connects the bit lines BL, [
” potential is “4Tl, “O” or “(Q Pf, “1
This is a circuit that detects a signal error and outputs an error signal ERR. That is, this detection gate 34 converts the error signal ERR into C
, PU or control circuit, etc., that the memory cell 10 has deteriorated or is defective. The write gate 35 is a circuit that inverts the data DA of the data bus or the like and outputs the inverted data to the bit line π in response to the write signal WRE. The read gate 36 is a circuit that outputs read data on the bit line BL to a data bus or the like in response to a read signal RDE.

The output side of the fill gate 35 is connected to the bit line π, and the input side of the read gate 36 is connected to the bit line B. This connection relationship is determined by whether or not the gate is an inverting type. The relationship may be reversed.Also, the input to the write gate 35 must be held during writing, or a data holding circuit such as a flip-flop may be provided as appropriate.

The erase circuit 40 includes transistors 41, 47) which are N-channel FETs, transistors 42, 45, 46) which are zero-threshold FETs, and capacitors 43, 44.
Accordingly, it has a function of generating a high voltage for erasing based on a high voltage VPP (for example, about 20 V) and a clock pulse φ, and is also provided with a logic control circuit 50. The logic control circuit 50 is a circuit that inputs a word line selection signal WO1, a read mode signal RDM, an erase mode signal ERM, a clock pulse φ, T1, and a positive mode signal WRM, and controls read, write, and erase operations for the memory cell 10. and AND gates 51, 52, 54, 5
5 and an OR gate 53.

In addition, in Figure 1 ~\earth○,・inertia word line, Q included.

iW is the clock pulse φ, an interpolation clock pulse generated by the clock.

The erase/read operation (1) and write/read operation (2) of the EEPROM circuit configured as above will be explained with reference to FIGS. 2(a), (b) and FIG. 3.

Figure 2 (a), (t)) are the erasing and writing (
(including reading), and FIG. 3 is a diagram showing changes in the threshold voltage VT of the storage transistors 11 and 12 in FIG. 1.

(1) Erasing/reading operation (FIG. 2(a)) (1a) Erasing operation When erasing the memory cell 10, for example, in FIG. 1, the word line selection signal WO is set to "'1" by an address decoder (not shown). Suppose that

First, as shown in FIG. 2 (a), the erase mode signal ER
When M becomes at 1 to, transistor 3 in FIG.
3 is turned on and the bit line π is turned on. On the other hand, since the word line ~VL○ or °°1°° is connected to the memory cell 2 via \D gate 52 and OR gate 53,
The transistor 21 in 0 is turned on, and the control gate of the storage transistor 11 and the storage transistor 12 are turned on.
The source becomes ○V.

AND gate 54.55 by clock pulse φ,
is open and the transistors 45 and 46 are in a conductive state, so the transistors 41 and 4 constituting the erase circuit 40
A pulse is supplied to the capacitors 2, 45, 46 and the capacitors 43, 44 to activate them, and a high voltage for erasing is generated on the erasing voltage supply line ERL. This high voltage is applied to the storage transistor 1
It works in the direction of making the threshold voltage VT higher (erasing) with respect to 1 and in the direction of making it lower with respect to the storage transistor 12. Therefore, as shown in FIG. 3, the threshold voltage VT of the storage transistor 11 is VTlla, and the threshold voltage VT of the storage transistor 12 is VT1.
2a, respectively.

When the erase mode signal ERM becomes Oi+, the erase operation is stopped.The threshold voltage VT of the transistor 11.
12a is maintained. This is the erased state.

(1b) After the read operation is erased, for example, when performing a read operation, the read mode signal RDM is set to "1". Then, in the erase circuit 40 of FIG. 1, the transistor 47 is turned on via the AND gate 51. Then, the charge on the erase voltage supply line ERL is discharged and initialized.Furthermore, the word line WLO becomes '1' through the AND gate 51 and the OR gate 53, so that the selection transistors 13 and 14 are turned on. Therefore, a potential corresponding to the difference (memory state) between the threshold voltages VT of the storage transistors 11 and 12 appears on the bit line BL. Even if the difference in threshold voltage VT between the memory transistors 11 and 12 is small, the potential on the bit lines BL and B is
．． 32 and is read out as the potential of ((iZl"OFI).

The readout gate 36 in the readout circuit 30 is located at 13 in FIG.
Roughly, the threshold voltage of the positive input terminal of the detection gate 34 is L2.
(approximately 3V), and the threshold voltage of the negative input terminal is set to have the level of L4 (approximately 1V). Such a setting can be achieved by making the input stage of the readout gate 36 and the detection gate 34, for example, a Schmitt circuit, or
This can be easily realized by changing the dimensions of the transistor.

Therefore, by the read gate 36, the stored contents can be read out as "1" when the potential of the bit line BL is above the level 13 in FIG. 3, and as 44011 when it is below.

Further, the bit line BL is detected by the detection gate 34.

The potential of TM is monitored. Therefore, bit line B
When the potential of L is lower than 2 in FIG. 3 or the potential of bit line π is at a level higher than L4 (intermediate state M), the threshold voltage V+ of the memory cell 10 is increased by the erase operation. Indicates that no change has occurred. At this intermediate state M, an error signal ER is sent from the detection gate 34.
R is output. Therefore, due to this error signal ERR, the memory cell 10 is degraded and the degraded areas 1fj, N in FIG.
You can see that there is. Thereby, deterioration or lifespan of the memory cell 10 can be detected in advance.

However, data reading is performed using tt 1 at L3 as described above.
tt, tt () Since pt judgment is performed, even after the error signal ERR is output, a considerable number of times (third
Data can be read correctly up to the number of times na-nb in the figure). Thereby, the lifespan of the memory cell 10 can be significantly improved. Moreover, while the EEPROM circuit is in use, even if one of the storage transistors 11 or 12 in the memory cell 10 becomes defective and the bit line BL or π enters the intermediate state M shown in FIG. 3, the other bit line π or BL
If it is not in the intermediate state M, data can be read correctly. Therefore, the defective rate can be significantly improved.

(2) Write/read operations (Figure 2(b)) (2a)
Write operation In the case of a write operation, the write signal ˜VRE and the write mode signal WR, ˜1 are set to “1°”. Write signal ~V
When RE is set to '1', the write buffer 35 in the read circuit 30 of FIG. 1 is turned on, and the write data DA is turned on.
is the write buffer 35 and the load transistor 31.
Bit BL via 32.

It is transmitted to BL. In general, the write mode signal WRM opens the AND gate 54.55 in the logic control circuit 50, and the clock pulses ψ, T are applied to the AND gate 54.55.
55, the write clock pulses φw, 'tw are generated, and the write circuit 20 is activated by the write clock pulses φW, iW.

However, when the bit line π is "0", the transistor 26.
27 remains off, and the write circuit 20 is not activated. This is because the memory cell 10 is already in the erased state. Therefore, the write-in operation is performed only when bit π="'1" and bit line BL="'O". This enables accurate access operations.

The output of the write circuit 20 works to lower the threshold voltage VT of the memory transistor 11 and to increase the threshold voltage VT of the memory/old transistor 12.

Therefore, as shown in FIG.
1 from the state of VTlla to the direction of VTI1b, and the memory transistor 12 from the state of V12a to VT12.
Each threshold voltage V moves in the direction b.

When the write signal @WRE and the full write mode signal WRM become “O”, the write operation is stopped, but the threshold voltage ■T of the memory transistors 11 and 12 becomes vTl.
It is held in the state of lb and VT12b. This is the data write state.

(2b) Read operation In the read operation after writing, the read mode signal RDM is set to "1" similarly to the read operation in (1b) above. Then, the charge output from the write circuit 20 is transferred to the transistor 21
When the selection transistors 13 and 14 are turned on, the selection transistors 13 and 14 are turned on, and data can be read. When the read signal RDE becomes "1", the read gate 36 in the read circuit 30 is turned on, and the read data on the bit lines 8L and π is output to the data bus or the like.

In this first embodiment, the method of replacing memory cell data is first carried out by memory cells 10 . . . on word lines WLO, . . . .
Data is written to 12.

FIG. 4 is a circuit diagram of a memory cell showing a second embodiment of the present invention.

In this memory cell IOA, storage transistors 11 and 12 and selection transistors 13 and 14 similar to those shown in FIG.
In addition, a write circuit 2OA substantially similar to that shown in FIG. It is being

As described above, since the erase circuit 40A is provided in the memory cell 10A, erasing and filling of data is performed in the memory cell 10A by inputting data from the bit lines 8m and π.
A plurality of memory cells 10A are selectively controlled within a cell and connected to the same word line.

...can be written and erased simultaneously. That is, data can be rewritten by simply selecting the word line WLO using the word line selection signal WO and supplying the clock pulses φ and T. For reading, word line selection signal @
Word line WLO is selected by WO, and the word line W
The selection transistors 13 and 14 may be selected by supplying the read signal RD to LO.

In addition to having almost the same advantages as the first embodiment, the second embodiment also has the following advantages. Since the erase circuit 40A is provided in the memory cell 10A, although the area of the memory cell IOA becomes large, it is possible to perform 8-inclusion and erase of the memory cells 10A, . . . connected to the same word line at the same time. Therefore, it is possible to shorten the 8-inclusion and erasing time.

Note that the present invention is not limited to the above embodiments, and various modifications are possible. Examples of such modifications include the following.

(a) In FIG. 1, the read buffer 36 is provided in the read circuit 30 to read out the data DA, but a loose circuit may be used to read the data DA.

For example, FIG. 5 is a circuit diagram of a differential sense amplifier,
A load transistor 61 consisting of a P-channel FET.
62, bit line BL, transistors 63 and 64 consisting of N-channel FETs that take a differential of ffπ, and constant current source transistors 65 consisting of N-channel FETs to which reference voltage VB is applied. ing.

If such a differential sense amplifier 36A is provided in place of the read gate 36 in FIG. 1 and the potential difference between the bit lines BL and π is detected, the read gate 36 in FIG. Although the circuit configuration becomes complicated, more accurate reading of data DA becomes possible.

(b) In FIG. 1, the capture circuit 20 is connected to the memory cell 1.
However, the write circuit 20 may be provided outside the memory cell 10, or the erase circuit 40 may be provided within the memory cell 10 and the write circuit 20 may be provided outside the memory cell 10. Also, almost the same advantages as in the first embodiment can be obtained.

(C) Memory cell 10゜1 shown in Figures 1 and 4
The OA, write circuit 20.20A, read circuit 30, and erase circuit 40.40A can also be modified into circuit configurations other than those shown in the drawings by using other transistors, gates, etc.

(Effects of the Invention) As described above in detail, according to the first and second inventions, data of one pit is transferred to the first. By storing information complementary to the second storage transistor and reading it out differentially, it is possible to significantly improve the cycle (lifetime) of repeated writing and erasing. Moreover, even if one of the first and second storage transistors becomes defective, the memory cell can be accessed as long as the other is normal.
The defective rate can be significantly improved.

According to the third invention, since the supply of the write voltage and the erase voltage is controlled, the write operation and the erase operation can be performed accurately, and the write time and erase time can be shortened.

In the fourth and sixth aspects of the invention, since the reading circuit detects the mismatch state of the voltage levels of the first and second bit lines, it is possible to detect deterioration or life of the memory cell in advance.

In the fifth and seventh inventions, the first. Since the potential difference on the second bit line is read in the form of "1" and "0'," even if minute memory cell data is read at low voltage and low current, it can be read with high accuracy. .

Therefore, it is possible to realize an EEPROM circuit with a simple circuit configuration, small circuit scale, and low power consumption, so it can be used in various 'IA's such as cordless telephones, automatic telephones, cameras, etc., which require small size and low power consumption. Can be applied to @.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an EEPROM circuit showing a first embodiment of the present invention, FIG. 2 (a>, (b) is a timing diagram of erasing and writing (including reading) in FIG. 1, and FIG. 3 is a diagram showing changes in the threshold voltage VT of the storage transistor in FIG. 1, FIG. 4 is a circuit diagram of a memory cell showing a second embodiment of the present invention, and FIG. 5 is a circuit diagram of a differential sense amplifier. 10.10A...memory cell, 11.12...first
゜Second storage transistor, 13.14... 1st゜Second selection transistor, 20.20A... Write circuit, 30... Read circuit, 31.32... Load transistor, 34...Detection gate, 35...West entry gate, 36...Reading gate, 40.40A...
- Erasing circuit, 50... logic control circuit.

Claims (1)

[Claims] 1) EEP having floating gate type memory cells
In the ROM circuit, the memory cell includes floating gate type first and second storage transistors, and first and second selection transistors connected to the drains of the first and second storage transistors, respectively. and supplying a write voltage to the control gate of the first storage transistor and the source of the second storage transistor, and controlling the source of the first storage transistor and the second storage transistor. An EEPROM circuit characterized by having a configuration in which an erase voltage is supplied to the gate. 2) The EEPROM circuit according to claim 1, wherein the memory includes gates of the first and second selection transistors connected to a word line, and drains of each transistor connected to complementary first and second bit lines. The cells are arranged in an array in the direction of the word line and the first and second bit lines, and the load of each memory cell is a set of FET circuits on the first and second bit lines. An EEPROM circuit characterized by the following structure. 3) The EEPROM circuit according to claim 1, wherein one or both of a write circuit supplying the write voltage and an erase circuit supplying the erase voltage are provided in the memory cell, and the memory cell is provided with a write circuit for supplying the write voltage and an erase circuit supplying the erase voltage. An EEPROM circuit characterized in that the supply of the write voltage and the erase voltage is controlled by the voltage levels of complementary first and second bit lines connected to the drains of the transistors, respectively. 4) In the EEPROM circuit according to claim 1, a read circuit is connected to complementary first and second bit lines connected to the drains of the first and second selection transistors, respectively, and The voltage level of the second bit line is “
5) The EEPROM circuit according to claim 1, wherein the readout circuit is provided with means for detecting ``1'', ``0'' or ``0'', ``1''. A means is connected to detect the potential difference on the complementary first and second bit lines connected to the drains of the selection transistors, respectively, and read it out at logic levels of "1" and "0". 6) The EEPROM circuit according to claim 2, wherein a read circuit is connected to the first and second bit lines, and the first and second bit lines are connected to each other.
The voltage level of the second bit line is “1”, “0” or “
7) The EEPROM circuit according to claim 2, further comprising a means for detecting the first and second bit lines in the readout circuit. ``1''
An EEPROM circuit characterized in that an EEPROM circuit is connected to reading means at a logic level of "0" or "0".