JPH0413370A - Picture processor - Google Patents

Abstract

PURPOSE:To reproduce a character, a wire frame and a halftone picture in an excellent way by converting an inputted picture data into a data suitable for picture edge extraction with a 1st data conversion means, converting also it into a data suitable for intermediate tone reproduction with a 2nd data conversion means and binarizing the converted data respectively. CONSTITUTION:A processing section based on the dither method and the error dispersion method in a halftone binarizing processing circuit 2 and a thin line edge extraction processing circuit 3 apply arithmetic processing to plural picture data respectively to obtain an object binarized picture. Since a line buffer is used to store tentatively the picture data in the arithmetic processing of the data, the data binarized by each processing of dither, error dispersion and thin line edge extraction have a relative delay. A main scanning direction picture synchronization section 402 takes the picture synchronization in the main scanning direction for the relative delay and a subscanning direction picture synchronization section 403 takes the picture synchronization in the subscanning direction for the relative delay respectively. A halftone binary picture data 4a and a thin line binary picture data 4b are inputted to a positive logic OR circuit 501 and a negative logic OR circuit 502, in which the data are respectively subject to logic operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus, and more particularly, to an image processing apparatus that inputs and processes images including binary images such as text and line drawings and halftone images.

[Prior Art] An example of this type of device is a facsimile machine. A facsimile is a device that electrically reads image information from a document and sends it to a remote location via a telephone line.

Conventionally, the original to be read was assumed to be a document, and the purpose was to read text information clearly and print it clearly.

However, in recent years, as the number of such devices has increased, various documents have been sent more frequently, and it has become necessary to clearly reproduce the halftones of printed matter such as gravure and photographs.

Since it is impossible to reproduce halftones of an image using binary information such as "1" or "0" degree using one pixel, it is necessary to express the image using the average density of a plurality of pixels.

A dither method has been known as this type of gradation expression method. What is the dither method? When converting the multivalued information of an input image into binarization, the various binarized darkness values are arranged in a matrix of a certain size (dather matrix), and the white and black in the matrix are Gradation is expressed by area ratio. This method allows smooth gradation expression similar to halftone dots in printing, but since one halftone pixel is apparently composed of multiple pixels that make up the dither matrix, it is difficult to use for characters and line drawings that contain thin lines. The resolution has decreased and it is difficult to read (
Become. For example, if halftones are expressed using a 4×4 matrix, the vertical and horizontal resolutions will each be reduced to 1/4.

Furthermore, as a halftone reproduction method different from the dither method, the error diffusion method has recently been attracting attention. The error diffusion method is a method of correcting peripheral pixel data by distributing the binarization error that occurs when an input multilevel image signal is binarized using a fixed threshold to surrounding pixels with predetermined weighting. This corrected pixel data is further binarized using a fixed threshold value, and the error is distributed two-dimensionally. By repeating this error distribution until the end of the image area, the binarization error is reduced in terms of area (density preservation Smooth images with good quality can be reproduced.

However, character information is composed of thin lines, and the contrast (MTF) of these thin lines is reduced by the optical system placed between the document and the photoelectric conversion element. especially,
When the reading resolution is about 1/8 mm, horizontal lines in Mincho fonts will cause a significant drop in the image signal, and even pure black characters will be read as medium-density characters due to a drop in MTF, so the error diffusion method is used. Even after converting the text into binarized text, the text turned out to be thin and choppy.

[Problems to be solved by the invention] In order to solve these problems, the applicant has already configured an edge extraction circuit for extracting large density changes in parallel with a halftone reproduction circuit, and We proposed an image processing circuit that has a synchronization circuit and a synthesis circuit, and can obtain image information with high halftone reproducibility and high character quality.

However, in order to reproduce halftones, the luminous intensity-density conversion (l
og conversion) circuit, a so-called gamma (γ) conversion circuit, is provided at the stage before the input to the edge extraction circuit and the halftone reproduction circuit, and the result of applying the same conversion and input is 1. Edge extraction from image information with low density in thin line areas was incomplete.

The present invention was made in view of this problem, and it
It is an object of the present invention to provide an image processing device that can satisfactorily reproduce line drawings and halftone images.

[Means for Solving the Problem] In order to solve this problem, the image processing apparatus of the present invention has the configuration shown below. That is, an input means for inputting image data as density data, a first data conversion means for converting the density data input by the input means into density data for a binary image, and a first data conversion means for converting the density data input by the input means into density data for a binary image; a second data conversion means for converting the data into density data for a halftone image; and an edge portion of the image is extracted based on the data converted by the first data conversion means and output as a binary image. an edge extracting means; a binarizing means for binarizing and outputting the data converted by the second data converting means to obtain a halftone image by area modulation; A composing means is provided for composing the value image and the binary image obtained by the edge extracting means.

[For use] In the configuration of the present invention, the first data conversion means converts input image data into data suitable for image edge extraction, and the second data conversion means converts input image data into data suitable for halftone reproduction. Convert to . And the second
The image converted by the data conversion means is converted into a binary image by area modulation to obtain a halftone image by a binarization means.
The image that has been digitized and converted by the first data conversion means is binarized by the edge extraction means into an edge image in which portions with steep density gradients are extracted. Then, the two binary images obtained in this way are combined by a combining means.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit block diagram according to the present invention.

In the figure, ■ is a γ conversion device that converts input image data (converted into digital data) from an image scanner (not shown) etc. into two types of γ values and outputs it, and 2 is a γ conversion device that uses the dither method and error diffusion method. Binarization circuit that binarizes halftone images, 3
4 is a thin line edge extraction circuit that extracts edge portions of thin lines such as characters; 4 is an image synchronization circuit that aligns the binarized images in the halftone binarization circuit 2 and the thin line edge extraction circuit 3;
5 is an image synthesis circuit that superimposes and outputs two synchronized images.

Analog image data read from an image input device such as an image scanner is quantized to 6 bits (64 gradations) and γ-converted to data suitable for the halftone binarization circuit 2 and thin line edge extraction circuit 3. After that, each circuit has 2
Valued. In addition, here, as pre-processing for binarization processing,
Well-known shading correction, density conversion, etc. are performed.

The contents of the halftone binarization circuit 2 and the thin line edge extraction circuit 3 will be described later, but in order to binarize the pixel of interest, several surrounding pixels are also utilized. Therefore, the binary data 2a, 3a at the pixel position of interest outputted from them has a synchronization shift of several lines and several dots. The image synchronization circuit 4 corrects this synchronization deviation, and the image synthesis circuit 5 synthesizes the two images.

FIG. 2(A) is a circuit diagram of the γ conversion device 1 of the embodiment, and the same figure (
B) shows an address map of the γ conversion ROM in the γ conversion circuit 1, and FIG. 2C shows a timing chart.

The read image data 1a quantized to 6 bits is 8KX
8: Word EFROMIOI address input ADD○
~5 is input. A control line 5EL1b for switching the γ value is input from the timing generator 104 to the upper bit ADD6 of the address input. This EF
ROMIOI contains a γ conversion value (γ1) suitable for binarizing halftones and a γ conversion value (γ1) suitable for extracting fine line edges.
2) or the address shown in Figure 2 (B), the converted value of γ1 is assigned to the address space of address bit ADD6 or “O′°, and when it is “°1”, the converted value of γ2 is assigned. I remember it.

Then, the state of address bit ADD6, that is, control line 5
Two types of γ conversion values are selected depending on the state of EL1b and output to the data line 1c. This data includes Figure 2 (
As shown in C), there are two pieces of output data 1c having different γ values within a time period corresponding to a pixel of input image data 1a, and these are separated and output by latch circuits 102 and 103.

The latch circuit 102 outputs γ suitable for the halftone binarization circuit 2.
Data 0DTI having a value is output as data 1e, and data 0DT2 outputted from the latch circuit 103 is outputted to the thin line edge extraction circuit 3 as data 1f.

FIG. 8 shows two γ conversion characteristics γl and γ2 in the above-mentioned EPROMI Ol.

As shown in the figure, γ1°, which is the γ conversion characteristic for halftones, is a semi-logarithmic curve. This is because the printer connected to this device is an LBP (laser beam printer). In other words, a CCD (solid-state device) used as an element to photoelectrically convert a document image outputs a voltage proportional to the amount of incident light, and a printer prints dots with a constant density and a constant area on white paper according to the input signal. This is because since the density is limited by the area of white and black when they are arranged, it is necessary to convert the light amount information, which is the COD output, into density data for LBP. This is a well-known conversion in facsimile and the like. In fact, γ1'' takes into account the photoelectric conversion properties of the CCD itself and the durability of the LBP (how the dots overlap due to the laser beam diameter, phenomenon characteristics, etc.).

Next, the conversion characteristic is "γ2°", and the reason why it was done this way is that the image information is changed to "0 (= white)" in the part with a gentle gradation change.
This is to make it suitable for a circuit for extracting edges of characters, lines, etc.

Edge extraction will be described later, but as shown in Figure 9, the data A of the pixel of interest that is to be binarized and the average value of the surrounding 5x5 24 pixels Bi (i = 1 - = 24). The binarization level (
It performs so-called differential processing to determine whether the image is white or black.

Expressed as a formula, it is as follows.

If C>O, the pixel of interest is made black (="i"°).

Note that α'' is a constant that determines the degree of edge enhancement.

If the °゛γ1'' conversion is performed before and after this process, the change in the light amount on the black side will be amplified, so for example, in the dark part of halftone color printing, the point where the three points Y, M, and C overlap is point A. , the binarization result will be “1°”. As a result, isolated points are scattered in the hazy dark part, and when the halftone output and edge extraction output are combined, the intermediate reproducibility on the dark side is impaired. In addition, if the light amount data output is used as is, the change in the light amount on the white side is large compared to the human eye (compared to the change in density), so it is possible to extract the image information by extracting edges such as roughness on the paper surface, dirt, and toner powder adhering to the copied image. It will be output as .

Therefore, in this embodiment, data near white (density 0
．． 1 or less) to a constant value, and uses a γ conversion characteristic "γ2" that does not change data beyond that value. Edge extraction performs binarization based on the difference with surrounding pixels rather than the absolute value of the data, so even if input data near white is converted to a constant value S, it will not appear in the image.

FIG. 2(C) is a timing chart showing the signal flow of the γ conversion device.

γ conversion EPROMI O1 is input data 1 of n-th pixel
With respect to a, two types of γ conversion values 1c, γ1 and γ2, are outputted during the input time t for one pixel due to the SEL signal 1b of °°O"1". The output data 1c is sent to latch circuits 102 and 10 at the rising and falling edges of the LTI signal, respectively.
3 and separated into 0DTI and 0DT2. 0
The output 1e of the DTI is sent to the halftone binarization circuit, and also to the 0DT2
The output 1d of is binarized in a thin line edge extraction circuit.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram of the halftone binarization circuit 2. As shown in FIG. In the figure,
201 is a halftone binarization part using the dither method, and a comparator 202 and a 4×4 dither matrix 2 for binarization.
Equipped with 03.

204 is a halftone binarization part using the error diffusion method, a comparator 205 for binarization, a binarization error distribution calculation unit 206 having a memory for accumulating the diffused error values,
It includes a subtracter 207 that takes the difference between the data of the pixel of interest and the data of the output pixel, an adder 208 that adds the previously accumulated error amount to the input pixel data of interest, and the like.

The image data binarized by the halftone binarization units 201 and 202 are selected by the selector 209, and output data 2a
It is output to the image synchronization circuit 4 as a.

Explain the operation.

The image data 1e that has been preprocessed for halftone binarization is sent to a dither binarization circuit 201 and an error diffusion binarization circuit 20.
4 is input.

In the dither method binarization circuit 201, 16 threshold values are set in a 4×4 dither matrix before binarizing the input image. The set dither matrix 203 is
Threshold values are sequentially output according to the data of the corresponding input image. The threshold value outputted from the dither matrix 203 and the input pixel data of interest are compared by the comparator 202 to be binarized. The binarized pseudo-halftone image data is 4×4=16 pixels corresponding to the dither matrix.
expresses two gradations.

On the other hand, the error diffusion binarization section 204 operates as follows.

In other words, the input image data (target pixel data) 205
is added to the pixel position of interest outputted from the binarization error allocation calculator 206 and the error amount accumulated up to that point in an adder 208 . The data of the pixel of interest position that has been added (the pixel of interest data to which the binarization error has been distributed) is compared with a fixed threshold value supplied to the comparator 205 and binarized. At this time, 2
A subtracter 207 takes the difference between the value before digitization and the value after binarization, and calculates the amount of error generated in the binarization process.

The calculated error amount is taken into the binarization error distribution calculator 206, and predetermined weighting is applied to diffuse the non-binarization error positions (there are a plurality) around the pixel position of interest according to the coefficient. below,
By repeating this process, a smooth binarized image with few binarization errors is reproduced.

In the selector 207, the halftone binarization units 201 and 204
The converted image is selected while in output mode,
It is output as a halftone image 2a.

Incidentally, at the same time as the halftone binarization processing circuit 2 performs the binarization process, the thin line edge extraction circuit 3 executes a thin line edge extraction process to form a contour image of a thin line such as a character or a figure.

FIG. 4(A) is a configuration diagram of the thin line edge extraction circuit 3;
B) shows the one-dimensional image waveform of each component.

The thin line edge extraction circuit 3 includes the γ conversion device 1 described above.
Data from lfga is supplied.

This data 1f is stored in the line buffer 301 for 5 lines.
A window section 302 that is stored in the
The image is extracted as 5×5 pixel data. This 5X5
The pixel data 3d of the window is differentiated by the differential operation unit 303, and edge portions are extracted from the density gradient of the pixel data. By performing a differential operation on the 5×5 window, it is possible to remove electrical noise and the like having very high frequency components. A comparator 305 compares the edge image data 3b obtained by the differential operation section 303 with a threshold value 3c set by a threshold value setting section 304 whose setting value can be changed arbitrarily and binarizes the resultant edge image data 3b. The extracted image 3a is output. By changing the setting of this threshold value, the degree of emphasis of thin line edges can be changed.

FIG. 5 shows the configuration of the image synchronization circuit 4.

The processing section based on the dither method and error diffusion method of the halftone binarization processing circuit 2 and the thin line edge extraction processing circuit 3 each perform arithmetic processing on a plurality of image data in order to obtain the desired binarized image. . For image data calculation processing, a line buffer is used to temporarily store the data, so dithering,
The data that has been binarized by the error diffusion and thin line edge extraction processes has a relative delay. Based on the relative delay number set by the relative delay number setting unit 401, the main scanning direction image synchronization unit 402 performs image synchronization in the main scanning direction, and the sub-scanning direction image synchronization unit 403 performs image synchronization in the sub-scanning direction. ing. The main scanning direction image synchronization unit 402 performs image synchronization in the main scanning direction by delaying either image data 2a or image data 3a, whichever has a phase lead in the main scanning direction, by that amount using a shift register or the like. , match the image data whose phase is delayed. Further, synchronization in the sub-scanning direction in the sub-scanning direction image synchronization unit 403 is performed by delaying either image data 2a or image data 3a, whichever has a phase lead in the sub-operation direction, by the line buffer by that amount. , match the image data whose phase is delayed. As a result, the binary image data 4a for halftones and the binary image data 4b for fine line edges are completely synchronized.
is generated.

FIG. 6 shows the binary image data 4a for halftone described above.
The configuration of an image synthesis circuit 5 of an embodiment for synthesizing the image data 4b and the binary image data 4b for fine line edges is shown.

Binary image data 4a for halftones and binary image data 4 for thin lines
b is as shown in the figure (positive logic OR circuit 501 and negative logic O
The signals are input to the R circuit 502 and subjected to logical operations. Data 4a and 4b are positive logic image data, that is, black is "1".
'', when white is "0", the OR circuit 501 or negative logic image data, that is, when white is "1" and black is "O", the OR circuit 501 is used.
A logical sum operation is performed in the circuit SO2.

The data calculated by the OR circuits 501 and 502 are output as image composite data 5a selected by the selector 503.

FIG. 7 shows an image processed by the above-described embodiment. 4A is an image based on halftone binary image data 4a obtained by the dither method, and FIG. 2B is an image based on thin line edge binary image data 4b from the thin line edge extraction circuit 3.

The image (C) in the figure is a composite of the images in (A) and (B), that is, based on the output data 5a of the image synthesis circuit 5.

The input image shown in FIG. 7 is a 14-point Mincho type character read at a resolution of 400 dpi.

The image in FIG. 7(A) is patterned by a dither matrix unique to dithering, resulting in a decrease in resolution, resulting in characters that are difficult to read. By synthesizing the characters (B) in the same figure, it is possible to generate characters with well-defined and easy-to-read characters.

Furthermore, since the thin line edge image to be synthesized appears only at the outline of the character, the density of the entire character is also preserved at the center of the character.

In the above description, the halftone binarization circuit 2 performs dither processing, but it goes without saying that the processing may also be performed using the error diffusion method.

An example of a binary image based on the error addition method is shown in FIG. 10(A). As shown in the figure, the character reproduction line is better than the one using dither processing, but even though it is an error diffusion method, the character reproduction is not satisfactory due to the density of the read image and the MTF characteristics of the image reading system. . Therefore, in this case as well, by combining the edge image extracted by the earliest edge extraction circuit 3 as shown in Figure (B), Figure (C) (7
), it is possible to generate a character image in which the density of the central part of the character is preserved.

In the embodiments described above, binarization was described using a dither method and an error diffusion method as halftone processing methods, but the present invention is not limited to these methods and can be applied to any halftone processing method. Further, although a method using a differential operation using a 5×5 window has been described as thin line edge enhancement processing, the window size and the differential operation method are not limited to the method of this embodiment.

Furthermore, it is easy to predict that the image synchronization circuit would not be necessary if there were no relative delay between the halftone binarization circuit and the thin line edge extraction circuit 3. Although an OR circuit is used as the image synthesis circuit 5, other circuits may be used as long as they have the function of synthesizing a plurality of image data.

Although EPROM is used as the conversion data storage means of the γ conversion device 1, other types of storage means such as mask ROM, RAM, etc. may be used.

In the present invention, the γ conversion device 1 includes γ1. Although only two types of γ2 are used as examples, further applications are possible by using a plurality of types.

As explained above, according to this embodiment, a halftone image is binarized using a γ conversion value suitable for halftone processing, and
Thin line images such as characters are binarized using γ conversion values suitable for edge extraction. By compositing these images, it is now possible to faithfully reproduce halftone-processed images containing thin lines, such as characters and figures, without compromising the gradation expression of the halftones. Become.

In addition, by switching and using one γ conversion ROM within the time of one pixel, it is possible to convert multiple γ from one pixel data.
Do not use multiple ROMs to output conversion data (
This is advantageous in terms of line size reduction and cost.

[Effects of the Invention] As described above, according to the present invention, it is possible to produce good images for both halftone images and thin line images such as characters.

[Brief explanation of drawings]

Figure 1 is a main configuration diagram of the image processing section in this embodiment, Figure 2 (A) is a configuration diagram of the γ conversion circuit in Figure 1, and Figure 2 (B) is the address of the ROM in Figure (A). Figure 2 (C) is a timing chart showing the operation of the γ conversion circuit; Figure 3 is a configuration diagram of the halftone binarization circuit in the embodiment; Figure 4 (A) is the thin line in the embodiment. 4(B) is a timing chart for explaining the operation in FIG. 4(A). FIG. 5 is a block diagram of the image synchronization circuit in the embodiment. FIG. 6 is a diagram in the embodiment. A block diagram of the image synthesis circuit, FIG. 7(A) is a diagram showing a dithered image obtained by processing with the halftone binarization circuit of the embodiment, and FIG. 7(B) is a diagram showing the first edge extraction of the embodiment. A diagram showing an edge image processed by circuit 3, a diagram showing a composite image obtained by processing by the image synthesizer of the embodiment of FIG. 7(C), and FIG. 8 shows the γ conversion of the embodiment. FIG. 9 is a diagram showing the target for detecting the density gradient at the pixel position of interest. FIG. FIG. 10(B) is a diagram showing an edge image processed by the earliest edge extraction circuit 3 of the embodiment, and FIG. 10(C) is a diagram showing an edge image obtained by processing by the image synthesizer of the embodiment. It is a figure which shows the composite image obtained by processing. In the figure, l...γ conversion device, 2... halftone binarization circuit, 3... thin line edge extraction circuit, 4... image synchronization circuit, 5... image synthesis circuits 201 and 204. ... Halftone binarization section, 202 and 205 ... Comparator, 203 ...
・Dither ROM, 206...binarization error distribution calculator,
207...Subtractor, 208...Adder, 209...
- Selector, 301...Line buffer, 302...
Window, 303... Differential operation section, 304... Threshold value setting section, 305... Comparator, 401... Relative delay number setting section, 402... Main scanning direction image synchronization section, 403
. . . Sub-scanning operation direction image synchronization unit, 503 . . . Selector. Patent applicant Canon Corporation (A) (B) Figure 2 Figure 5 Figure 6 (A) (B) (C) Figure 7 Figure 8 Figure 9

Claims (2)

[Claims] (1) an input means for inputting image data as density data; a first data conversion means for converting the density data input by the input means into density data for a binary image; a second data conversion means for converting the density data into density data for a halftone image; and an edge portion of the image is extracted based on the data converted by the first data conversion means and output as a binary image. an edge extracting means for converting the data converted by the second data converting means,
Binarization means for binarizing and outputting to obtain a halftone image by area modulation, and composition means for synthesizing the binary image obtained by the binarization means and the binary image obtained by the edge extraction means. An image processing device comprising: (2) The image processing apparatus according to claim 1, wherein the first and second data conversion means are each gamma conversion means.