JPH04133591A - Spatial switch circuit system - Google Patents

Abstract

PURPOSE:To realize a high transmitting speed by providing (n) pieces of input buffers to which received signals are inputted, (n) pieces of output buffers from which transmitting signals are outputted, a selection circuit connected to the output sides of the (n) pieces of input buffers, distribution circuit connected to the input sides of the (n) pieces of output buffers, and control circuit which controls the selection and distribution circuits. CONSTITUTION:When data transmission is performed between input-output buffers 51 and 58, the receiving and transmitting signals (1) and (2) of the buffer 51 are controlled so that they can be respectively connected to SSW terminals 7a and 7b by a control signal from a control circuit 2. As a result, signal routes from the signal (1) to the terminal 7a and from the terminal 7b to the signal (2) are established at a selection circuit 3. Similarly, the receiving and transmitting signals (15) and (16) of the buffer 58 are controlled so that they can be respectively connected to the SSW terminals 7b and 7a and signal routes from the signal (15) to the terminal 7b and from the terminal 7a to the signal (16) are established at a distribution circuit 4. Therefore, data transmission becomes possible between the input-output buffers 51 and 58.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a space switch circuit system, and particularly to a multi-switch space switch circuit system with a high transmission signal speed (for example, 32 MH2).

[Conventional technology]

The conventional space switch (hereinafter abbreviated as SSW) circuit system is
As shown in Figure 2, for example, a 2x8 (nxHl) SS
W circuit 11. ~11. and these SSW circuits 111-1
1. 8 for multi-connecting 8 (m) terminals each.
3w lotus 20a to 20h and each SSW circuit 111 to 11
It has a control circuit 2 that controls 11. In addition, 1 in the figure
21.12°~121. is a received signal input terminal, 122,
12. ~12, , are transmission signal output terminals.

Next, the operation will be explained. For example, ssw circuit 11.
and SSW circuit 11. When transmitting data between
SSW circuit 11. The received signal (2) and the transmitted signal (2) are controlled to be connected to the SSW buses 20a, 20b, respectively, by control signals from the control circuit 2. This results in
The signal paths of the received signal - bus 20a and the transmitted signal - bus 20b are confirmed. Similarly, ssw circuit 11. The received signal [phase] and transmitted signal [phase] are each 38W.
By controlling the connections to the buses 20b and 20a, the received signal - bus 20b and the transmitted signal [phase] - Hass 20
The signal path of a is confirmed. As a result, data transmission becomes possible between the SSW circuit 111 and the SSW circuit 11s by establishing the routes ①→20a-[phase] and ②-20b-① via the SSW bus.

Furthermore, when data is to be transmitted between different SSW circuits, SSW lots other than the already used SSWs 20a and 20b are allocated and the corresponding SSW circuit is set.

The SSW circuit will be explained below.

FIG. 3 is a 2×8 SSW circuit diagram, and here the SSW circuit 11. of FIG. 2 is shown. The case is shown below. 13 in Figure 3
141-148 are input/output buffers; 15. is an SSW unit with a selection function; 141 to 148 are input/output buffers; ~158 is SSW bus 20a~2
The terminals connected to 0h and 16 are input terminals for control signals.

- By controlling the control circuit 2 during boat fishing, transmitting and receiving signals and SS
The connection with the W bus is established. Therefore, the buffers on the side of terminals 15+ to 15s connected to the SSW bus can be used as input/output buffers 14. to 14. as shown in the figure, so that they can be used for both input and output. ~148. However, since the input/output buffers 141 to 148 have a capacitive load of about 10 pF per terminal, the impedance seen from the terminal side is approximately 10 pF per terminal. The capacitive load increases and the fourth
A square wave like the one shown in Figure Fa) can also be generated by the square wave shown in Figure 4 (bl).
The waveform becomes a triangular wave as shown by the solid line, and as the capacitive load increases, the waveform becomes as shown by the broken line. This phenomenon is also related to the transmission speed of the transmitted signal, and the faster the speed, the more the waveform will be distorted as shown by the broken line.

[Problem to be solved by the invention]

As described above, in the conventional SSW circuit system, as the number of multi-connections of SSW circuits per SSW bus increases, the capacitive load increases, resulting in waveform distortion and the problem that the number of multi-connections is limited. . Also, therefore,
There is also a limit on the transmission speed, and higher transmission speeds (e.g. 3
It was difficult to realize a 2MH2) circuit.

In view of the above points, it is an object of the present invention to provide an SSW circuit system capable of solving the conventional problems and realizing an increase in transmission speed. To achieve this, the SSW circuit scheme of the present invention:
n input buffers to which reception signals are input, n output buffers to which transmission signals are output, a selection circuit connected to the output side of the n input buffers, and a selection circuit connected to the output sides of the n output buffers. The device is characterized in that it includes a distribution circuit connected to the input side, and a control circuit that controls the selection circuit and the distribution circuit.

[Effect]

According to the present invention, by changing the SSW circuit system from the conventional multi-connection system to a one-to-one connection system in which only the SSW function is made independent and concentrated in one place, connection restrictions due to waveform distortion due to capacitive load are eliminated. transmission speed can be increased.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an SSW bus system according to an embodiment of the present invention. The SSW bus method of this embodiment is as follows:
As shown in FIG. 1, an 8×16 (mXn) SSW circuit 1, eight input/output buffers 51 each consisting of an input buffer 5A to which a received signal is input and an output buffer 5B to which a transmitted signal is output. 58, and a control circuit 2 for controlling the SSW circuit 1, and this SSW circuit 1 is composed of an 8-1 type selection circuit 3 and a distribution circuit 4. In addition, the first
61.63-67 in the figure. is the reception signal input terminal, 6
□, 64-6.6 are transmission signal output terminals, 7a-7h are S
These are SSW terminals connected to the SW buses 20a to 20h, respectively, and the same reference numerals in the figure indicate the same or corresponding parts.

The operation of the configuration of the above embodiment will be explained below.

For example, when data is transmitted between the input/output buffer 5I and the human output buffer 5°, the received signal (■) and the transmitted signal (■) of the input/output buffer 51 are controlled by the control signal from the control circuit 2 to the SSW terminal 7a, respectively. 7b. As a result, the selection circuit 3 determines the signal path of the received signal (1) - terminal 7a and the transmitted signal (2) -1 terminal 7b. Similarly, input/output buffer 5. By controlling the received signal ■ and the transmitted signal [phase] to be connected to the SSW terminals 7b and 7a, respectively, the signal path of the received signal [phase] one terminal 7b and the transmitted signal [phase] one terminal 7a is connected to the distribution circuit. Confirmed at 4. Here, the SSW circuit 1 is an SSW circuit that can connect the signal lines of ① to [phase] in duplicate to the SSW terminals 7a to 7b. Therefore, as a result of the control by the control circuit 2, ■-7a-[phase], ■
By determining the route -7b-■, data transmission becomes possible between the input/output puffer 51 and the input/output puffer 58. If data is to be transmitted between further input/output buffers, an SSW terminal other than the already used terminals 7a and 7b is allocated and set.

〔Effect of the invention〕

As explained above, the present invention changes the SSW circuit system from the conventional multi-connection system to a one-to-one connection system in which only the SSW function is made independent and concentrated in one location. This has the effect that the connection limitations of SSW circuits are eliminated, and circuits with higher transmission speeds can be realized easily as long as the device speed of the SSW circuit allows.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing an example of a conventional system, and Fig. 3 is a block diagram showing an example of the conventional system.
A block diagram showing a specific example of the SW circuit, Figure 4 is the SS in Figure 3.
It is a signal waveform diagram in W bus. 1... SSW circuit, 2... Control circuit, 3... Selection circuit, 4... Distribution circuit, 5. ．． 52-58... Input/output cover/sofa, 5A... Input Hanofa, 5B... Output buffer, 6. ．． 63-61. ... Reception signal input terminal, 6□, 64-6.6 ... Transmission signal output terminal, 7a,
7b-7h...SSW terminal. Patent applicant: NEC Corporation Miyagi NEC Corporation

Claims (1)

[Claims] n input buffers to which received signals are input, n output buffers to which transmission signals are output, a selection circuit connected to the output side of the n input buffers, and a selection circuit connected to the output sides of the n output buffers. A space switch circuit system comprising: a distribution circuit connected to an input side; and a control circuit that controls the selection circuit and the distribution circuit.