JPH04130942A - Digital signal processor - Google Patents

Abstract

PURPOSE:To constitute constant data of an external ROM, etc., and to make this digital signal processor suitable for the small quantity and various sorts of digital signals by including a cache memory in the processor and inputting arithmetic data with high using frequency from an external memory space to process them. CONSTITUTION:The cache memory for storing constant data is newly added to th digital signal processing LSI mainly constituted of a computing element for executing logical operation and the operation of four arithmetic rules, a data memory for storing arithmetic data and an instruction memory for storing instruction data. These functions are mutually connected through internal paths to transmit data to be processed. The data memory is constituted of a high speed RAM for processing variable data whose values are sequentially converted in accordance with the result of arithmetic processing. The cache memory stores constant data for operation, i.e. coefficient data, as a substitute for a conventional ROM and its contents are read out on occasion. The address input signal line and data I/O signal lines of the cache memory are connected from both the inside and outside of the LSI.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a digital signal processing device, and relates to a technique that is effective when used in a device that performs real-time digital signal processing, such as a digital filter. .

[Conventional technology]

As a digital signal processing LSI (large-scale semiconductor integrated circuit device), the 'HD8' sold by Hitachi, Ltd.
1820 (DSP-E) J Kaal.

The outline of this digital signal processing LSI consists of an arithmetic unit that performs logic and four arithmetic operations, a multiplier that performs multiplication, a data memory that holds calculation data, and an instruction memory that holds instruction data. Each functional block is internally They are interconnected by a bus to transmit data to be processed. The data memory mentioned above is a high-speed RAM (
R that holds the random access memo and constant data (coefficient data) during calculations and reads them as necessary.
It consists of OM (read only memory).

[Problem to be solved by the invention]

In conventional digital signal processing LSIs, coefficient data for processing in the system to which it is applied is stored in a ROM, so that the numerical values cannot be changed after being commercialized and become fixed data. Therefore, as application systems become larger and the processing content becomes more complex and diverse,
In order to meet such demands, it is necessary to increase the capacity of the built-in data memory.

However, if the memory capacity of a car is increased, the circuit scale of the digital signal processing LSI becomes even larger, resulting in higher prices and a lack of reliability and versatility. In other words, it is unsuitable for application to small to medium-sized systems consisting of small quantities and a wide variety of products.

An object of the present invention is to provide a digital signal processing device suitable for a small to medium-sized system consisting of a wide variety of products in small quantities.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a cache memory is built-in, and frequently used calculation data is taken in from a ROM in an external memory space and processed.

[For production]

Since constant data can be configured using an external ROM or the like without using a cache memory to reduce calculation efficiency, it is possible to obtain a small-sized digital signal processing device suitable for production of a wide variety of products in small quantities.

〔Example〕

FIG. 1 shows a schematic block diagram of an embodiment of a digital signal processing device according to the present invention. Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using known semiconductor integrated circuit manufacturing techniques.

The digital signal processing LSI (large-scale semiconductor integrated circuit device) of this embodiment is basically the rHD81820 (DSP-E ) It consists of the same structure as J.

That is, the outline of the digital signal processing LSI of this embodiment includes an arithmetic unit that performs the same logic and four arithmetic operations as described above, a multiplier that performs multiplication, a data memory that holds operation data, and an instruction memory that holds instruction data. In addition to this, a cache memory that holds constant data is newly added.

Each of these functions is interconnected by an internal bus to transmit data to be processed.

The data memory mentioned above is an accumulative RAM (random) that handles variable data whose values are sequentially converted according to the results of arithmetic processing.
access memory). The cache memory is used as an alternative to the conventional ROM to hold constant data (coefficient data) during calculations and to read the data as needed. Address input signals and data input/output signal lines of this cache memory are provided both from inside and outside.

FIG. 2 shows a block diagram of one embodiment of the cache memory.

Cache memory can be broadly divided into an address search section and a data memory section. The address search section includes a directory memory that stores, as an address tag, the address signal of the upper few bits of the address on the main memory of the data stored in the same column position of the data memory.

Of the address signals given to the address bus ADB of the cache memory by an external instruction memory or the like, a column address portion is supplied to a common decoder of the directory memory and data memory.

As a result, the address tag from the directory memory and the data from the data memory are output simultaneously. Among these, from the data memory, there are no particular restrictions, but 1
A block of data is read out all at once and transferred to a buffer memory included in the data memory.

In the address search section, the address tag read from the directory memory is input to the tag comparison circuit. This tag comparison circuit has already been supplied with the address of the tag section among the addresses given from the instruction memory or the like. Therefore, when the address tag is output from the directory memory, the tag comparison circuit immediately performs a comparison operation and generates and outputs a signal HIT indicating whether it is a match (cash hit) or a mismatch (mishit).

If it is a queue hint, one block of data that is read from the corresponding column position of the data memory and transferred to the buffer memory, although not particularly limited, is specified by the lower two bits of the address. Word data is selected by a selector (not shown) and output through the data bus DATB1 or DATB2.

If there is a miss, an address signal is transmitted to the main memory bus through the internal address bus ADB, the external memory MM is accessed, and data is read. The data read from external memory is
The data is taken in through the data bus DATE1 or DATB2. Data reading from such external memory is also performed in block units. The data read from the external memory MM as described above is used as coefficient data etc. for digital data processing by the arithmetic unit or multiplier, and the address is stored in the directory memory of the address search unit. stored in memory.

In this embodiment, although not particularly limited, the data memory is configured to have three votes. That is, it has two ports for reading and one port for writing. This allows simultaneous write and read operations from three ports. For example, data Doutl output from one read port is connected to data bus DATB1, and data Doutl output from another read port is connected to data bus DATB1.
ut2 are respectively output to the data bus DATB2.

Furthermore, the data bus DATB3 is connected to the write port Din.
connected to.

FIG. 3 shows a circuit diagram of an embodiment of a memory cell having three ports as described above.

In the memory cell, a launch circuit is configured by an inverter circuit IV and a clocked inverter circuit CN2 that feeds back its output signal to the input side, and an input clocked inverter circuit CNI that transmits a write signal to the input terminal of the inverter circuit IN. provided. This clocked inverter circuit CN1 is an inverted write word! Activated by WW1. The feedback clocked inverter circuit CN2 is activated by the non-inverted write word 'aww1. That is, the complementary word line wwi,
Due to ww1, the input clocked inverter circuit CNI is activated during writing, and the feedback clocked inverter circuit CN2 is deactivated (output high impedance state), thereby inputting the write signal.

The output terminal of the inverter circuit IV has a first output terminal.
and second clocked inverter circuits CN3 and CN4 are provided. These clocked inverter circuits CN3.
CN4 is activated by the first read word line F*RW11 and the second read word line RW12. The output terminals respectively have dedicated read data 1RD1.
Connected to RD2.

By using such 3-boat memory cells, it becomes possible to read and write data more efficiently.
High-speed digital signal processing can be performed using a cache memory that occupies a relatively small area.

FIG. 4 shows a circuit diagram showing another embodiment of the address search unit and data memory.

In this embodiment, the directory memory and tag comparison circuit are configured using content recall memory.

That is, an address latch is formed by two inverter circuits whose inputs and outputs are cross-connected.

This address latch includes MO3FETQ5. An address signal is supplied from complementary input line D via Q6.

The address signal held in the latch circuit is MO3F for comparison.
Supplied to the gates of ETQ2 and Q4. In this case, the address holding signal is transmitted crosswise to the complementary input lines. MO3FETQ2 for comparison above. MO3FETQ1.Q4 receives the signal from the input line. Q3 is connected in series configuration. These series MO5FETs QI, Q2, Q3, and Q4 are provided in parallel to the select line SW and the ground potential point of the circuit. When the same address as the one input to D is input to the above input line, the comparison MO3FE
TQI, Q2, Q3 and Q4 are not turned on at the same time. On the other hand, if a different address is input, the series MO3FETQ1. Q2 or Q3. One of Q4 turns on at the same time and pulls the select wAsw down to the ground potential. A plurality of circuits as described above are provided in the select ISW, and when the input signals (address signals) of all bits match, the select line SW maintains a high level and outputs a selection signal (hit signal).

This output signal is directly used as a word constituting a data memory, and can be outputted from a memory cell coupled thereto. Alternatively, the select vAsw signal is
It may be used as a signal that validates and outputs the data read in parallel as described above.

In the digital signal processing device as described above, coefficient data is constituted by an external memory, and a cache memory is built inside, so that the coefficient data is retrieved from this cache memory during digital arithmetic processing. This makes it possible to ensure high-speed digital calculation processing in real time. In addition, because of its versatility, cache memory can be configured to have a small footprint, allowing for multi-functionality and special functions. Therefore, the digital signal processing layer Lsf can be configured with a relatively small circuit scale consisting of a data memory using a high-speed RAM, an instruction memory, and a cache memory.

As mentioned above, the data stored in the cache memory can be configured using an external memory, so it is sufficient to install a ROM suitable for multi-functions and multi-purposes, so it is possible to create a system consisting of a small quantity and a wide variety of products. It is easy to extend the functionality and apply changes.

The effects obtained from the above examples are as follows. In other words, (1) by incorporating a cache memory and importing and processing frequently used calculation data from external memory space, constant data can be configured in external ROM etc. without reducing calculation efficiency, so it is possible to store a small amount of data in large quantities. The effect is that a compact digital signal processing device suitable for the product type can be obtained.

(2) By using a multi-port memory as the cache memory, efficient reading/writing can be performed, resulting in the advantage of high-speed digital signal processing and the ability to reduce the circuit scale.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, part of the instruction memory may also be replaced with cache memory. In this case, it becomes possible to extend or change the digital signal processing itself from the outside, in other words, it becomes possible to extend or change the signal processing stage capability. In a digital signal processing device, multiplication, addition, etc. are repeated, so even if part of the instruction memory is replaced with a cache memory as described above, speeding up is unlikely to be hindered. The specific configuration of the built-in cache memory can take various embodiments. Further, the system configuration of the digital signal processing device itself can take various embodiments.

In addition, the built-in cache memory may be used as part of the data memory as described above, or may be used as a data memory as shown in the diagram in Figure 5.
(for variables and coefficients), or for redundant instruction memory. In other words, the circuit scale of each memory (memory capacity i
As t) increases, the probability of defective bits occurring increases accordingly. Therefore, cache memory CMI to CM3
When an address with a defective bit and correct data are stored in each memory, and the defective address is accessed in each memory, each cache memory CMI to CM
3 detects it and outputs the correct data. By doing so, the product yield can be significantly improved.

The present invention can be widely used in digital signal processing devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, by incorporating a cache memory and importing and processing frequently used calculation data from external memory space, constant data can be configured using external ROM etc. without reducing calculation efficiency, making it possible to produce a large variety of products in small quantities. A suitable compact digital signal processing device can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing an embodiment of a digital signal processing device according to the present invention, FIG. 2 is a block diagram showing an embodiment of a cache memory built in the digital signal processing device, and FIG. FIG. 4 is a circuit diagram showing one embodiment of a multi-vote memory cell used in the cache memory, FIG. 4 is a circuit diagram showing another embodiment of the data memory of the address search section, and FIG. 1 is a block diagram showing an embodiment of a digital signal processing device according to the invention; FIG. ADB...address bus, DATB 1 to DATB3...
・Data bus, iV...Imper circuit, CNI~C
N4...Clocked inverter circuit, Q1~Q8...M
OSFET, CMi to CM 3...Redundant cache memory

Claims (1)

[Scope of Claims] 1. A digital signal processing device characterized in that frequently used calculation data is fetched from an external memory space into a built-in cache memory and processed. 2. The digital signal processing device according to claim 1, wherein the calculation data is stored in a ROM provided in an external memory space. 3. The cache memory is provided with an input-only data line and an output-only data line, and is capable of simultaneous writing and reading within the same processing time. digital signal processing equipment.