JPH04130807A - Mos amplifier circuit - Google Patents

Abstract

PURPOSE:To prevent oscillation in a high frequency by including differential amplifier MOSFET, resistance means which are respectively provided for the drains of differential amplifier MOSFET and a load circuit provided through the resistance means. CONSTITUTION:A capacitor C1 provided between the drains of differential MOSFETQ1 and Q2 operates so that it suppresses the peak of the gain of the MOS amplifier circuit, which is generated when a capacitative load CL is connected. Namely, the capacitor C1 operates in such a way that it shorts the amplification output of a high frequency band component more than an interruption frequency f1 so as to cancel it. An input signal component consisting of a high band frequency band, which leaks from parasitic capacity CGD can be attenuated by setting the appropriate resistance value of resistances R1 and R2. Thus, a signal attenuation operation by the capacitor C1 and the resistances R1 and R2 synergistically operates and the gain can be reduced with the increase of the frequency, and danger that an oscillation phenomenon occurs can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS amplifier circuit, and particularly relates to a technique that is effective when used for driving a relatively large capacitive load.

[Conventional technology]

There is, for example, Japanese Patent Laid-Open No. 1-55771 as an operational amplifier circuit constituted by a CMOS circuit including a P-channel MOSFET (insulated gate field effect transistor, hereinafter the same) and an N-channel MOSFET.

The conventional phase compensation circuit has an output stage M as shown in FIG.
A phase compensation capacitor CF is provided between the gate and drain of OSFETQ7, in other words, between the output terminal Vout and the output terminal of the differential circuit.

[Problem to be solved by the invention]

When an operational amplifier circuit equipped with a phase compensation circuit as shown in FIG. 4 is connected in a voltage follower configuration, in other words, the output terminal Vout and the inverted input terminal Vin(
-), the high cutoff frequency is determined by the phase compensation capacitor CF between the gate and drain and the input differential MOS
The oscillation margin can be increased by setting the high cutoff frequency to a point with a large phase margin.However, in this case, the load capacitance The capacitance value of CL is limited to a very small value.

That is, as shown in the characteristic L4 shown in FIG. 5, the gain starts to attenuate from the high cutoff frequency f1, but
If the capacitance value of L is increased (then a large peak will appear at the frequency fp), if the gain peak that appears when a large capacitance is connected to the load is large, there is a risk that the operational amplifier circuit will oscillate. There is sex.

Furthermore, due to the parasitic capacitance COD between the gate and drain of the input differential MOSFET QI, in the region higher than the frequency f2,
Since the input signal leaks to the output side via the phase compensation capacitor CF, the gain is not sufficiently attenuated, which may cause oscillation depending on the load capacitance.

An object of the present invention is to provide a MOS amplifier circuit that avoids the risk of oscillation while driving a capacitive load having a large capacitance value.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this book (2) is as follows.

That is, M when a large capacitive load is connected to the output circuit.
In the OS amplifier circuit, a capacitor is provided between the drains of the differential amplifier MOSFETs, and/or the differential amplifier MOSFET is
Resistance means are provided at the drains of the SFETs and connected to the load circuit.

[For production]

According to the above means, the input signal leaked through the parasitic capacitance can be attenuated by the capacitor or resistance means provided at the drain of the differential MOSFET, and/or the gain of the differential amplifier circuit itself can be reduced. , the gain peak in the region higher than the high cutoff frequency can be suppressed, and the risk of oscillation can be avoided.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of an MO5 amplifier circuit according to the present invention. Each circuit element in the figure is manufactured using known CMOS integrated circuit manufacturing technology, especially 1iIJII.
! However, it is formed on a single semiconductor substrate such as single crystal silicon. In the figure, the P-channel MOS FET has its channel (pack gate)
By adding an arrow to the part, N-channel MO
Distinguished from SFET. This can be seen in Figures 2 to 4.
The same applies to the circuit diagram shown in the figure.

P-channel MOSFETs Ql and Q2 in differential configuration
The common source of is P, which acts as a constant current source.
A channel MOSFET Q9 is provided. In this embodiment, as mentioned above, the high cutoff frequency f1
In order to reduce the gain in the above high band, a capacitor C1 is provided between the drains. In addition, in order to attenuate the high-frequency signal passed through through the parasitic capacitance between the gate and drain of the differential MOSFET QI that receives the input signal Vin (+) when the voltage follower configuration is used, the differential MOSFET Q1. Resistors R1 and R are connected to the drain of Q2.
2 is connected. The drains of the differential MOSFETs QI and Q2 are connected via the resistors R1 and R2 to a current mirror type N-channel MOSFET Q, which constitutes a load circuit.
3. Q4 is provided.

The drain of the load MOSFETQ3, which is the output of the differential circuit, is supplied to the gates of an N-channel drive MOSFETQ5 and an output MOSFETQ7. A P-channel MOSFET QIO that acts as a constant current load is provided on the drain side of the drive MOSFET Q5, and its inverted signal is transmitted to the gate of an output MOSFET Q6 connected in a push-pull configuration to the output MOSFET Q7. That is, the output circuit of this embodiment is a so-called impartifed push-pull output circuit.

In this embodiment, a phase compensation capacitor C2 is connected between the gate and drain of the output MOSFET Q7, in other words, between the output terminal Vout and the output terminal of the differential circuit.
is provided.

Note that the reference constant current source 1o is passed through a P-channel MOSFET Q8 in the form of a diode, and this P-channel MOSFET Q8 is
By connecting OSFETQB and MOSFETQ9 and QIO in a current mirror configuration, MOSFETQ9 and QIO operate as a constant current source.

The capacitor C1 provided between the drains of the differential MOSFETs QI and Q2 acts to suppress the gain peak of the MOS amplifier circuit that occurs when a capacitive load CL is connected. That is, the capacitor C1 acts to short-circuit and cancel out the amplified output of the high frequency component above the cutoff frequency f1. Further, the input signal component in the high frequency band leaked due to the parasitic capacitance COD as described above can be attenuated by setting appropriate resistance values of the resistors R1 and R2.

As a result, the MOS amplifier circuit shown in FIG. 1 uses a voltage follower configuration in which the output terminal Vout and the inverted input terminal Vin() are read directly, and drives the load CL having a relatively large capacitance value. At this time, for high frequency components exceeding the high cutoff frequency f1 as shown in the characteristic Ll of FIG. 5, the capacitor C1 and the resistor R1,
The signal attenuation effect of R2 acts synergistically to reduce the gain as its frequency increases.

This can prevent the risk of oscillation occurring.

FIG. 2 shows a circuit diagram of another embodiment of the MOS amplifier circuit according to the present invention.

In this embodiment, the resistors R1 and R2 are omitted. Even when the resistors R1 and R2 are omitted, the gain limiting effect of the capacitor C1 allows the fifth
As shown by the characteristic L2 in the figure, the gain can be attenuated in the frequency band up to the frequency f2 at which the input signal passes due to the parasitic capacitance COD. In this case, since the gain is attenuated to some extent by the capacitor C1, even if the high-frequency component of the input signal passes through due to the parasitic capacitance COD as described above, it does not cause oscillation.

As in the embodiments of FIGS. 1 and 2 above, the capacitor C
1, resistors R1, R2, and capacitor CI, the MO5 amplifier circuit is in the form of a voltage follower as described above, and is suitable as a voltage generating circuit for driving a liquid crystal. That is, although not shown, the voltage divided by a series resistor circuit or the like is converted into impedance and output. Such a voltage can be used, for example, as a signal line drive voltage of a liquid crystal display device with an active matrix structure using thin film transistors. By the voltage divider circuit and the MO5 amplifier circuit in the form of a voltage follower, positive and negative driving voltages for lighting levels and driving voltages for non-lighting levels are formed centered on the voltage on the common electrode side of the liquid crystal panel, The data is selectively supplied to the signal line electrode in accordance with display data, and written to the pixel bridge of the selected scanning line. In this case, since the liquid crystal display device can be regarded as a load having a large capacitance value within the same flaw, the above-mentioned oscillation countermeasures are required. In addition to the active matrix structure described above, the liquid crystal display device may have a simple matrix structure in which pixels are formed at the intersections of scanning lines and signals.

FIG. 3 shows a circuit diagram of yet another embodiment of the MOS amplifier circuit according to the present invention.

In this embodiment, the capacitor C1 is omitted. Even when the capacitor C1 is omitted in this way, the resistors R1 and R2 attenuate the high frequency components of frequency 12 or higher, so the gain limiting effect causes the fifth
As shown in characteristic L3 in the figure, the gain can be attenuated in a frequency band of frequency 12 or higher where the input signal passes through due to the parasitic capacitance COD. This makes it possible to prevent oscillation caused by input signals passing through.

In addition, in the same figure, due to the load capacitance CL having a large capacitance value,
The gain peak is set at the frequency rp, but this peak decreases as the load capacitance becomes smaller.
The amplifier circuit is effective for circuits that use relatively light load capacitance. The signal attenuation operation by the resistors R1 and R2 is performed by the N-channel MOS that constitutes the load of the differential circuit.
FETQ3. The drain parasitic capacitance (not shown) of Q4 also acts to form a low-pass filter, which attenuates high-frequency components.

The effects obtained from the above embodiments are as follows. That is, (1) M when a large capacitive load is connected to the output circuit.
In the O8 amplifier circuit, a capacitor is provided between the drains of the differential amplifier MOSFETs, and/or resistor means are provided at the drains of the differential amplifier 4M05FETs, and the load circuit is connected through the resistor means. In particular, it is possible to reduce the amplified output signal of the differential amplifier circuit itself and/or attenuate the high-frequency components passed through the input parasitic capacitance by means of capacitors and resistors, thereby reducing the risk of oscillation in high bands above the cutoff frequency. This has the effect of avoiding sex.

(2) By providing a load circuit to the drain of each differential amplification MOSFET via a resistance means, differential MOSFET
Since it is possible to attenuate the high frequency input signal component that passes through the parasitic capacitance between the gate and drain of the SFET, it is possible to obtain the effect that oscillation at high frequency can be prevented.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples (although it is understood that various changes can be made without departing from the gist of the invention). Needless to say, for example, as an output circuit, the output MOSFET of the pushinable type as mentioned above is used.
Q6. In addition to those using Q7, these are omitted and MOSF
The configuration of the output circuit may be configured from ETQ5 and constant current load MOSFETQIO, or it may be configured using a Puchscheple output circuit with 0 MO8 configuration. You can have it. In addition, the load circuit of the differential amplifier circuit may be a current mirror type active load circuit, or may be composed of resistance means such as a load MOSFET.
In the embodiments of FIGS. 1 to 3, MOS F E
The conductivity type of T may be reversed, i.e.,
Differential MOSFET and constant current M provided in common source
The OS FET may be an N-channel MOSFET, and the load MOSFET may be a P-channel MOSFET.

The MO5 amplifier circuit according to the present invention can be widely used in devices that drive a relatively large capacitive load, or devices that require amplification operation up to high frequencies, in addition to the above-mentioned liquid crystal drive voltage generation circuit. be able to.

〔Effect of the invention〕

A brief explanation of the results obtained by typical inventions disclosed in this application is as follows. In other words, MOS in which a large capacitive load is connected to the output circuit
In the amplifier circuit, a capacitor is provided between the drains of the differential amplification MOSFETs, and/or a resistance means is provided at each drain of the differential amplification MOSFET, and a load circuit is connected through the resistance means. Therefore, it is possible to lower the amplified output signal of the differential amplifier circuit itself and/or attenuate the high-frequency components passed through the input parasitic capacitance using capacitors or resistive means, so there is a risk of oscillation in a high band above the cutoff frequency. can be avoided. Furthermore, by providing a load circuit to the drains of the differential amplification MOSFETs via resistive means, it is possible to attenuate the high-frequency input signal components that pass through via the parasitic capacitance between the gate and drain of the differential MOSFETs. , it is possible to prevent oscillation at high frequencies.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the Pwl 0 S amplifier circuit according to the invention, FIG. 2 is a circuit diagram showing another embodiment of the MOS amplifier circuit according to the invention, and FIG. 3 is a circuit diagram showing another embodiment of the MOS amplifier circuit according to the invention. , a circuit diagram showing still another embodiment of the MOS amplifier circuit according to the present invention, No. 41j! j is a circuit diagram showing an example of a MOS amplifier circuit using a conventional phase compensation circuit, and FIG. 5 is a gain-frequency characteristic diagram for explaining the operation of the MOS amplifier circuit of the present invention. Q1~Q7...MOSFET, R1, R2...resistance, C
Engineering: Capacitor, C2, CF: Phase compensation capacitor, CL: Load capacitance.

Claims (1)

[Claims] 1. Differential amplification MOSFET and these differential amplification MOSFETs
1. A MOS amplifier circuit comprising resistance means provided at the drains of the ETs, and a load circuit provided via the resistance means. 2. Differential amplification MOSFET and these differential amplification MOSFETs
a capacitor provided between the drains of the ET; a load circuit provided at the drains of the differential amplification MOSFET;
and an output circuit that receives an output signal obtained from the load circuit and drives a relatively large capacitive load. 3. Differential amplification MOSFET and these differential amplification MOSFETs
A capacitor provided between the drains of the ET, a resistance means provided at each of the drains of the differential amplification MOSFET, a load circuit provided via the resistance means, and an output signal obtained from the load circuit. and an output circuit for driving a relatively large capacitive load in response to a MOS amplification circuit. 4. The above load circuit is an MO connected in a current mirror configuration.
3. The MOS amplifier circuit according to claim 1, wherein the MOS amplifier circuit is comprised of an SFET.