JPH04130396A - Method for driving plasma display panel - Google Patents

Abstract

PURPOSE:To reduce the cost of a plasma display panel by the lowering of the breakdown strength proof of a circuit element by always impressing a bias voltage equal to or under a discharge starting voltage on an address electrode and impressing the address voltage over the discharge starting voltage on the address electrode at the time of selecting light emission. CONSTITUTION:The discharge maintaining pulse of a negative polarity and the bias voltage of a positive polarity equal to or under the discharge starting voltage are always impressed on main discharge electrodes 13 and 14 and the address electrode 22, respectively. At the time of selecting light emission in a unit light emitting area, the write pulse of the negative polarity is impressed on the electrode 13 instead of the discharge maintaining pulse and the address voltage over the discharge starting voltage is impressed on the electrode 22. Thus, discharge is caused at the intersection of the electrodes 22 and 13. The discharge of a discharge maintaining electrode pair 12 is caused by the discharged charge, and the light emission in the unit light emitting area is kept by the following discharge maintaining pulse. At such a time, it is necessary to control the voltage of a value obtained by subtracting the bias voltage from the address voltage for the electrode 22, and the charge amount accumulated on the electrode pair 12 side is restrained to such an extent that self erasing discharge is not caused.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method for driving a plasma display panel that performs matrix display using a pair of discharge sustaining electrodes and three address electrodes, which reduces the cost of the plasma display panel by lowering the withstand voltage of driving circuit elements. A method for driving a plasma display panel having a discharge sustaining electrode pair consisting of a pair of main discharge electrodes and an address electrode perpendicular to the sustaining electrode pair, the method comprising: It is constructed by constantly applying a bias voltage and applying an address voltage exceeding the discharge start voltage to the address electrode when selecting light emission of a unit light emitting region.

(Industrial Application Field) The present invention relates to a plasma display panel that performs matrix display using a pair of discharge sustaining electrodes and an address electrode 31 as poles.

Plasma display panels (FDP) have excellent display visibility among flat display devices, and are rated at 0A.
Applications are being expanded to include II devices.

Along with this, it is possible to perform multi-gradation color display,
And low cost is desired.

[Prior Art] Conventionally, in AC-type (alternating current drive type) PDPs that use a dot matrix display system to display characters and figures by combining dots (pixels) that emit light, it has been possible to increase the 2. Description of the Related Art Surface discharge type PDPs that are capable of color display are known.

A surface discharge type FDP has a discharge sustaining electrode pair consisting of a pair of main discharge electrodes that define a main discharge cell, and an address electrode that is orthogonal to the discharge sustaining electrode pair. By selective discharge cells defined at the intersection points,
It is configured to select (address) the light emission of the phosphor corresponding to the unit light emitting area.

Generally, a surface discharge type FDP is driven as follows.

First, a voltage exceeding the discharge start voltage is applied to the discharge sustaining electrode pair to start the discharge of the main discharge cells line by line, and then a discharge erase pulse (
A selective discharge cell corresponding to a main discharge cell unnecessary for display is applied by applying an address pulse), and the wall charge of the dielectric layer covering the discharge sustaining electrode pair is erased to stop the discharge.

A discharge sustaining AC voltage having a peak value lower than the discharge starting voltage is applied to the discharge sustaining electrode pair, and the discharge is continued in the main discharge cell corresponding to the display pixel due to the wall charge accumulated in the dielectric. As a result, the phosphor corresponding to the main discharge cell during discharge is excited by the ultraviolet rays generated by the discharge and emits light.

[Problem to be solved by the invention]

As mentioned above, in the conventional driving method, the address electrode is set at a potential (approximately 100 ports) at which a discharge occurs in a selected discharge cell by application of an address pulse during addressing, but is set to the ground potential (approximately 100 ports) at times other than addressing. 0 Porto).

For this reason, when configuring the drive circuit, it is necessary to use circuit elements with withstand voltage characteristics of 100 volts or more as circuit elements such as switching transistors for applying address pulses, which makes the drive device expensive. There was a problem.

Furthermore, conventionally, the discharge of the main discharge cell SC, which is unnecessary for display, is stopped by utilizing the re-discharge (self-erasing discharge) of the selective discharge cell WC caused by wall charges excessively accumulated due to the discharge of the selective discharge cell. Another problem was that the address electrode and the phosphor were bombarded with ions during the self-erasing discharge.

Furthermore, in conventional addressing, a two-stage discharge side (m) (applying two pulses) is performed in which the discharge of unnecessary main discharge cells is stopped after emitting light on a line-by-line basis.
Another problem was that it took a long time to complete an address.

In view of the above-mentioned problems, the present invention aims to reduce the cost of plasma display panels by lowering the withstand voltage of driving circuit elements.

Moreover, the invention of claim 2 aims to extend the life of a plasma display panel by reducing ion bombardment.

Furthermore, the invention of claim 3 aims at increasing the speed of addressing.

[Means to solve the problem]

In order to solve the above-mentioned problem, the driving method according to the invention of claim 1 includes a discharge sustaining electrode pair 12 consisting of a pair of main discharge electrodes 13 and 14, as shown in FIGS. A method for driving a plasma display panel 1 having address electrodes 22 orthogonal to each other, the address electrodes 2
2. A bias voltage Vb lower than the discharge start voltage Va is always applied to the address electrode 22, and when the unit light emitting area EU is selected to emit light, an address voltage VA exceeding the discharge start voltage Va is applied to the address electrode 22. In the driving method according to the invention, as shown in FIG. 2, the address voltage VA is applied to the address electrode 22 via a current limiting resistor 53.

In the driving method according to the invention of claim 3, as shown in FIGS. 1 and 3, negative polarity is normally applied to each of the main discharge electrodes 13 and 14 of the discharge sustaining electrode pair 12 alternately and periodically. While applying the sustaining pulse SP, a positive bias voltage v lower than the discharge starting voltage Va is applied to the address electrode 22.
b is applied, and when selecting light emission of the unit light emitting region EU, a negative write pulse WP is applied to the one main discharge electrode 13 in place of the discharge sustaining pulse SP.

[For production]

Normally, each main discharge electrode 13.14 of the discharge sustaining electrode pair 12
, negative polarity sustaining pulses SP are alternately and periodically applied.
is applied, and a positive bias voltage vb lower than the discharge starting voltage Va is applied to the address electrode 22.

When selecting light emission in the unit light emitting area EU, a negative write pulse WP is applied to one of the main discharge electrodes 13 instead of the sustaining pulse SP, and an address voltage VA exceeding the discharge starting voltage Va is applied to the address electrode 22. This causes a discharge to occur at the intersection of the address electrode 22 and the main discharge electrode 13.

Then, the electric charge generated by the discharge causes the discharge sustaining electrode pair 12 to
A discharge occurs, and by the subsequent discharge sustaining pulse SP,
The unit light emitting area EU continues to emit light.

In other words, one stage of discharge control B (one pulse application)
The light emission of the unit light emitting area EU is selected by.

At this time, for the address electrode 22, it is sufficient to control the voltage equal to the value obtained by subtracting the bias voltage vb from the address voltage VA, and the voltage applied to the address electrode 22 decreases by the voltage drop across the resistor 53 due to the discharge current, causing a discharge. By limiting the current, the amount of charge (ions) accumulated on the discharge sustaining electrode pair 12 side is suppressed to an extent that self-erasing discharge does not occur.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a plan view of the PDP I according to the present invention, and FIG. 4 is a sectional view taken along the line IV-mV in FIG.

In these figures, the PDPI includes a glass substrate 11 on the display side, a plurality of discharge sustaining electrode pairs 12 consisting of a pair of main discharge electrodes 13 and 14 extending in the X (horizontal) direction on the inner surface of the glass substrate 11, and a dielectric layer. 17. A lattice-shaped partition 19, a glass substrate 21 on the back side, a plurality of partitions 29 extending in the Y (vertical) direction on the inner surface of the glass substrate 21, address electrodes 22 provided between each partition 29, and mutually emitting light. Phosphors of different colors 28
R, 28G, 28B, etc., and in FIG. 4, the upper surface of the glass substrate 11 becomes the display surface 1o.

The internal discharge space 30 is filled with a mixed gas of neon and quinanone, for example, and this discharge space 30 is partitioned by partition walls 19 and 29 for each unit light emitting area EU.

In PDP 1, the phosphors 28R, 28G and 28B are
For example, an appropriate amount of indium oxide (IngOs) is mixed into a fluorescent substance of a predetermined luminescent color to make it a conductor, and it is provided so as to cover the entire surface of the address electrode 22. As a result, in the PDPL, as clearly shown in FIG. 1, the phosphors 28R, 280, and 28B are present in the entire area surrounded by the partition wall 19 in each unit light emitting area EU, and the display The brightness is high.

The main discharge electrodes 13 and 14 are transparent electrodes made of a Nesa film (tin oxide), and a bus electrode (not shown) is superimposed on the back side in order to lower the line resistance value.

Further, a protective film made of MgO (not shown) is provided on the surface of the dielectric layer 17.

In the PDP 1 configured as above, the discharge space 30
Each of the phosphors 28R and 28G is placed at the intersection of the main discharge electrode 13 and the address electrode 22, which face each other via the phosphors 28R and 28G.

A selective discharge cell WC for selecting (addressing) 28B is defined, and selected phosphors 28R, 28G, and 28B are placed on mutually opposing portions of the main discharge electrodes 13.14 in the vicinity of the selective discharge cell WC. A main discharge cell SC for emitting light is defined. As a result, the phosphors 28R, 28G
, 28B that correspond to each unit light emitting area EU can be made to selectively emit light. However, PDP
1, to perform multicolor display for each pixel,
One pixel has a predetermined number (for example, three) of unit light emitting areas E.
U, that is, phosphor 28R128G, 2 with multiple emission colors
8B, and these phosphors 28R, 28G, 2
The display color of the pixel is determined by the combination of the 8B light emissions.

Next, a method of driving the PDP 1 will be explained.

FIG. 1 is a diagram showing an example of a drive voltage waveform of a PDPI according to the present invention, and FIG. 2 is a circuit diagram of a drive output section 50 of the address electrode 22.

The drive output unit 50 is connected to an address power supply line (power supply voltage V
A is about 90 to 100 volts) and a ground line (0 volts) are connected in series with a switching transistor 52, a current limiting resistor 53, and a bias power supply 54.
Consists of etc. The transistor 52 performs a switching operation according to an address signal SA input from a drive logic circuit (not shown) via a coupling capacitor 51.

The address electrode 22 is connected to a connection point p between the resistor 53 and the bias power supply 54, and the bias voltage vb of the bias power supply 54 is always applied to the address electrode 22. Accordingly, the withstand voltage value of the transistor 52 only needs to be equal to or higher than the voltage value obtained by subtracting the bias voltage vb from the power supply voltage VA. Therefore, in the drive output section 50, it is possible to use an inexpensive transistor 52 with a lower withstand voltage than in the case where the bias power supply 54 is not provided.

Note that this drive output section 50 is provided for each address electrode 22.

In FIG. 1, each main discharge electrode 13.14 of the discharge sustaining electrode pair 12 (see FIG. 3) is normally supplied with negative sustaining voltage pulses SP (pulse width is tl) alternately and with a peak value VS. Applied periodically.

Here, a sustaining voltage pulse sp is applied to the main discharge electrode 13.
Instead, a negative write pulse WP with a peak value Vw (Vw>Vs) is applied, and an address pulse AP is applied to the transistor 52 to turn on the transistor 52.

When the transistor 52 is turned on, the voltage applied to the address electrode 22 increases from the bias voltage vb according to the time constant of the address electrode 22. When the voltage of the address electrode 22 reaches the discharge starting voltage Va of the selected discharge cell WC, a discharge occurs in the selected discharge cell WC defined at the intersection of the address electrode 22 and the main discharge electrode 13 to which the write pulse WP has been applied. Wall charges are generated on the dielectric layer 7 covering the main discharge electrode 13.

At this time, in the drive output section 50, the resistance 5 due to the discharge current
The potential at the connection point p decreases by the voltage drop of 3, and the discharge current is limited.

Thereby, the amount of charge accumulated in the dielectric layer 17 is suppressed to such an extent that self-erasing discharge does not occur in the selective discharge cell WC.

Then, when the sustaining voltage pulse SP is applied to the other main discharge electrode 14, a discharge occurs in the main discharge cell SC due to the wall charges accumulated on the main discharge electrode 13 side. The discharge of the main discharge cell SC occurs every time a sustaining voltage pulse SP is applied until an erase pulse with a pulse width of t2 is applied to each main discharge electrode 13, and the ultraviolet rays generated by the discharge cause the corresponding phosphor 28R to discharge. , 28G, and 28B are excited and emit light.

That is, in PDPI, by applying the address pulse AP to the transistor 52 simultaneously with the application of the write pulse WP to the main discharge electrode 13, addressing is performed with one pulse output in terms of timing.

According to the embodiment described above, it is possible to start the light emission of the unit light emitting area EU by one stage of discharge control, and in parallel with the start of the light emission, it is possible to stop the light emission of the other unit light emitting areas EU. Therefore, it is possible to speed up the display operation and realize high-quality multi-gradation display.

According to the above-described embodiment, since the bias voltage vb lower than the discharge starting voltage Va is always applied to the address electrode 22, a plurality of open collector circuits made of switching elements such as low voltage transistors 52 and field effect transistors are used. Alternatively, the discharge of the selective discharge cell WC can be controlled by an inexpensive IC that integrates an open drain circuit, and the cost of the drive output section 50 can be reduced. Further, when the potential of the address electrode 22 changes according to a time constant, the time from application of the address pulse AP until the potential of the address electrode 22 reaches the discharge starting voltage Va can be shortened.

According to the embodiment described above, by providing the resistor 53,
Since self-erasing discharge in the selective discharge cell WC is prevented, scattering of the phosphors 28R, 28G, and 28B due to ion bombardment is suppressed. In particular, in PDPl, the phosphor 28R,
28G and 28B have conductivity, and phosphor 28R,
When 28G and 28B scatter and adhere to the dielectric 17,
There is a risk that wall charge will leak and the display operation will become unstable. Therefore, by suppressing the scattering of the phosphors 28R, 28G, and 28B, the phosphors 28R92B (1,
, 28B, and the display operation becomes stable.

In the above embodiment, the discharge sustaining electrode pair 12 is provided on the glass substrate 21 on the back side, and the address electrode 22 and the phosphor 28
R, 28G, and 28B may be provided on the glass substrate 11 on the display surface side. In that case, it is desirable that the address electrode 22 be a transparent electrode.

In the above embodiment, the driving conditions such as address power supply voltage VA, bias voltage vb, peak values Vs and Vw are as follows.
It can be appropriately selected depending on the size, shape, structure, etc. of PDP1.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the cost of a plasma display panel by lowering the breakdown voltage of driving circuit elements.

According to the second aspect of the invention, it is possible to extend the life of the plasma display panel by reducing ion bombardment.

According to the third aspect of the invention, it is possible to speed up the selection of light emission in a unit light emitting area.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the drive voltage waveform of the PDP according to the present invention, FIG. 2 is a circuit diagram of the drive output section of the address electrode, FIG. 3 is a plan view of the FDP according to the present invention, and FIG. IV- in Figure 1
It is a sectional view taken in the direction of the IV arrow. In the figure, 1 is an FDP (plasma display panel), 12 is a pair of sustaining electrodes, 13.14 is a main discharge electrode, 22 is an address electrode, 53 is a resistor, EU is a unit light emitting area, SP is a sustaining pulse, and VA is a sustaining electrode. Address voltage, Va is discharge start voltage, vb is bias voltage, wp is write pulse. 13.14 Main discharge electrode 22 Address electrode Eυ Unit light emitting area Plan view of FDP according to the present invention FIG. 4 Cross-sectional view taken along the IV-IV arrow in FIG. 1

Claims (3)

[Claims] (1) A discharge sustaining electrode pair (12) consisting of a pair of main discharge electrodes (13) and (14), and an address electrode (
22) A method for driving a plasma display panel (1) having a unit light emitting area ( EU), the discharge starting voltage (Va) is applied to the address electrode (22).
A method for driving a plasma display panel, the method comprising applying an address voltage (VA) exceeding . (2) Set the address voltage (VA) to the current limiting resistor (
5. The method of driving a plasma display panel according to claim 1, wherein the voltage is applied to the address electrode (22) via a voltage source (53). (3) A discharge sustaining electrode pair (12) consisting of a pair of main discharge electrodes (13) and (14), and an address electrode (
22), wherein the discharge sustaining electrode pair (12)
A negative discharge sustaining pulse (SP) is applied alternately and periodically to each of the main discharge electrodes (13) and (14), and a discharge starting voltage (Va) is applied to the address electrode (22).
Apply the following positive bias voltage (Vb),
When selecting light emission for a unit light emitting area (EU), one of the main discharge electrodes (13) is used instead of the sustaining pulse (SP).
A method for driving a plasma display panel, characterized in that a write pulse (WP) of negative polarity is applied to the address electrode (22), and an address voltage (VA) exceeding the discharge start voltage (Va) is applied to the address electrode (22).