JPH04127822A - Protective relay - Google Patents

Abstract

PURPOSE:To improve the characteristic change by frequency fluctuation and get highly accurate judgment results even against the frequency fluctuation being the object of failure detection by removing the sampling time width and the second harmonic from the sampling values of current and voltage. CONSTITUTION:The principal part comprises a distribution path 1 for current data, a distribution path 2 for voltage data, temporary storage rooms 3-5 for current data, temporary custody rooms 6-9 for voltage data, multiplication circuits 11-14, addition circuits 15 and 16, a multiplication circuit 17, circuits 18 and 19 for deforming the quantities of electricity, a subtraction circuit 20, a division circuit 21, a substitution circuit 22, a part 23 for guiding out quantity for judgment, and others. The integrated quantity of the sampling data of the current and the voltage of a power system is guided out to get first quantity of electricity and the second quantity of electricity, and out of the components of that quantities of electricity, the components related to the sampling time width and the second harmonic are removed from the phase difference component. The quantity of electricity becomes only the components related to the phase difference of current and voltage, and the characteristic not accompanied with against frequency fluctuation can be gotten.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a protective relay for protecting an electric power system.

[Conventional technology]

Figure 11 shows, for example, "Electric Kyodo Research, Vol. 41, No. 4,
FIG. 4 is a diagram for explaining the algorithm of the conventional digital operation type power direction relay shown in the system and product form C of Table 4-13 of "Digital Relay" P45.

The following formula is shown in the first table as a calculation principle formula for obtaining the power direction.

"l/1lflcosθ=Vs4a+Vs-1'1m-
:+...(1) Here, m-3 on the right side is data at a time 3 samples before time m, indicating the case of 30'' sampling, and data at times separated by 90 degrees in electrical angle. It shows that there is.

Next, the operation of equation (1) as a power direction relay will be explained.

Now, if the amount of electricity input to the relay is expressed as shown in Fig. 11, equations (2) and (3) are obtained.

i (t) −1, sin (ωot)
・−= (2) v(t) −Vp sin
(ωot+θ) (3) Here, ω at sampling point m. If the value of t is α, each sample value is i, −I9sinα (4
)V, =v, sin (α+θ) ・
−...−(5), the sample value at time m− is i s−k = 1.5in (β at cr−)
......(6) V114-V, 5in (α- to β
+θ) −−−−−・It is given by (7).

However, β: sampling time (interval) width θ: lead angle of voltage when the current is referenced: k=L 2.3.・・・
・It is.

If we pay attention to the right side of equation (1), we get the following.

Vp' 1s + Vs-2' 1m-3=Vpsin (
α+θ)・Ipsinα+Vpsin(α−3β+θ)
・1.5in(cr-3β)=VpI, (sin(α
10θ) sin a+5in(α+θ−90@) sin(
α-90″)1=V, I, (sin(α+θ)sinα
+cos(cr+θ)CO5α)-Vjp CO5θ
(8) The principle of this calculation is that the system frequency and the sampling time width β are always in a constant relationship, and the sampling value at time m is a sine (
If it is a sin) component, it is constructed based on the fact that the sampling value before the specified sample (in the above explanation, it means data separated by 90 degrees) can be expressed by a cosine (cos) component. It is something that

Therefore, in the 50 Hz system, the sampling time width β is β. Therefore, in the 60 Hz system, strict control of the sampling time width β is required, including β6°.

[Problem to be solved by the invention]

Conventional protective relays are configured as described above, so
The system frequency is always constant, and in order to establish a digital relay for boat fishing, the frequency must be 50Hz, 60Hz.
The calculation principle formula is constructed on the premise that it is necessary to accurately determine the sampling time width β in accordance with Hz.

For this reason, the premise of formula % is broken and the equality sign no longer holds true for frequency fluctuations in the grid, and the error becomes large based on the calculation principle, resulting in a non-negligible effect on protection ability. In addition to this, there were other problems such as the need to change the sampling time width β at frequencies of 50 Hz and 60 Hz.

Furthermore, depending on the system frequency, the sampling time width β
must be set to a multiple of 30°, and in the case of equation (8), in order to obtain an effective calculation result as a power direction relay, the electrical angle must be set to 90° (4.167 m5 on a 60Hz base).
, 5m5 on a 50Hz basis) is required (ignoring the time required for processing by the processing device),
With conventional calculation principles, it is difficult to shorten the detection time any further, and there is a problem that the detection time is almost at its limit for high-speed operation.

This invention was made to solve the above-mentioned problems, and it not only improves characteristic changes (errors) due to frequency fluctuations, but also provides highly accurate judgment results even with frequency fluctuations in the system targeted for accident detection. The object of the present invention is to obtain a protective relay that can perform arithmetic processing for both frequencies of 50 Hz and 60 Hz.

Furthermore, it can be used in systems where the frequency fluctuates slowly, such as when starting up a hydraulic power generator, and it is possible to set the sampling time width independent of the system frequency, that is, to create a protective relay that can operate at high speed. The purpose is to obtain.

[Means to solve the problem]

The protective relay device according to the present invention includes a temporary storage room for current data that samples voltage data and current data obtained by detecting voltage and current of a power system during a predetermined sampling time, quantizes the data, and temporarily stores the detected voltage data and current data. Define a temporary storage room for data, the sampled values of current and voltage stored in the temporary storage room, and the calculation order, and output the first electrical quantity and the second electrical quantity by the arithmetic circuit that performs the processing. and a first sampling calculation formula whose dividend is the product of the square of the amplitude value of the current and the amplitude value of the voltage of the power system. A determination for determining whether a power direction component obtained by dividing by a second electrical quantity consisting of a second sampling calculation formula having the amplitude value of the voltage of the power system as a divisor is greater than zero and outputting the result. A quantity deriving section is provided.

[For production]

The protective relay in this invention derives the product of sampling data of current and voltage of the power system to obtain a first quantity of electricity and a second quantity of electricity, and three components of the quantity of electricity, namely, current, Components related to the voltage phase difference (θ), components related to the second harmonic (α), and sampling time width (β)
Among the components related to the phase difference, the components related to the sampling time and the second harmonic are removed from the phase difference component, and the order of the input sampling data is controlled so that only the components related to the phase difference of current and voltage remain. Characteristics without errors can be obtained even with frequency fluctuations.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. First, the principle of operation of the present invention will be explained with reference to FIG. In the figure, ■ is a distribution path for digitally quantified current data, 2 is a distribution path for voltage data, 3 to 5 are temporary storage rooms for current data, 6 to 9 are temporary storage rooms for voltage data, and 10 is a data Distribution path, 11 to 14 are multiplication circuits, 15
．． 16 is an addition circuit, 17 is a multiplication circuit, 18 and 19 are electrical quantity transformation circuits, 20 is a subtraction circuit, 21 is a division circuit, 22 is a substitution circuit, and 23 is a determination quantity deriving section.

Next, the operation will be explained. First, the current and voltage data distribution paths 1 and 2 each have a digital data string...I@+
1m. 3. i. 2. ...and...vIII-2+
...v, +V@+1 Vll. 2... are flowing in synchronization with the sampling time width β, and current and voltage data temporary storage rooms 3 to 9 currently have i, respectively.

g+Jm+++1+a + Va4Z + v,,
+ Va + vll-2 is stored.

The loading and unloading of data stored in this storage room is controlled by another control system (not shown).

For example, current data i is the latest data. , appears in the current data distribution path 1 (of course, it goes without saying that voltage data v, +3 also appears in the voltage data distribution path 2 in synchronization with this), the temporary current data In the storage room 5, the current data i, is cleared, and the data i,...
1 is stored, data i0.1 is cleared in the current data temporary storage room 4, and data i,. Store 2. Similarly, in the current data temporary storage room 3, i.

, will be stored.

At this time, the data in the temporary storage chambers 6 to 9 for voltage data is cleared and stored in synchronization with another control system, as in the case of current data. That is, data ■,. , is stored in the storage room 6, the data V, is stored in the voltage data temporary storage room 7. 2, and data V in the voltage data temporary storage room 8. 1, and data v and -1 are stored in the voltage data temporary storage chamber 9, respectively.

The multiplication circuits 11 to 14 obtain data from a temporary storage room for each data via the data distribution path 10, derive inner product values, and output the respective data.

First, the multiplication circuit 11 derives the volume 1m+zV* from the data obtained from the data temporary storage room 3°8, and the multiplication circuit 12
is the data obtained from temporary data storage rooms 4 and 7.
1@+1V11°1 is derived, and the multiplication circuit 13 calculates the product 1@V@+2 with the data obtained from the temporary data storage rooms 5 and 6.
The multiplier circuit 14 derives the product 2va from the data obtained from the data temporary storage room 8, and the adder circuit 15
is the data obtained from the temporary data storage rooms 6 and 9, and the amount of data V
,. 20v and -z are respectively derived and output.

The adder circuit 16 inputs the outputs of the multiplier circuits 11 and 13, respectively, and calculates Ie+rV+a+ l1IVII4□ =1. Vp(sin(cr +2β)sin(α+θ)
+sinα5in(α+2β+θ)) =1.11. (cosθcos2β−cos (2α
+2β+θ)) ・(9) is derived and output.

The multiplier circuit 17 inputs the output of the multiplier circuit 12 and calculates 2is++Vs*+ −=2rpv, 5in(α+
β) sin (α ten β + θ) − IpVp (cos θ − c
os(2α+2β+θ))... (lO) is derived and output.

The division circuit 21 inputs the outputs of the addition circuit 159 and the multiplication circuit 14, respectively, and calculates the following equation: =cos 2β .
(11) is derived and output (however, V 5in
(α+β)≠0, ■, ≠0).

The electric quantity transformation circuit 18 inputs the output of the adder circuit 16, and calculates IpV, cos(2α+2β+θ) −I, V, cosθ(os2β−(1s+zVs+1
1IV+a+z)... (12) The right side is derived and output by transforming it as shown below.

The electric quantity transformation circuit 19 inputs the output of the multiplication circuit 17, and calculates the following equation: IpVpcos(2α+2β+θ) =IpV, cosθ−2i, , IV+e+1 +
+++ Transformed as shown in (13), the right side is derived and output.

Further, the subtraction circuit 20 inputs the outputs of the electrical quantity transformation circuits 18 and 19, respectively, and calculates 1, V, cos (2α + 2β + θ) −IpV,
cos (2o: +2β+θ)=(1,Vpcos
θcos2β−(Ie+zVs+ LVa+z) )−
(1, V, cos θ-2i, , v, , + ) −
−(14) That is, i, V, cos B == (1s+zVn +
1mVm+z) 21+*++V-◆1cos
2β-1 ...... (14-1) is derived and output (however, cos 2β-1≠0
). The left side of equation (14) is naturally zero.

The substitution circuit 22 is connected to the subtraction circuit 20 . Using the outputs of the division circuit 21 as inputs, 2ν1 :vllllya2-2vlI+v, -□(i 翔+2vII
+i−ν−+22i−◆ν7. , ) ...... (15) is derived and output (however, V..., -2!v, +
v, -z≠0. ■, ≠0).

The judgment amount deriving unit 23 uses the output rpV, co of the substitution circuit 22.
sθ is derived.

In the above description, the case is described in which the denominator in each arithmetic expression does not become zero, but it goes without saying that if the denominator becomes zero, separate processing such as discarding the arithmetic aggregation is performed.

Although not shown, this amount is controlled so that the output contact as a protective relay is closed when the following conditions are satisfied.

I, V, cos θ ≧ 0 (15-1)
Here, as shown in the subtraction circuit 20, the second harmonic component when the inner product value of current and voltage is obtained is eliminated by the difference, and the component cos 2β of the sampling time width is independently derived.
co of the amount obtained as the inner product value of current and voltage in the substitution circuit 22
By substituting into s 2β, the equation (15) is obtained.

In other words, the gist of the present invention is to obtain sampled values of current and voltage, and use the sampled values to calculate the numerator on the right side of equation (15) using the required circuit. The calculation formulas vary and the shape of the molecule changes. ), as the first quantity of electricity, 1, V-・5in (cr + θ) cos θ (cos 2β
-1) is derived.

Also, calculate the denominator to derive the second electrical quantity ■, 5in (α + β) (cos 2β - 1) (but not zero), and divide the first electrical quantity by the second electrical quantity. Obtained power direction component 1. V.

It is determined whether cos θ is greater than zero or not based on a determination criterion, and the output of the protective relay is obtained.

Here, the current of the first and second electric quantity calculation formulas.

The related terms of cos 2β related to the component related to the phase difference (θ) of the voltage and the component related to the sampling time width (β) are referred to as follows.

sin (α+β) cos θ(cos 2β−1)
is the first sampling calculation formula sin (α+β) (cos 2β−1) is the second sampling calculation formula.

An embodiment of the present invention (an implementation example of the right-hand side of equation (15)) will be described below.
Explain the diagram. In FIG. 10, the same parts as in FIG. 1 are denoted by the same reference numerals. Reference numeral 31 denotes an adder circuit, which inputs the outputs of multiplier circuits 11 and 13, respectively, i,. ZV11+111V11°2 is derived and output.

32 is a subtraction circuit, and a multiplication circuit 14. With the outputs of the adder circuits 15 as inputs, (1) and 1). z 2v*+ν1°2 is derived and output.

33 is a division circuit, and a multiplication circuit 14. The outputs of the subtraction circuits 32 are used as inputs, and the following is derived by outputting (however, νmat 2ve
+ν.

≠O, cos2β-1≠0).

34 is a subtraction circuit, and multiplication circuit 17. Using the outputs of the adder circuit 31 as inputs, i□2V@+I@II@, z 2L++V+m and -I
pVpcosθ (cos 2β-1) is derived and output.

35 is a multiplication circuit, which inputs the outputs of the subtraction circuit 34 and divides the division circuit 33 -I, V, (sin α5in (α+2β+θ)+5i
n(α+2β)sin(α+β)2sin(α+β)s
in(α+β+θ))=IpV, cos θ
, , , , -(18) is derived and output (however, V@+g 2ve+νwr-Z≠
O, Vpsin(cr+θ) (CO32β-1)≠0).

This means that the determination amount deriving unit 23 has obtained the result shown in equation (18).

If the denominator is zero, the same processing as described in the first operation principle diagram is required.

The criteria for this are not shown, but IpV, co
When s θ ≧ 0 (19) is satisfied, the contact point as a directional relay is closed.

Note that equation (18) is not the only method for realizing the present invention, and results completely equivalent to the present invention can be obtained using some of the calculation equations described below.

FIG. 2 shows another embodiment.

Here, before describing a specific implementation method, the calculation algorithm will be described.

(I, V,) +5in(α (sin(cr+β)sin(α-β+θ)β)sin
(α+β+θ) −2sincrsin(cr+θ))
1, V, cos θ ・・・・・・・・・ (20) (However, V-+2 2ν, +V- ≠0゜V, 5in(α+β) (cos2β-1)≠0) In other words, the formula Even with the relationship between the sampling data of current and voltage shown on the left side of (20), the third equation has the same result as the third equation of equation (18).

This is equivalent to replacing m in parentheses on the right side of equation (15) with m-1.

FIG. 2 is a block diagram of an actual circuit on the left side of equation (20), and in the figure, the same reference numerals as in FIGS. 1 and 1O indicate the same or equivalent parts.

40 is a multiplication circuit which derives and outputs Im++Vs-1 through the data distribution path 10-1 and with the outputs of the temporary data storage chambers 3-1 and 8-1 as inputs, respectively.

41 is a multiplication circuit which inputs the outputs of the data temporary storage chamber 4-1.8 via the data distribution path 10-1, and outputs i,
v, is derived and output.

42 is a multiplication circuit, which receives the outputs of the temporary data storage chambers 5-1 and 7 via the data distribution path 10-1 as inputs, and has a length of 1 m.
−1ν and +1 are respectively derived and output.

43 is an adder circuit, which inputs the outputs of the multiplier circuits 40 and 42, respectively, and adds 1m++Vm-+ + 1+++-IVs+
+ is derived and output.

44 is a multiplication circuit, which inputs the output of the multiplication circuit 41 and
1 V, is derived and output.

45 is a subtraction circuit, which inputs the outputs of the addition circuit 439 and the multiplication circuit 4, respectively, (++s++Vs-1+I*-+V*++) 21m
Vm is derived and output.

46 is a multiplication circuit, and subtraction circuit 45. 2ν with the outputs of the divider circuit 2 as inputs, respectively.

v11+, 2vII+v, -, ((1+a++Vs
-++1+a-+Vs++) 2tsv is derived and output (however, V@+g2ν+V, -≠0).

If the denominator is zero, the same processing as described in the first operation principle is required.

This means that the determination amount deriving unit 23 has obtained the result shown in equation (20).

Further, FIG. 3 shows another embodiment.

This calculation algorithm is as follows.

2ν.

Va+2-2vlI+v.

(1+*(V*+z”Vs (i□IVIIl+llll ν1 , (IpVp) [sir+α(sin(α+2β+θ
)+5in(cr-2β10))(sin(α+β)s
in (α + β + θ) + 5 in (α - β) sin (α - β
+θ) j= I, V, cos θ ・・・・・・・・・ (2I) (However, v@, z-2v@+va-z ≠Q, Vp
sin(cr+θ)(cos2β-1)≠0).

That is, even with the relationship between the current and voltage sampling data shown in equation (21), the third equation has the same result as the third equation of equation (18).

FIG. 3 is a block diagram of a circuit realizing the left side of equation (21). In the figures, the same reference numerals as in FIGS. 1, 2 to 10 indicate the same or corresponding parts.

50 is a multiplication circuit which derives and outputs 1s-IV@-1 by inputting the outputs of the temporary data storage chambers 5 to 1.8-1, respectively, via the data distribution path 10-2.

Reference numeral 51 denotes an adder circuit which inputs the outputs of the multiplier circuits 12 and 50, respectively, and derives and outputs t@*+V+*+++1s-IVs-1.

52 is a multiplication circuit which is connected to the data temporary storage room 4-1 through the data distribution path 10-2. Using the outputs of the adder circuits 15 as inputs, ta (Va.2+ν, -2) is derived and output.

53 is a subtraction circuit, which inputs the outputs of the addition circuit 511 and the multiplication circuit 52, respectively, and calculates L(vs+z+vs-t) (i+e*+Vm+++
ia-+V*-+) is derived and output.

54 is a multiplication circuit, and a division circuit 33. Using the outputs of the subtraction circuits 53 as inputs, 2V+a V@*z 2v, +v-("(", t+"-")(la
st V*+(+l5-t Va-1)) is derived and output (however, V□t 2v, +v.

≠0).

When the denominator is zero, processing similar to that described in the operating principle of FIG. 1 is required.

This means that the determination amount deriving unit 23 has obtained the result shown in equation (20).

Further, FIG. 4 shows another embodiment.

This calculation algorithm is shown below.

2v.

Vs*1 2Va+VBK-(illI◆+L
-+) (V*◆1-■@-〇+ (1+e++Vs++
+L-1ν@-1) 2tsν, )・IpVp[(s
in(α+β)-sin(α-β))×(sin(α1β+θ)-sin(α-β+θmonth+(sin(α+β)
sin(cr+β10) +5in(α-β)×5in
(cr-β10θ)) −2sincr ・5in(α+
β)1=1. V, cos θ ・・・・・・・・・ (22) (However, v@+! 2v, +v.

≠0゜ V, sin (α+β) (cos2β-1)≠0).

When the denominator is zero, processing similar to that described in the operating principle of FIG. 1 is required.

That is, even with the relationship between the current and voltage sampling data shown in equation (22), the third equation has the same result as the third equation of equation (18).

Equation (22) is a modification of Equation (20), focusing on the following.

1m+IVs-1+1m-IVs+1 = (1m+++xs-+) (1m++V*+++1
a-+Vs-+) (22-1) FIG. 4 is a block diagram of a circuit realizing the left side of equation (22). In the figures, the same reference numerals as in FIGS. 1, 2, 3, and 10 indicate the same or corresponding parts.

55 is a subtraction circuit which derives and outputs 111+It and -1 by inputting the outputs of the temporary data storage chambers 3-1 and 5-1 via the data distribution path 10-3, respectively.

56 is a subtraction circuit which inputs the outputs of the data temporary storage chambers 7 and 8-1 via the data distribution path 10-3, and outputs V@
+I Vm-1 is derived and output.

57 is an adder circuit, which inputs the outputs of the multiplier circuits 40 and 42, respectively, and calculates Is*IV++++I +Ia-IV*-1.
is derived and output.

58 is a multiplication circuit, which inputs the outputs of the subtraction circuits 55 and 56, respectively, and calculates (las+1+e-1) (Vs*+
Vm-+) is derived and output.

60 is a multiplier circuit which inputs the output of the multiplier circuit 41 and outputs 2
1. ν, is derived and output.

59 is an addition circuit, multiplication times! Using the outputs of Ir5B and Ir60 as input, (ia*+-1m-+)(V*++ VII-+)+
2iaVm is derived and output.

61 is a subtraction circuit, which inputs the outputs of addition circuits 57 and 59, respectively, and calculates (1mst L-+) (Vs++ Vs-1)+
(1+a++Vs++ +1+a-+Va-+)
21mν.

is derived and output.

62 is a multiplication circuit, and a division circuit 33. 2V with the outputs of the subtraction circuits 61 as inputs.

v11G! 2v, -1-y, -, ((i11+kan-11&-1)(V-◆1-shim-1)+(Im++V
a++ + 1s-IV+e-1) 2LsV+a)
is derived and output (however, Vl11+Z 2v
, +v, −2≠0).

This means that the determination amount deriving unit 23 has obtained the result shown in equation (22).

Further, FIG. 5 shows another embodiment.

This calculation algorithm is shown below.

vs V@+□2va+v@-z (i"Iv"'l"-Yamaichi■-2i,v,Mukokuro) 2v.

4pVp[5in(α+β)sin(α+β+θ)+5
in(α-β)sin(α-β+θ)2sinα5in
(cr+θ) 1, V, cos θ When the denominator is zero, processing similar to that described in the operating principle of FIG. 1 is required.

Equation (23) is a modification of Equation (21), focusing on the following.

i, (v,.! + Vll-2) = 21+eV
+a "pa・"°・−・va ・−・・・・・・・(23-1) (However, ■, ≠0).

FIG. 5 is a block diagram of a circuit realizing the left side of equation (23). In the figures, the same symbols as in Figures 1 to 4 and 10 are the same.
or a corresponding portion.

10-4 is a data distribution path, 63 is a multiplication circuit, 63-1 is a division circuit, 64 is a multiplication circuit, 65 is a subtraction circuit, and 66 is a multiplication circuit. It inputs the output and outputs 2V. The division circuit 63-1 is a 0 multiplication circuit that inputs the outputs of the multiplication circuit 63 and the addition circuit 15, respectively, and derives and outputs -v@*1+vJ- (provided that 2V+mV, ≠0) 64 inputs the outputs of the multiplication circuit 60 and the division circuit 63, respectively, to 2H, v, Vm+
2vm which derives and outputs 2+Vm-2- (however, V, ≠0). The subtraction circuit 65 is the addition circuit 5
With the outputs of the 12 multiplier circuits 60 as inputs, the signal n+Z+
V, -Z +1ll1sym+++l+s-mountain-+21+mV+e
2v* is derived and output (however, ■, ≠0).

66 is a multiplication circuit, and division circuit 33. Using the outputs of the subtracting circuits 65 as inputs, 24 sVs shock per unit) vs is derived and output (however, ν, 4°≠0.v7≠
0).

The determination amount deriving unit 23 includes: This means that you have obtained it.

Further, FIG. 6 shows another embodiment.

This calculation algorithm is shown below.

The result shown in equation (23) is 2 vs + v.

2v.

9. z 2v, +v,, (-21”・e (Is
+V□1 +1ll-IV+1 +(i□, +i.

)(v,,,+ν,-,)1 1,Vp[-2sir+crsin(cr+θ)(si
n(α+β) sin(α+β+θ)+5in(α−β)
sin(α−βtenθ))+(sin(α+β)+5in
(α β)) (sin (α+β+θ)+5in(α β1000)) ] = IpV, cos θ ・・・・・・・・・ (24) (However, ν..□−2v@+Vll−2 ≠Q, V
psin(α+β)(cos2β-1)≠0).

When the denominator is zero, processing similar to that described in the operating principle of FIG. 1 is required.

Equation (24) is a modification of Equation (20) that focuses on the following.

1□1VI11-1 + l5-IV*+1==(1@
+1 + I@-1) (V11+1+ν111-1)(
1a+IVe4++'I*Vs-I) FIG. 6 is a block diagram of a circuit for realizing equation (24).

In the figures, the same reference numerals as in FIGS. 1 to 5 and 10 indicate the same or corresponding parts.

70 is an adder circuit which inputs the outputs of the temporary data storage rooms 3 to 1.5-1 via the data distribution path 10-5, derives i, . There is.

Reference numeral 71 denotes an adder circuit, which is connected to the data temporary storage room 7.71 via the data distribution path 10-5. Using the outputs of El-1 as inputs,
■,. 1+ν and -1 are derived and output.

Reference numeral 72 denotes an adder circuit, which inputs the outputs of the multiplier circuit 12 and 50, respectively, and outputs I+s++Ve. 1+l5-TVs-1 is derived and output.

73 is a multiplier circuit which inputs the outputs of the adder circuits 70 and 7, respectively, and inputs (++e.+ + lll-1) (VII+
1 + Vp-1) is derived and output.

74 is an adder circuit, with the outputs of the adder circuit 721 and the multiplier circuit 60 as inputs, respectively, (1m++Vs*+ + l5-TVs-1) + 2
1mV+s is derived and output.

75 is a subtraction circuit, and multiplication circuit 73. (1m++Vm+++is, -+V*-+) 21s using the outputs of the adder circuit 72 as inputs, respectively.
Vm+(i□1+i□+) (Vp, -++shi1-1) is derived and output.

76 is a multiplication circuit, and a division circuit 33. Using the outputs of the subtraction circuits 75 as inputs, the following is derived and output:
ν, −7≠0).

This means that the determination amount deriving unit 23 has obtained the result shown in equation (24).

FIG. 7 shows another embodiment.

This calculation algorithm is as follows.

(+,,1+i.

) (Si0..tenν,,)1 − I, Vp[s in (α+β) sin(α−β+
θ) + 5in (αβ) sin (α + β + θ) ・(sin (α + β) + 5in (α β)) (sin (α + β + θ) + 5in (α - β + θ)) 11
, V, cos θ (however, vIl◆2 2V, +v.

≠0゜ V, 5in (α10) (cos2β ■) ≠ 0) If the denominator is zero, Described in the operating principle in Figure 1. The same treatment as above is required.

Figure 7 shows FIG. 3 is a block diagram of a circuit for realizing equation (25).

In the figures, the same reference numerals as in FIGS. 1 to 6 and 10 indicate the same or corresponding parts.

10-6 is a data flow path. 32-1 is an adder circuit, and multiplier circuit 14. Using the outputs of the adder circuits 15 as inputs, vs+z+2v#+Vm-z is derived and output.

33-1 is a division circuit, and multiplication circuit 14. Addition circuit 32-
Using the outputs of 1 as inputs, derive and output (however, V,.! + 2V+
m +v, −2≠0).

80 is a multiplication circuit; multiplication circuit 73. 2v with the outputs of the division circuits 33-1 as inputs, respectively.

V@+ 2+2v, + v, -, (1*+r + i!
I-r) (Vm+ + + Va-+) is derived and output.

81 is a subtraction circuit, which receives the outputs of the addition circuit 575 and the multiplication circuit 80, respectively, and has a voltage of 2V.

11 mountain -1+i, - mountain" Va+z + 2v,
+ Vs・(ts or r +1*-+) (sho, 1+v
, -+) is derived and output (however, V, .z +
2V+s+v.

≠0).

82 is a multiplication circuit, and a division circuit 33. Using the outputs of the subtraction circuits 8 as inputs, ■ (tm++ + 1a-1) (v*++ +V@-1
) ) is derived and output (however, V, .z-2v
, +v, 4≠0).

This means that the determination amount deriving unit 23 has obtained the result shown in equation (25).

Further, FIG. 8 shows another embodiment.

This calculation algorithm is as follows.

2V+s V@+g-2V@+-V@-2((1sVs+z+Ie
+zV-) 21+m++Vs+1)・l5Vp[(
sin cr sin(cr+2β+θ) sin(α+2β
) sin (cr + θ)) 2 sin (α + β) sin (α
+β+θ)1=1. V, cos θ ・・・・・・・・・ (26) (However, V11+g 2VII+ν, -2≠0.■,
≠0゜V, 5in (cr +θ) (cos2β-1)
≠0).

FIG. 8 is a block diagram of a circuit realizing equation (26),
In the drawings, the same reference numerals as in FIGS. 1 to 7 and 10 indicate the same or corresponding parts.

10-7 is a data flow path.

The addition circuit 85 is the multiplication circuit 44. (1+aV@+2+ ia+zv+a) 21m++ with the output of the adder circuit 16 as the input, respectively.
Vs++ is derived and output.

86 is a multiplication circuit, and division circuit 33. 2V with the outputs of the subtraction circuits 85 as inputs.

vll”2 2V@+V@-2 ((IeVm+2+1m.2V11) 2111゜I
Vl++1) is derived and output (however, ν, .z
2va+ν, −2≠0).

This means that the determination amount deriving unit 23 has obtained the result shown in equation (26).

Further, FIG. 9 shows another embodiment.

This calculation algorithm is as follows.

・I, Vp(sir+α5in(α-2β+θ)+5i
n(α-2β)sin(α+θ)2sin(α-β)s
in(α−β+θ)=1. νpcos θ ・・・・・・・・・ (27) (However, V□2 2vs+vs-z ≠Q, V, 5i
Let n(α+θ)(cos2β-1)≠0.

Equation (27) is a modification of Equation (26), and m−t of Equation (26)
-m-2.

When the denominator is zero, processing similar to that described in the operating principle of FIG. 1 is required.

FIG. 9 is a block diagram of a circuit realizing equation (27),
In the drawings, the same reference numerals as in FIGS. 1 to 8 and 10 indicate the same or corresponding parts.

3-2 to 5-2 are temporary storage rooms for data, and im
+ L-1+ l5-2 is stored.

90 is a multiplication circuit which inputs the outputs of the data temporary storage rooms 3 to 2 and 9 via the data distribution path 0 to 8, respectively, and inputs i,
v, -□ is derived and output.

91 is a multiplication circuit which inputs the outputs of the data temporary storage chamber 5-2.8 via the data distribution path 10-8, and outputs i,
−□v1 is derived and output.

The adder circuit 92 inputs the outputs of the multiplier circuit 901 and the multiplier circuit 91, respectively, and derives and outputs i, v, -2+i□2ν.

The multiplier circuit 93 receives the output of the multiplier circuit 50 and outputs 2
1111-I Vs-1 is derived and output.

The subtraction circuit 94 inputs the outputs of the addition circuit 921 and the multiplication circuit 93, respectively, and calculates (1mVm-2+i□zvs) 2L-1v yaw.

is derived and output.

The multiplication circuit 95 is connected to the division circuit 33. Using the outputs of the subtraction circuits 94 as inputs, the following are derived and output (However, ■, .2-2ν, +v
, −z≠0).

This means that the determination amount deriving unit 23 has obtained the result shown in equation (27).

Note that modifications of the above embodiment can be broadly classified into two types. The first is that even if m is changed in equation (26), if the data control procedure of the present invention is followed, β in the second equation can be changed to c
It is possible to obtain the power direction component while keeping os 2β.

Generalizing and replacing m in equation (26) with m+k (k is an integer), the following equation is obtained.

IpVp [sin ((β to X+) sin(cr+(
k+2) β+θ)+5in(cr+(k+2) β
) sin(α+ to β+θ)−2sin(cr+(k+1
)β) sin(cr+(k+1)β+θ)1cos(2
a+2(k+1)β+θ)+cos(2β-θ)-co
s(2cr+2(k+1)β+θ)1-cosθ-co
s(2α+2(k+1)β10)IIV.

-cosθ+Co5(2α+2(k+1)βOctober 1,
V, cosθ...
Old...(28) (However, V @ 4 k4 z -2V
@ * @ + V +a * k -2≠01Vp
sin (β+θ in cr+ (cos2β−1)≠0).

Equation (26) corresponds to the case where k=0.

Now, in the second equation (26), even if m is changed, if the data control procedure of the present invention is followed, β in the second equation can be set to cos 2! It is also possible to obtain the power direction component as β (1 is an integer).

- form a film, Indicated by adding l to each subscript number, 1+++ is unrelated to the subscript l. is necessary.

I, V, [sin α5in (cr + 2j2 β + θ) +
5in(α+2f β)sin(α+θ)2sin(α
+j! β) sin(α+j2β+θ)1cos (2α
+21β+θ)) cosθ+cos (2α+2!β+θ)1cosθ+
cos (2α+21!, β+θ)) IpV, cos θ (Itanshi, V1@i2j 2V@+V1g-2ffi
≠0. V, 5in (α+θ) (cos212β-1)
≠0).

Equation (26) is I! This corresponds to the case of −1.

This means that the second equation of equation (26) is What was shown was If it is l, is obtained.

It goes without saying that these two types of variations apply not only to specific embodiments, but to all embodiments.

Although voltage data is used to derive , the effect does not change in any way even if the data is used.

Specifically, it is as follows.

current It is also possible to treat cos 2β as follows.

For example, equations (29) and (30) This is shown in the case of

This is clear from below.

= cos2β As described in Fig. 1, in this invention, if the sine wave has a constant frequency like the conventional relay, the sampling time width β
If we set the electrical angle to 30 degrees and use data from 3 samples before (or after), that data will be 90 degrees smaller than the current data.
° It is the previous (or subsequent) data, and if the former is a sine component, the latter is a cosine component.In order to use an operation principle that does not depend on the premise that the input data should be taken in in what order. We have shown the means for stipulating this.

Therefore, according to the present invention, the sampling time width β is
Since it is possible to set it regardless of the system frequency,
In addition to making it possible to share the sampling time width β at frequencies of 50 Hz and 60 Hz, the better the performance of the processing device is, the shorter the sampling time width β can be set.

Specifically, in order to obtain a solution for the power direction relay in this invention, 5 sample data from m-2 to m+2 (conventional relays require 3 sample data from m-m+3), and the sampling time width β is If it is shortened, it will be able to operate at higher speeds than conventional relays.

Furthermore, if the frequency fluctuation during these 5 sample data is such that the frequency of the system can be considered almost constant, that is,
It can also be applied to protect the hydroelectric power generator from startup until it reaches its rated frequency.

An additional effect of the present invention is that timed coordination becomes easier than with conventional relays.

In other words, conventional relays achieve time-limited coordination from the power source end to the load end using tap values, suppression springs, contact spacing, etc.
In this invention, by setting the sampling time width β to be shorter toward the load side and longer toward the power source end, in the event of an accident, almost the same current will pass through each section and flow toward the fault point, so the principle is the same. This relay will ensure timed coordination.

At this time, if consideration is given such as increasing the number of times of verification of the calculation results toward the current end, it will also contribute to improving the reliability.

Further, the idea of the present invention may be applied to an impedance relay, and the same effects as in the above embodiments can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, the first quantity of electricity and the second quantity of electricity are obtained by the four arithmetic operation circuits that satisfy the required relational expressions using the sampled values of current and voltage, and the first quantity of electricity is converted into the first quantity of electricity. Since the circuit is configured to determine whether the power direction component obtained by dividing by the electrical quantity of It can be used as a relay. Furthermore, it is possible to obtain a relay that has excellent time-limited coordination and can operate at high speed.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration block diagram for explaining the invention in detail, FIG. 2 is a circuit block diagram showing one embodiment of the invention, and FIGS. 3 to 10 show other embodiments of the invention. The circuit block diagram shown in FIG. 11 is a waveform diagram illustrating an algorithm of a conventional power direction relay. In the figure, 3 to 5 are temporary storage rooms for current data, and 6 to 5 are temporary storage rooms for current data;
9 is a temporary storage room for voltage data; for example, 16 to 21 are four arithmetic operation circuits; and 23 is a determination amount deriving unit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A temporary storage room for current data and a temporary storage room for voltage data in which voltage data and current data obtained by detecting voltage and current of the power system are sampled and quantized in a predetermined sampling time width and temporarily stored, and the temporary storage a four-arithmetic calculation circuit that calculates a required relational expression for system protection using sampled values of current and voltage stored in the room and outputs a first quantity of electricity and a second quantity of electricity that satisfy the required relational expression; The first electrical quantity is made up of a first sampling calculation formula whose dividend is the product of the amplitude value of the current of the power system and the square of the amplitude value of the voltage, and the amplitude of the voltage of the power system. a second sampling calculation formula with the value as a divisor; and a determination amount deriving unit that determines whether or not the power direction component obtained by dividing by the second electrical quantity is greater than zero and outputs the result. Protective relay.