JPH04127534A - Semiconductor device - Google Patents

Abstract

PURPOSE:To display the high breakdown strength characteristics sufficient for circuit operation having super rapidity and low power consumption by a method wherein, within a heterojunction bipolar transistor, an emitter, a base, a collector layer are structured to make specific band gaps. CONSTITUTION:The title semiconductor device is provided with an n type layer 28, a p type base layer 26 making smaller band gap than that of the emitter layer 28, the first collector layer 24 making equal band gap to that of the base layer 26, the second collector layer 22 planar-doped in p-type and the third n-type collector layer 18 making the larger layer band gap than that of the first collector layer. Through these procedures, since the electric field in the first collector layer 24 is set up by the difference in the impurities of the base layer and the second collector layer, the running rate of the electrons injected from the base layer to the first collector layer is accelerated. Besides, the band gap of the third collector layer to be a high electric field by p-n junction becomes wider than that of the first collector layer furthermore, the band gap of the fourth collector layer becomes gradually wider. Accordingly, the occurrence of the avalanche effect can be avoided more securely.

Description

[Detailed Description of the Invention] [Required I14] A semiconductor device, which relates to a semiconductor device, particularly an HBT (heterojunction bipolar transistor), which has ultra-high speed and low power consumption, and also has high breakdown voltage characteristics sufficient for circuit operation. an n-type emitter layer, a p-type base layer bonded to the emitter layer and having a smaller bandgap than the emitter layer, and a p-type base layer bonded to the base layer and having a bandgap smaller than the base layer; a first collector layer equal to the layer; a second collector layer bonded to the first collector layer and planar-doped to P type; bonded to the second collector layer;
n whose bandgap is larger than that of the first collector layer
a third collector layer of the mold.

[Industrial Application Field] The present invention relates to a semiconductor device, and particularly to an HBT (heterojunction bipolar transistor).

In HBT, by using a heterojunction for the emitter-base junction, the efficiency of electron injection between the emitter and base can be increased, and there is no restriction on the doping of the emitter layer and the base layer, which increases the degree of freedom in design. This enables device design suitable for higher speeds.

For this reason, the St.
It is highly anticipated that it will break the limits of bipolar transistors. Especially HBT using compound semiconductors
In addition to the advantageous conduction characteristics of electrons in the base layer and collector depletion layer, the design flexibility including the band #I structure is greatly expanded, making it very advantageous for ultra-high speed, and is currently being actively researched. There is.

[Prior Art] Conventionally, among various compound semiconductors, AlGaAs/
HBT using a GaAs heterojunction has been the most actively researched because of its ease of controlling crystal growth. As a result, it has achieved the fastest switching speed of any existing semiconductor device.

In order to achieve even higher speeds, the important thing in device design is to reduce parasitic capacitance and parasitic resistance, as well as reduce the transit time of the base layer and collector depletion layer. The transit time of the collector depletion layer has been reduced by thinning the base layer and adopting a graded base, and
P-type collector, I-type collector, BCT (Ballis
tic Co11ection Transistor
) structure, etc., and by optimizing the electric field within the depletion layer, speeding up has been achieved.

FIGS. 3 and 4 show the band addition and layer structure of a conventional HBT and a BCT that employs the i/p"/n" 411 structure as one of the high-speed collector structures.

In these HBT and BCT, an N-type emitter layer 4
2.52 and P+ type base layer 44.54 are common, respectively, but instead of the n-type collector layer 46 of HBT, BC
The collector layer of T is composed of an i-type layer 56 with high mobility, a P+-type planar doped layer 58, and an n+-type layer 60.

And this i/p''/n+multilayer collector tree construction supplement, P
By adjusting the concentration of the + type planar doped layer 58, the electric field in the type 1 layer 56 is reduced to IjLl! After becoming i, electrons cause a velocity overshoot in the entire region, and move quasi-pallistically through one layer with a low impurity concentration.

That is, the HB of the conventional n-type collector supplement shown in FIG.
In T, electrons injected from the p+ type base 144 into the n type collector layer 46 are immediately injected into the valley, whereas in the i/p''/n+ multilayer collector topography supplement CT shown in FIG. , a constant collector voltage vc
In the range of ＠, electrons cause velocity overshoot in most regions of the collector layer, and are able to travel quasi-pallistically through the valley, where the traveling speed is higher than the L valley.Therefore, this i/p By employing the /n+ multilayer collector structure, it is possible to reduce the electron transit time, which is the intrinsic delay time of the device, especially the collector depletion layer transit time.

For example, H using AlGaAs/GaAs heterojunction
It has been reported that a maximum cutoff frequency of 105 GHz was achieved by applying the i/p''/n+ multilayer collector #l structure to B T, demonstrating the usefulness of this structure (T,
l5ibashi et al, uLTR^-old GH
5PEED AlGaAs/GaAs IIETERO
JUNcTION BIPOL＾RTRAMSISTO
R”, 1988 International Ele
ctron DevicesMeeting TECH
NIC^L DIGEST p826-829).

However, when GaAs is used for the base layer, the turn-on voltage increases, resulting in a higher power supply voltage and higher power consumption, which is said to be difficult to integrate.

On the other hand, In and AlA using InGaAs for the base layer
s/InGaAsJI? HBTs using so-called narrow-gap-based heterojunctions, such as 1nP/InGaAs heterojunctions, have higher electron mobility than GaAs, and not only have superior high speeds but also have low turn-on voltages. It also has excellent low power consumption.

Therefore, in order to reduce power consumption, HBTs using the above-mentioned BCT supplementary low-gap-based heterojunctions, such as InAlAs/InGaAs and InP/InGaA
When applied to an HBT using an s heterojunction, the collector structure becomes i-type 1 nGaAs/P + type InGaAs/n 0-type InGaAs. InGaAs has extremely high electron mobility and has a large energy difference between the r-valley and the L-valley, so the velocity overshoot effect works more effectively.

BC with i/p”/n+multilayer collector like this
When applied to an HBT using a narrow-gap-based heterojunction such as nGaAs, it is considered to be more advantageous for speeding up than in the case of GaAs or the like.

[Problems to be Solved by the Invention] However, when the above-described conventional BCT structure having an i/p''/n+ multilayer collector is applied to an HBT using a narrow gap-based heterojunction such as InGaAs,
Although this is very advantageous for speeding up, on the other hand, the following problems occur.

That is, as is clear from FIG. 4, the electric field in the depletion layer between the P+ type planar doped layer 58 and the n+ pear-shaped collector M60 is stronger than that in the collector depletion layer with a normal collector structure. Become.

Therefore, the breakdown voltage of this collector structure is the p+ n+ of the P+ type planar doped layer 58 and the n-type collector 160.
It is determined by the junction, and is even lower than the normal collector structure.

Moreover, when narrow-gap InGaAs is used for the base layer, InGaAs is usually used for the collector layer as well. Narrow-gap semiconductors have a high ionization rate under high electric fields, making them susceptible to avalanche effects and tunnel effects. Therefore, if a narrow-gap semiconductor is used for the collector layer, the collector breakdown voltage will further decrease. become.

In this way, a problem arises in that the circuit configuration is severely restricted and the circuit operation becomes difficult due to the decrease in collector breakdown voltage characteristics.

As a solution to this problem, when using a narrow-gap semiconductor for the base layer, it is possible to adopt a double-hetero structure with a wide gap for the collector layer.
Therefore, it becomes disadvantageous for the movement of electrons in the collector depletion layer,
You will sacrifice speed.

Therefore, the present invention has ultra-high speed and low power consumption,
Another object of the present invention is to provide a semiconductor device having high breakdown voltage characteristics sufficient for circuit operation.

[Means for Solving the Problems] The above problems include an n-type emitter layer, a P-type base layer that is bonded to the emitter layer and whose band gap is smaller than that of the emitter layer, and a P-type base layer that is bonded to the base layer, a first collector layer having a bandgap equal to that of the base layer; a second collector layer bonded to the first collector layer and planar-doped to P-type; a second collector layer bonded to the second collector layer; This is achieved by a semiconductor device characterized in that it has an n-type third collector layer with a larger gap than the first collector layer.

Further, in the above semiconductor device, the second collector layer is provided between the second collector layer and the third collector layer, and the band gap is inclined such that the band gap gradually increases from the boundary with the second collector layer. This is achieved by a semiconductor device characterized by having an n-type fourth collector layer that is smoothly connected to the third collector layer.

Further, in the semiconductor device described above, the present invention is achieved by the semiconductor device characterized in that the second collector layer has a band gap equal to that of the first collector layer.

Further, in the above semiconductor device, the second collector layer has a band gap that is inclined to gradually increase from a boundary with the first collector layer. achieved by.

Further, the present invention is achieved by the above semiconductor device, wherein the base layer and the first collector layer have a band gap smaller than that of GaAs.

[Function] In the present invention, since the electric field in the first collector layer is set by the difference in the impurity concentration doped in the base layer and the second collector layer, electrons in the first collector layer are The speed overshoot effect of can be set to be maximum in operating conditions. Therefore, electrons injected from the base layer to the collector layer travel semi-pallistically in the r-valley, where the travel speed is high, with a speed overshoot in the first collector layer that occupies most of the collector layer. can do.

Therefore, ultra-high speed can be achieved.

In addition, a part of the second collector layer and the third collector layer are depleted by the p-n junction, resulting in a high electric field, but since the third collector layer has a wide gap, the traveling electrons Even if kinetic energy is obtained from an electric field, avalanche effects are prevented from occurring. Further, by configuring the band gap of the fourth collector layer or the second and fourth collector layers to be gradually increased, it is possible to more reliably prevent the occurrence of the avalanche effect. Therefore, it is possible to realize a high breakdown voltage of the collector.

Furthermore, the band gap of the base layer and the first collector layer is a so-called narrow gap, which is 6 band gaps smaller than that of GaAs, which increases electron mobility and enables ultrahigh-speed operation, while reducing turn-on voltage. This makes it possible to reduce power consumption.

These make it possible to achieve ultra-high speed, low power consumption, and high breakdown voltage characteristics necessary for circuit operation.

[Example] The present invention will be specifically described below based on an illustrative example.

FIG. 1 is a sectional view showing an HBT according to a first embodiment of the present invention.

An n+ type 1nGaAs collector contact layer 14 having a thickness of 300 to 500 nm is formed on the InP substrate 12. Then, on this n+ type I nGaAS collector contact layer 14, an n+ type 1 nGaAsP layer with a thickness of 50 nm is formed.
Quaternary mixed crystal graded layer 16, 1100n thick n+ pear-shaped 1nP id gap collector layer 18, 50nm thick n1 type InGaAsP quaternary mixed crystal graded N20, 20nm thick P1 type 1 nGaAs gray nato 1 layer 2
2. L type 1 with a thickness of 200 nm, nGaAsGaAs narrow gear lug collection 2, P+ type I with a thickness of 50 to 1100 nm
nGaAs base layer 26, 200 nm thick n-type 1n
P! Mitter layer 28, 50nm thick n+ pear-shaped 1nGaA
sP original mixed crystal graded layer 30 and 50 nm thick n+
In-type nGaAs emitter contact layers 32 are formed by stacking layers in sequence.

In addition, an n+ type 1 nGaAs collector contact layer 14
Top, p+ type InGaAs base layer 26 and n+ type 1
On the nGaAs emitter contact layer 32 are a collector electrode 34, a base electrode 36, and an emitter electrode 3, respectively.
8 is formed.

At this time, the n+ type I nGaAs P quaternary mixed crystal graded layers 16, 20 and 30 are (InP) (l n
GaAs)+-x composition X from 0 to 1 or 1
It is changed from 0 to 0.

In addition, p1 type 1nGaAs base FW26 and P" type 1
The P-type impurity concentration of the nGaAs planar-doped N22 is determined so that the difference in concentration between the two produces an electric field that maximizes the speed overshoot effect of traveling electrons in the L-type nGaAs narrow gap collector layer 24.

Furthermore, an n+ type 1 nGaAs collector contact layer 14
is for obtaining low contact resistance, and the n+ pear-shaped 1nGaAsP mixed crystal graded layer 16 is
type InGaAs collector contact layer 14 and n+ type 1
This is to smoothly connect energy bands so that spikes do not occur in the conduction band at the junction with the nP wide gag collector layer 18.

Next, the operation will be explained using FIG. 2.

FIG. 2 is an energy band diagram of the HBT shown in FIG.

The emitter-base junction between the n-type nPm emitter layer 28 and the P+ type InGaAs base layer 26 is an ablative junction, and a spike of about 0.3 eV is formed at the bottom of the conduction band at the junction. For this reason, the n-type 1nP emitter layer 28
Electrons injected into the P+ type 1nGaAs base layer 26 from the
can travel through the s-base layer 26 at very high speeds.

Further, the turn-on voltage, which is the voltage necessary to turn on the HBT of such a supplement, is determined by the band gap of the base layer, and the band gap of this P'' type In, GaAs base layer 26 is Eg = 0. .76eV and
For example, since the bandgap Eg of GaAs is small compared to 1.42 eV, a low turn-on voltage can be obtained, and therefore low power consumption operation is possible. At the same time, InGaAs, which has a small bandgap, also has a small effective mass of electrons, and therefore has a large amount of movement, so P+ type I
This contributes to increasing the speed of electrons in the nGaAs base layer 26 and can further shorten the base transit time.

Further, electrons traveling at a very high speed in the P+ type 1 nGaAs base layer 26 are injected into the l type 1 nGaAs narrow gap collector layer 24;
The aAs narrow gap collector layer 24 is also P+ type I nG.
Like the aAs base layer 26, it has a narrow gap. Furthermore, since it is a highly pure l-type layer, scattering due to impurities is extremely small. Furthermore, the electric field in the 1-type InGaAs narrow gap collector layer 24 maximizes the electron velocity overshoot effect due to the difference in P-type impurity concentration between the P+-type 1-nGaAs base layer 26 and the P+-type 1-nGaAs gray-nato 1 layer 22. It has been optimized as follows.

Therefore, electrons cause velocity overshoot over the entire region of the type 1 InGaAs narrow-gap collector layer 24, and can travel quasi-ballistically through a high-speed valley.

By the way, the P+ type InGaAs planar doped layer 22
and n+ pear-shaped 1nGaAsP mixed crystal graded layer 20
In addition, a part of the n+ type InP wide gap collector layer 18 becomes a depletion layer due to the p+ type n+ junction and is subjected to a high electric field, and the electrons traveling at ultra high speed in the i type layer nGaAs narrow gag collector layer 24 are It enters this high electric field region with high kinetic energy. However, n
The +-type I nGaAsP quaternary mixed crystal graded layer 2o has an inclined band gap, and the band gap is 0.
．． It gradually expands from 76eV to 1.2eV. The bandgap of the n+ pear-shaped 1nP ID gap collector layer 18 is 1-2 eV, which is sufficiently wide. Therefore, it is possible to prevent the occurrence of electron avalanche effect, and therefore, it is possible to obtain a sufficient collector breakdown voltage.

Note that in these depletion layers, electrons are
There is a transition from valley to L valley, but n+ pear-shaped InGaA
Impurities in the sP mixed crystal graded layer 20 and the n+ type InP wide gap collector layer 18! F8! Since the L concentration is high, the width of the depletion layer does not increase that much, and the distance that electrons travel through the L valley becomes short. Therefore, it hardly contributes to an increase in travel time.

As described above, according to this embodiment, (1) a spike is formed at the bottom of the conduction band at the emitter-base junction between the n-type 1nP emitter layer 28 and the P+-type 1nGaAs base layer 26, and a hot electron effect is produced; p+P+ type nGa
Both the As base layer 26 and the l-type InGaAs narrow gap collector layer 24 have a narrow gap;
In-type nGaAs narrow gap collector layer 24 and P
+ type InGaAs planar doped layer 22 and n raw type 1 n
I/P with GaAsP quaternary mixed crystal graded M20
”/n+ Collector top construction supplementary l-type InGaAS
The electric field in the narrow gear tube collector layer 24 is p+ type I n
The n+ type InGaAsP quaternary mixed crystal graded layer 20 and the n1 type InP wide gap collector layer 18 are optimized by the p type impurity concentration difference between the GaAs base layer 26 and the P4 type T nGaAS planar doped layer 22. By having a sloped bandgap and a wide gap that gradually expand, respectively, and preventing the occurrence of electron avalanche effects, it is possible to lower the turn-on voltage and perform low power consumption operation, and the base and collector It is possible to shorten the running time of the circuit and perform ultra-high-speed operation, and furthermore, it is possible to obtain high collector breakdown voltage characteristics sufficient for circuit operation.

In the above embodiment, the P+ type grainer-doped layer is a p+ type InGaAs grainer doped layer 22 using InGaAs with the same narrow gap as the P+ type InGaAs base layer 26, but the n1 type InGaAsP
Quaternary mixed crystal gray element mixed crystal graded upper m20GaAsP
A quaternary mixed crystal is used (or a graded layer may be used).

That is, l type 1 nGaAs narrow gap collector layer 2
4 and the n+ pear-shaped 1nP id gap collector layer 18, an InGaAsP quaternary mixed crystal graded layer is provided which is inclined so that the band gap gradually expands. The junction portion of this InGaAsP quaternary mixed crystal graded layer with the i-type InGaAs narrow gap collector layer 24 is a P1 type I doped with P-type impurities.
An nGaAsP quaternary mixed crystal planar doped layer is formed, and an n-type impurity is doped between it and the remaining n1 type InP wide gap collector layer 18, so that the band gap is equal to that of the p+ type layer GaAsP quaternary mixed crystal planar doped layer. Continuously connected n+ pear-shaped 1nGaAsP mixed crystal graded layers are formed.

By the way, since this p1 type 1 nGaAsP quaternary mixed crystal planar doped layer is also depleted and a high electric field is applied, it is better to form a graded layer in which the band gap is gradually expanded in this way. It can be said that this is more desirable for the collector voltage characteristics than the case of .

In the above embodiment, the collector layer provided in contact with the P+ type InGaAs base layer 26 is an I type I nGaAs base layer 26.
Although the nGaAs narrow gap collector layer 24 is used, it is not necessarily limited to type 1, and may be p-type or n-type. Normally, at low current density, electrons "longen the distance traveled through the valley and increase the speed." P-type is said to be better for achieving high current density, but at high current density
k) In order to prevent the effect and operate at high speed, n-type is preferable, or alternatively, only the vicinity of the junction with the P+ type 1 nGaAs base layer 26 should be P-type or n-type, and most of the rest should be P-type or n-type. By using n-type as in the above embodiment, the advantages of both may be combined.

Furthermore, the n-type InP emitter layer 28 is not limited to InP.
For example, it may be an n-type InAlAs emitter layer, and other InP layers may also be used as InAIAS or 1nGaA.
The layer made of sP may be replaced with InAlGaAs.

Furthermore, in the above embodiment, in order to increase the speed, P
+ type I nGaAs base layer 26 and i type I nGaA
s narrow gap collector layer 24
Although nGaAs is used, if emphasis is placed on improving breakdown voltage characteristics rather than increasing speed, it is not necessarily necessary to use a narrow gap semiconductor material, and for example, GaAs or the like may be used.

[Effects of the Invention] As described above, according to the present invention, an n-type emitter layer, a P-type base layer whose band gap is smaller than that of the emitter layer, and a first collector layer whose band gap is equal to that of the base layer. , a P-type grainer-doped second collector layer, and an n-type third collector layer with a larger band gear 7 than the first collector layer.
Since the electric field in the collector layer is set by the difference in impurity concentration between the base layer and the second collector layer, electrons injected from the base layer to the first collector layer travel at high speed in the valley. It can run quasi-pallistically with overshoot, and the third collector layer, which has a high electric field due to the p-n junction, has a wide bandgap that is larger than that of the first collector layer. Therefore, it is possible to prevent the avalanche effect from occurring.

Furthermore, since the band gap of the fourth collector layer gradually increases, it is possible to more reliably prevent the avalanche effect from occurring.

This makes it possible to achieve ultra-high speed and high voltage resistance required for circuit operation.

Further, by using a narrow gap semiconductor for the base layer and the first collector layer, it is possible to achieve ultra-high speed and low power consumption.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an HBT according to an embodiment of the present invention, FIG. 2 is an energy band diagram of the HBT shown in FIG. 1, and FIG. 3 is an energy band diagram for explaining a conventional HBT. FIG. 4 is an energy band diagram for explaining the conventional BCT. In the figure, 12...InP substrate, 14...n1-type InGaAs collector contact layer, 16.20.30--n'' type 1nGaAsP quaternary mixed crystal graded layer, 18... ...n+ pear-shaped 1nP wide gap collector layer, 22...P+ type 1 nGaAs planar doped layer, 24...l type 1 nGaAs narrow gap collector layer, 26... P+ type 1 nGaAs base layer, 28
......n-type InP emitter layer, 32...
n+ type 1 nGaAs emitter contact layer, 34...Collector electrode, 36...Base electrode, 38...Emitter electrode, 42.52...N type emitter Layer, 44.54・
...P+ type base layer, 46...n type collector layer, 56...1 type layer, 58...P+ type planar doped layer, 60...
...n+ type layer.

Claims (1)

[Claims] 1. An n-type emitter layer, a p-type base layer bonded to the emitter layer and having a smaller band gap than the emitter layer, and a p-type base layer bonded to the base layer and having a band gap smaller than the base layer. the first equal to the layer
a second collector layer connected to the first collector layer and planar-doped to p-type; and a second collector layer connected to the second collector layer and having a bandgap larger than that of the first collector layer. and a large n-type third collector layer. 2. The semiconductor device according to claim 1, wherein the semiconductor device is provided between the second collector layer and the third collector layer, and has a band gap that gradually increases from the boundary with the second collector layer. A semiconductor device comprising an n-type fourth collector layer that is inclined and smoothly connected to the third collector layer. 3. The semiconductor device according to claim 1 or 2, wherein the second collector layer has a bandgap equal to that of the first collector layer. 4. The semiconductor device according to claim 1 or 2, wherein the second collector layer has a band gap that gradually increases from a boundary with the first collector layer. Characteristic semiconductor devices. 5. The semiconductor device according to claim 1, wherein the base layer and the first collector layer have a band gap smaller than that of GaAs. .