JPH04127482A - Manufacture of photovoltaic element - Google Patents

Abstract

PURPOSE:To reduce drift of optically generated carrier between electrodes and to largely suppress recombination of the carrier by forming the electrodes on an opened region or a strait region to become nuclei of crystallization due to formation of grain boundaries between one-conductivity-type amorphous semiconductor layers to become adjacent nuclei. CONSTITUTION:An insulating film 3 made of silicon oxide, etc., is formed on an amorphous silicon layer 2 on a base 1 made of a conductive substrate to become a rear surface electrode. The film 3 is patterned by photolithography, a land region 13 made of the film 3 remains, and an opened region 20 exposed on the layer 2 is partly formed. Then, a type amorphous silicon layer 4 is formed on the base 1 including the regions 13 and 20. The layers 4, 2 are partly brought into contact with one another on the region 20. The amorphous silicon layer is crystallized by heat treating, and an n<+> type polycrystalline silicon layer 12, and an n<+> type polycrystalline silicon layer 14 are formed. Crystallization progresses radially from the part of the region 20. Accordingly, a grain boundary part 22 is concentrated at the intermediate part of the adjacent regions 20 and 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a photovoltaic element used as a solar cell, a light sensor, etc.

C. Prior Art] In general, a photovoltaic element is made by laminating in this order a transparent electrode, an amorphous semiconductor layer of p-type, 1-type, or n-type conductivity, and a back electrode on a transparent substrate such as glass. It is configured.

Although such photovoltaic devices have the advantage of being inexpensive, they have the problem of lower photoelectric conversion efficiency than photovoltaic devices using single-crystal silicon as a substrate.

As a countermeasure to this problem, a structure in which the semiconductor layer is composed of an amorphous layer and a crystalline semiconductor layer has been proposed in order to improve the photoelectric conversion efficiency.
Al Digest of 2nd International
ionalPhotovoltaic 5science
and Engineering Conference
e 1986, pp. 394-397, it is composed of a laminate of p-type polycrystalline silicon and n-type amorphous silicon.

[Problems to be Solved by the Invention] Conventionally, polycrystalline silicon layers have been formed by CVD or a combination of CVD and recrystallization to reduce costs. In this method, the grain size of the polycrystalline silicon is small, and the polycrystalline silicon contains a correspondingly large number of grain boundaries. These grain boundaries have the property that recombination of photogenerated carriers is likely to occur, which is an obstacle to improving photoelectric conversion efficiency.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for manufacturing a photovoltaic element having a high-quality polycrystalline semiconductor layer with large crystal grains and small grain boundaries.

[Means for Solving the Problems 1] The first aspect of the present invention is to provide an amorphous semiconductor layer of one conductivity type doped with a high concentration of an impurity that determines conductivity on a substrate; forming an insulating film on the layer, patterning the insulating film to partially form an aperture region in which the surface of the amorphous semiconductor layer is exposed; An intrinsic amorphous semiconductor layer is formed on the upper surface of the substrate, and this is heat-treated to proceed with crystallization using the amorphous semiconductor layer of one conductivity type located under the opening region as a core, thereby forming a polycrystalline semiconductor layer of one conductivity type. a step of forming a semiconductor layer, a step of forming a semiconductor layer of another conductivity type on the polycrystalline semiconductor layer, and a step of forming an electrode in contact with the semiconductor layer region of the other conductivity type located on the opening region. It is characterized by having the following.

The second aspect of the present invention includes a step of forming an insulating film on a base, patterning the insulating film, and partially forming an aperture region where the surface of the base is exposed; selectively forming an amorphous semiconductor layer of one conductivity type doped with impurities that determine conductivity; and forming an intrinsic amorphous semiconductor layer on the substrate including the amorphous semiconductor layer and the insulating film a process of forming a crystalline semiconductor layer, and heat-treating the same to proceed with crystallization using the amorphous semiconductor layer of one conductivity type as a nucleus;
a step of forming a polycrystalline semiconductor layer of one conductivity type; a step of forming a semiconductor layer of another conductivity type on the polycrystalline semiconductor layer;
The method is characterized by comprising a step of forming an electrode in contact with a semiconductor layer region of a different conductivity type located on the opening region.

A third aspect of the present invention is to provide an amorphous semiconductor layer of one conductivity type doped with an impurity that determines conductivity at a high concentration on a substrate, and to form an insulating film on this amorphous semiconductor layer, A step of patterning the insulating film to partially form a strait region where the surface of the amorphous semiconductor layer is exposed, and forming an intrinsic amorphous semiconductor layer on the upper surface of the substrate including the insulating film and the strait region. a step of forming a polycrystalline semiconductor layer of one conductivity type by heat-treating the amorphous semiconductor layer of one conductivity type located under the strait region and proceeding with crystallization using the amorphous semiconductor layer of one conductivity type as a nucleus; The method is characterized by comprising a step of forming a semiconductor layer of a different conductivity type on the semiconductor layer, and a step of forming an electrode in contact with the semiconductor layer region of the other conductivity type located on the strait region.

A fourth aspect of the present invention includes a step of forming an insulating film on a base, patterning the insulating film to partially form a strait region where the surface of the base is exposed, and conductive only in this strait region. selectively forming an amorphous semiconductor layer of one conductivity type doped with an impurity that determines the property of the substrate; a step of forming a semiconductor layer, applying heat treatment to the semiconductor layer and proceeding with crystallization using the amorphous semiconductor layer of one conductivity type as a core;
a step of forming a polycrystalline semiconductor layer of one conductivity type; a step of forming a semiconductor layer of another conductivity type on the polycrystalline semiconductor layer;
The method is characterized by comprising a step of forming an electrode in contact with a semiconductor layer region of a different conductivity type located on the strait region.

[Effect 1] When an amorphous semiconductor layer doped with a high concentration of an impurity that determines conductivity is heated, crystallization proceeds faster than an intrinsic amorphous semiconductor layer. Therefore, crystallization progresses with this doped amorphous semiconductor layer as a core, forming a polycrystalline semiconductor layer with large crystal grains, and the grain boundaries are between adjacent amorphous semiconductor layers of one conductivity type that serve as the core. Therefore, by forming an electrode on the open pore region or the strait region that serves as the nucleus for crystallization, the movement of photogenerated carriers between the electrodes is less likely to cross grain boundaries, and the regeneration of photogenerated carriers is reduced. Coupling can be significantly suppressed.

[Example] First, the first aspect of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 is a plan view showing one step of the method for manufacturing a photovoltaic device of the present invention, and FIG. 2 (a) to g) are sectional views showing the method for manufacturing a photovoltaic device of the present invention in order of steps and the second
Figure (b) is a sectional view taken along the line B--B in Figure 1.

As shown in FIG. 2(a), an n-type amorphous silicon layer 2 doped with a high concentration of n-type impurities and having a thickness of 5,000 layers is formed on a base 1 made of a conductive substrate that will serve as a back electrode. death,
An insulating film 3 made of silicon oxide or the like is formed on this amorphous silicon layer 2.

The above-mentioned n-type amorphous silicon layer 2 is, for example, a radio frequency (R
F) Formed on the substrate 1 by glow discharge method. The reaction gases are SiH, losccm, and PH.

(1%)/H3 is mixed and introduced at IO sccm. The substrate temperature was 300° C., the RF power was 20 W, and the gas pressure was 300 mtorr.

Further, when silicon oxide is formed as the insulating film 3, it is formed by sputtering, for example. The film forming conditions were 16 sec of argon (Ar) and 4 sec of oxygen (0,) as reaction gases, and RF power of 300 W.
, the substrate temperature is 300°C.

Subsequently, as shown in FIGS. 1 and 2(b), the insulating film 3 is patterned by photolithography to leave the land region 13 consisting of the insulating layer 2 and the amorphous silicon layer 2. An aperture region 20 whose surface is exposed is partially formed.

Next, as shown in FIG. 2C, an l-type amorphous silicon layer 4 having a thickness of 10 μm is formed on the upper surface of the substrate l, including the land region 13 and the opening region 20. The i-type amorphous silicon layer 4 and the n°-type amorphous silicon layer 2 partially contact each other over the opening region 20.

This type 1 amorphous silicon 4 is formed by RF glow discharge, and the film forming conditions are as follows: The temperature of the substrate is maintained at 550°C, the pressure is 300 mTorr, the RF power is 20 W, and the Si
H, flow rate 10105e.

Thereafter, as shown in FIG. 2(d), the substrate 1 subjected to the above-mentioned treatment is placed in a vacuum container, maintained at a temperature of 600°C, and heat-treated to form an amorphous silicon layer. By crystallization, an n-type packed crystal 9932 layer 12 and an n-type polycrystalline silicon layer 14 are formed. This crystallization process is called solid phase growth, and since the n° type amorphous silicon layer 2 crystallizes faster than the type 1 amorphous silicon layer 4, the n° type amorphous silicon layer 2 located in the opening region 20 2 becomes a nucleus for crystallization, and crystallization proceeds radially from this opening region 20 portion. Therefore,
Grain boundary portions 22 are concentrated in the middle between adjacent open pore regions 20.20.

Thereafter, as shown in FIG. 2(e), a p-type amorphous silicon layer 5 with a thickness of 500 layers is formed on the n-type polycrystalline silicon layer 14, and the p-type amorphous silicon layer 5 is On the silicon layer 5, an insulating film 6 made of silicon oxide or the like with a thickness of 5000 nm is formed.
form.

The above-mentioned p' type amorphous silicon layer 5 is formed by, for example, a high frequency glow discharge method. The reaction gas is SiH4 lo
sccm, B, H, (]%)/H1 10105c
Mix and introduce. And the substrate temperature is 300℃, RF
The power was 20 W and the gas pressure was 300 mtorr.

Further, when silicon oxide is formed as the insulating film 6, it is formed by sputtering, for example. The film forming conditions were 16 sec of argon (Ar) and 4 sec of oxygen (0,) as reaction gases, RF power of 300 W,
The substrate temperature is 300°C.

Thereafter, as shown in FIG. 2(f), the insulating film 6 is patterned by photolithography to form a contact hole 16 at a location above the opening region 20.

Finally, as shown in FIG. 2(g), silver,
A surface electrode layer made of a metal such as titanium, aluminum, copper, or a multilayer film thereof is formed by vapor deposition or sputtering, and this surface electrode layer and the p'-type amorphous silicon layer 5 are connected via a contact hole 16. Then, this surface electrode layer is selectively etched to leave only the vicinity of the contact hole 16, thereby forming a comb-shaped surface electrode 7.

In the device formed according to the present invention, photocarriers are generated when light is projected from the front electrode 7 side, and the generated photocarriers are transferred to the substrate 1 side, which becomes the back electrode, respectively. Current is collected on the surface electrode 7 side. As described above, since the surface electrode 7 is contacted above the aperture region 20 and the grain boundary 22 is located in the middle of the aperture region 20, 20, it is unlikely that the photocarriers will cross the grain boundary 22. As a result, recombination of optical carriers can be significantly suppressed, and photoelectric conversion efficiency can be improved.

Next, the second aspect of the present invention will be explained with reference to FIGS. 3(a) to 3(g).

FIG. 3 is a cross-sectional view showing the method for manufacturing the electromotive force element of the present invention in the order of steps, similar to the embodiment shown in FIGS. 1 and 2.

As shown in FIG. 3(a), an insulating film such as silicon oxide is formed on a base 1 made of a conductive substrate that will become a back electrode, and then patterned by photolithography to form a land formed of this insulating film. The region 13 is left to form an open region 20 in which the surface of the base 1 is exposed. This insulating film is formed, for example, by sputtering, as in the embodiments described above.

The film forming conditions were argon (Ar) as the reaction gas for 16s.
ecm, oxygen (0,) 4 sec, RF power was 300 W, and substrate temperature was 300°C.

Subsequently, as shown in FIG. 3(b), an n° type amorphous silicon layer 2 doped with n type impurities at a high concentration and having a thickness of 5000 layers is formed on the entire surface, patterned, and opened. The n'-type amorphous silicon layer 2 is left only in the hole region 20.

The second n'-type amorphous silicon layer 2 is formed by high frequency glow discharge as in the previous embodiment.

Next, as shown in FIG. 3(C), a film with a thickness of 10 μm is deposited on the base 1, including the n-type amorphous silicon layer 2 and the land region 13.
m of l-type polycrystalline silicon layers 4 are formed.

This type 1 amorphous silicon 4 is RF
Formed by glow discharge.

Thereafter, as shown in FIG. 3(d), the substrate 1 subjected to the above-mentioned treatment was placed in a vacuum container and maintained at a temperature of 600°C.
The amorphous silicon layer is crystallized by heat treatment and solid phase growth, thereby forming an n'-type polycrystalline silicon layer 12 and an n-type polycrystalline silicon layer 14.

In this solid phase growth, the n
``Amorphous silicon 2 becomes a nucleus for crystallization, and crystallization progresses radially from this opening region 20 portion.

Therefore, grain boundary portions 22 are concentrated in the middle between adjacent open pore regions 20.20.

Thereafter, a photovoltaic element is formed by the steps shown in FIGS. 3(e) to 3(g). These figures 3(e) to 3(g) correspond to the above-mentioned figures 2(e) to 2(g).
Since this step is the same as the step shown in g), the explanation will be omitted here.

Next, the third aspect of the present invention will be explained with reference to FIGS. 4 and 5.

FIG. 4 is a plan view showing one step of the method for manufacturing a photovoltaic device of the present invention, and FIGS. Yes, 5th
Figure (b) is a sectional view taken along the line B--B in Figure 5.

As shown in FIG. 5(a), an n-type amorphous silicon layer 2 doped with a high concentration of n-type impurities and having a thickness of 5,000 layers is formed on a base 1 made of a conductive substrate that will serve as a back electrode. death,
An insulating film 3 made of silicon oxide or the like is formed on this amorphous silicon layer 2.

The above-mentioned n-type amorphous silicon layer 2 is, for example, a radio frequency (R
F) Formed on the substrate 1 by glow discharge method. The reaction gas was SiH, 10105c, and PH.

(1%)/H1 is mixed and introduced at losccm. The substrate temperature was 300° C., the RF power was 20 W, and the gas pressure was 300 mt, orr.

Further, when silicon oxide is formed as the insulating film 3, it is formed by sputtering, for example. The film forming conditions were 16 sec of argon (Ar) and 4 sec of oxygen (0,) as reaction gases, and RF power of 300 W.
, the substrate temperature is 300°C.

Subsequently, as shown in FIGS. 4 and 5(b), the insulating film 3 is patterned by photolithography to leave an island-like region +3a made of the insulating film 3, and to form n゛amorphous silicon. A strait region 20a is partially formed where the layer surface is exposed.

Next, as shown in FIG. 5C, a type 1 amorphous silicon layer 4 having a thickness of 10 μm is formed on the upper surface of the substrate 1, including the island region 13a and the strait region 20a. The 1 type amorphous silicon layer 4 and the n' type amorphous silicon layer 2 partially contact each other over the strait region 2Oa.

This type 1 amorphous silicon 4 is formed by RF glow discharge, and the film forming conditions are as follows: The temperature of the substrate is maintained at 550°C, the pressure is 300 mTorr, and the RF power is 20W1Si.
The H4 flow rate is 10SCCI11.

Thereafter, as shown in FIG. 5(d), the substrate 1 subjected to the above-mentioned treatment is placed in a vacuum container, maintained at a temperature of 600°C, and heat-treated to form an amorphous silicon layer. By crystallization, an n° type polycrystalline silicon layer 12 and an n-type polycrystalline silicon layer 14 are formed. This crystallization process is called solid-phase growth, and since the n-type amorphous silicon layer 2 crystallizes faster than the l-type amorphous silicon layer 4, the n-type amorphous silicon layer 2 located in the opening region 20 Silicon 2 becomes the nucleus of crystallization, and crystallization progresses radially from this strait region 20a. Therefore, the grain boundary portions 22 are concentrated in the middle between the adjacent strait regions 20a, 20a.

Thereafter, a photovoltaic element is formed by the steps shown in FIGS. 5(e) to 5(g). These FIGS. 5(e) to 5(g) correspond to the aforementioned FIGS. 2(e) to 2(g).
Since this step is the same as the step shown in g), the explanation will be omitted here.

In the device formed according to the present invention, photocarriers are generated when light is projected from the front electrode 7 side, and the generated photocarriers are transferred to the substrate 1 side, which becomes the back electrode, respectively. Current is collected on the surface electrode 7 side. As described above, since the surface electrode 7 is contacted above the strait region 20a and the grain boundary 22 is located in the middle between the strait regions 20a, 20a, it is less likely that photocarriers will cross the grain boundary 22. , recombination of optical carriers can be significantly suppressed, and photoelectric conversion efficiency can be improved.

Next, the fourth aspect of the present invention will be explained with reference to FIGS. 6(a) to 6(g).

FIG. 6 is a sectional view showing the method for manufacturing the electromotive force element of the present invention in the order of steps, similar to that shown in the embodiment of FIG.

As shown in FIG. 6(a), an insulating film such as silicon oxide is formed on a base 1 made of a conductive substrate that will become a back electrode, and then patterned by photolithography to make a film made of this insulating film. The island region 13a is left and the surface of the base 1 is exposed or a strait region 20a is formed.

This insulating film is formed, for example, by sputtering, as in the embodiments described above. The film forming conditions were argon (Ar) 16 sec and oxygen (0,) 4 sec as reaction gas.
cm, RF power is 300W, substrate temperature is 300℃
It is.

Subsequently, as shown in FIG. 6(b), an n-type amorphous silicon layer 2 doped with n-type impurities at a high concentration and having a thickness of 5,000 layers is formed on the entire surface and patterned to form a strait. The n'-type amorphous silicon layer 2 is left only in the region 20a.

This n-type amorphous silicon layer 2 is formed by high frequency glow discharge as in the previous embodiment.

Next, as shown in FIG. 6(c), a film with a thickness of 1 is deposited on the base 1, including the n-type amorphous silicon layer 2 and the island-like region 13a.
An l-type amorphous silicon layer 4 having a thickness of 0 μm is formed. This type 1 amorphous silicon 4 is formed by RF glow discharge as in the previous embodiment.

Thereafter, as shown in FIG. 6(d), the substrate l subjected to the above-mentioned treatment was placed in a vacuum container and maintained at a temperature of 600°C.
Heat treatment is performed to crystallize the amorphous silicon layer by solid phase growth, thereby forming an n'-type polycrystalline silicon layer 12 and an n-type polycrystalline silicon layer 14.

In this solid phase growth, the n'-type amorphous silicon 2 formed in the strait region 20a serves as a crystallization nucleus, and crystallization proceeds radially from this strait region 20a.

Therefore, the grain boundary portions 22 are concentrated in the middle between the adjacent strait regions 20a, 20a.

Thereafter, a photovoltaic element is formed by the steps shown in FIGS. 6(e) to 6(g). These figures 6(e) to 6(g) correspond to the above-mentioned figures 2(e) to 2(g).
Since this step is the same as the step shown in g), the explanation will be omitted here.

In the above-described embodiment, a conductive metal substrate is used as the base 1, but the present invention is not limited to this, and for example, a ceramic substrate with a back electrode formed on the surface may be used.

Furthermore, in the above-mentioned embodiments, a case was explained in which an n-type silicon layer was used as the amorphous semiconductor layer doped with a high concentration of impurities that determine the conductivity type, but a p-type amorphous semiconductor A similar effect can be achieved using layers.

(g) As described in detail, according to the present invention, crystallization progresses with the amorphous semiconductor layer doped with a high concentration of impurities that determine the conductivity type as a core, and polycrystalline crystals with large crystal grains are formed. A semiconductor layer is formed, and grain boundaries are formed between adjacent amorphous semiconductor layers of one conductivity type that serve as nuclei, and electrodes are formed on open pore regions or strait regions that serve as crystallization nuclei. Therefore, the movement of photogenerated carriers between electrodes no longer crosses grain boundaries,
Recombination of photogenerated carriers can be prevented and photoelectric conversion efficiency can be improved.

[Brief explanation of drawings]

1 and 2 show an embodiment of the first invention of the present invention, FIG. 1 is a plan view showing one step of the present invention, and FIG.
) to FIG. 2(g) are cross-sectional views showing the present invention in the order of steps. FIGS. 3(a) to 3(g) are cross-sectional views showing a second embodiment of the present invention in order of steps. 4 and 5 show an embodiment of the third invention of the present invention, FIG. 4 is a plan view showing one step of the present invention, and FIG.
) to FIG. 5(g) are cross-sectional views showing the present invention in the order of steps. FIGS. 6(a) to 6(g) are cross-sectional views showing the fourth embodiment of the present invention in the order of steps. 1...Base, 2...N-type amorphous silicon layer, 3...
・Insulating film, 4... Type 1 amorphous silicon layer, 5...
P゛ type amorphous silicon layer, 6... Insulating film, 7... Surface electrode, 12... N゛ type packed crystal silicon layer 13...
land region, 13a... island region, 14... n-type polycrystalline silicon layer, 20...
...open pore region, 20a...strait region, 22...grain boundary.

Claims (4)

[Claims] (1) An amorphous semiconductor layer of one conductivity type doped with an impurity that determines conductivity at a high concentration is provided on a substrate, an insulating film is formed on this amorphous semiconductor layer, and this insulating film is patterned. forming an intrinsic amorphous semiconductor layer on the upper surface of the substrate including the insulating film and the aperture region, and heat-treating the layer. A step of proceeding with crystallization using the amorphous semiconductor layer of one conductivity type located under the opening region as a core to form a polycrystalline semiconductor layer of one conductivity type, and a step of forming another layer on this polycrystalline semiconductor layer. Manufacturing a photovoltaic device comprising the steps of: forming a semiconductor layer of a conductivity type; and forming an electrode in contact with a semiconductor layer region of a different conductivity type located on the opening region. Method. (2) A step of forming an insulating film on the substrate and patterning this insulating film to partially form an aperture region where the surface of the substrate is exposed, and an impurity that determines conductivity only in this aperture region. selectively forming an amorphous semiconductor layer of one conductivity type doped with a high concentration of a step of heat-treating the amorphous semiconductor layer to proceed with crystallization using the amorphous semiconductor layer of one conductivity type as a core to form a polycrystalline semiconductor layer of one conductivity type; A method for manufacturing a photovoltaic device, comprising the steps of: forming a semiconductor layer; and forming an electrode in contact with a semiconductor layer region of a different conductivity type located on the opening region. (3) An amorphous semiconductor layer of one conductivity type doped with an impurity that determines conductivity at a high concentration is provided on the substrate, an insulating film is formed on this amorphous semiconductor layer, and this insulating film is patterned. to partially form a strait region in which the surface of the amorphous semiconductor layer is exposed; and forming an intrinsic amorphous semiconductor layer on the upper surface of the substrate including the insulating film and the strait region, and subjecting it to heat treatment. A step of proceeding with crystallization using an amorphous semiconductor layer of one conductivity type located under the strait region as a core to form a polycrystalline semiconductor layer of one conductivity type, and a step of forming a polycrystalline semiconductor layer of another conductivity type on this polycrystalline semiconductor layer. A method for manufacturing a photovoltaic device, comprising the steps of forming a semiconductor layer and forming an electrode in contact with a semiconductor layer region of a different conductivity type located on the strait region. (4) Forming an insulating film on the substrate and patterning this insulating film to partially form a strait region where the surface of the substrate is exposed, and adding impurities that determine conductivity only to this strait region. selectively forming a heavily doped amorphous semiconductor layer of one conductivity type; and forming an intrinsic amorphous semiconductor layer on the substrate including the amorphous semiconductor layer and the insulating film. , a step of heat-treating this to proceed with crystallization using the amorphous semiconductor layer of one conductivity type as a core to form a polycrystalline semiconductor layer of one conductivity type, and a step of forming a semiconductor of the other conductivity type on this polycrystalline semiconductor layer. A method for manufacturing a photovoltaic device, comprising the steps of forming a layer, and forming an electrode in contact with a semiconductor layer region of a different conductivity type located on the strait region.