JPH04127477A - Nonvolatile memory - Google Patents
Nonvolatile memoryInfo
- Publication number
- JPH04127477A JPH04127477A JP2249410A JP24941090A JPH04127477A JP H04127477 A JPH04127477 A JP H04127477A JP 2249410 A JP2249410 A JP 2249410A JP 24941090 A JP24941090 A JP 24941090A JP H04127477 A JPH04127477 A JP H04127477A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate
- control gate
- layer
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000013078 crystal Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 1
- 239000002356 single layer Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 239000000463 material Substances 0.000 abstract description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 3
- 238000000206 photolithography Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract 1
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 5
- 230000014759 maintenance of location Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- CNZOFNMWZBNPLL-OSKRVHINSA-L flot regimen Chemical compound [Pt+4].[O-]C(=O)C([O-])=O.[NH-][C@H]1CCCC[C@@H]1[NH-].FC1=CNC(=O)NC1=O.O([C@H]1[C@H]2[C@@](C([C@H](O)C3=C(C)[C@@H](OC(=O)C(O)[C@@H](NC(=O)OC(C)(C)C)C=4C=CC=CC=4)C[C@]1(O)C3(C)C)=O)(C)[C@@H](O)C[C@H]1OC[C@]12OC(=O)C)C(=O)C1=CC=CC=C1 CNZOFNMWZBNPLL-OSKRVHINSA-L 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、電気的に書き込み、消去可能な不揮発性メモ
リ（以下、ＥＥＦＲＯＭという）に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to electrically writable and erasable nonvolatile memory (hereinafter referred to as EEFROM).
［従来の技術］
近年、殆どあらゆる製品にマイクロコンピュータが内蔵
されるようになってきている。メモリはマイクロコンピ
ュータには不可欠なものであり、従来よりＳＲＡＭやＤ
ＲＡＭが使用されているが、これらのメモリは電源を切
ってしまうとメモリ内容も消えてしまうという短所を有
する。[Prior Art] In recent years, microcomputers have come to be built into almost every product. Memory is indispensable for microcomputers, and traditionally SRAM and D
Although RAM is used, these memories have the disadvantage that the memory contents are erased when the power is turned off.
この短所を補ったものがＥＥＰＲＯＭであり、電源を切
ってもメモリ内容が消えないという長所を有する。ＥＥ
ＰＲＯＭは構造的に大きく分けてＭＮＯＳ型とＦＬＯＴ
ＯＸ型に分かれる。ＭＮＯＳ型は、酸化膜と窒化膜界面
のトラップに電子を蓄える素子であり、ＦＬＯＴＯＸ型
は、酸化膜によりどこからも浮遊させた多結晶シリコン
層に電子を蓄える素子である。EEPROM compensates for this drawback and has the advantage that the memory contents do not disappear even when the power is turned off. EE
PROM can be roughly divided into MNOS type and FLOT type in terms of structure.
Divided into OX type. The MNOS type is an element that stores electrons in traps at the interface between an oxide film and a nitride film, and the FLOTOX type is an element that stores electrons in a polycrystalline silicon layer suspended from anywhere by an oxide film.
ＦＬＯＴＯＸ型は記憶保持時間が長く、ＭＯＳプロセス
とも整合が良いことからよく使われている。ＦＬＯＴＯ
Ｘ型も大きく多結晶シリコン層１層のものと２Ｎのもの
に分かれる。この内、１層構造のものは２層構造のもの
と比べてプロセスが簡単で、制御ゲート側に単結晶シリ
コン酸化膜を使っているので、保持特性が良い等の長所
を有する。The FLOTOX type is often used because it has a long memory retention time and is compatible with MOS processes. FLOTO
The X type is also broadly divided into those with a single polycrystalline silicon layer and those with a 2N layer. Among these, the one-layer structure has advantages such as a simpler process and better retention characteristics because it uses a single-crystal silicon oxide film on the control gate side than the two-layer structure.
第２図は、従来から用いられている１層多結晶シｌＪコ
ンＦＬＯＴＯＸ型ＥＥＰＲＯＭの構造を示すものである
。図中、１はＮ型基板、２はＰ型拡散層で、Ｐ型拡散層
（導電層）２の中にＮ型のＭＯＳ（以下、ＮＭＯＳとい
う）が形成され、ソース３ａ、 ドレイン３ｂ、ゲー
ト５ａを有する。このＮＭＯＳのドレイン３ｂは、１０
０人程度の酸化Ｍ４ ｂ、ＮＭＯＳのゲート酸化膜４ａ
と同時に成長させた５００人程度の酸化膜４ｄ及びＮＭ
ＯＳのゲート部５を通して制御ゲート３Ｃへつながって
いる。このゲート部５がＥＥＦＲＯＭの浮遊ゲートにな
る。FIG. 2 shows the structure of a conventionally used one-layer polycrystalline silicon FLOTOX type EEPROM. In the figure, 1 is an N-type substrate, 2 is a P-type diffusion layer, and an N-type MOS (hereinafter referred to as NMOS) is formed in the P-type diffusion layer (conductive layer) 2, and includes a source 3a, a drain 3b, and a gate. It has 5a. The drain 3b of this NMOS is 10
0 oxidation M4b, NMOS gate oxide film 4a
About 500 oxide films 4d and NM were grown at the same time.
It is connected to the control gate 3C through the gate section 5 of the OS. This gate portion 5 becomes the floating gate of the EEFROM.
かかるＥＥＰＲＯＭは、ＮＭＯＳ トランジスタをオン
・オフすることにより、ドレイン３ｂに電圧を与え、こ
れと制御ゲート３Ｃに印加した電圧とで薄い酸化１１１
４ｂを通して電荷のやりとりを行い、ＮＭＯＳ）ランジ
スタのしきい値を変化させ［発明が解決しようとする課
題］
ところで、上記１層多結晶シリコンＦＬＯＴＯＸ型ＥＥ
ＰＲＯＭは、上述のように、プロセスが簡単で、保持特
性が良いという長所を有するが、反面、２層多結晶シリ
コンタイプに比してセル面積が大きく、高集積化には向
かないという短所があった。In such an EEPROM, a voltage is applied to the drain 3b by turning on and off the NMOS transistor, and this and the voltage applied to the control gate 3C form a thin oxide layer 111.
By the way, the above-mentioned one-layer polycrystalline silicon FLOTOX type EE
As mentioned above, PROM has the advantages of simple processing and good retention characteristics, but on the other hand, it has the disadvantage that it has a larger cell area than the two-layer polycrystalline silicon type, making it unsuitable for high integration. there were.
本発明は、上記事由に鑑みなされたもので、その目的と
するところは、従来の長所を生かし、しかもセル面積の
小型化が図れる不揮発性メモリを提供することにある。The present invention has been made in view of the above reasons, and its purpose is to provide a nonvolatile memory that takes advantage of the advantages of the prior art and can also reduce the cell area.
［！ｌ！ｆｌを解決するための手段］
本発明は上記課題を解決するため、単結晶基板上に、ト
ンネル電流注入用の薄い酸化膜と、浮遊ゲートを絶縁す
る比較的厚い酸化膜とを有し、前記薄い酸化膜下に形成
されたドレインと、比較的厚い酸化膜下に形成されたソ
ースと、前記浮遊ゲートの一部からなるゲートとで構成
されるＭＯＳトランジスタと、前記ソース及びドレイン
と絶縁分離された制御ゲートとを有する１層導電ゲート
層型の電気的書き込み／消去可能な不揮発性メモリにお
いて、前記制御ゲートをトレンチ溝構造としたことを特
徴とする。[! l! Means for Solving fl] In order to solve the above problems, the present invention has a thin oxide film for tunnel current injection and a relatively thick oxide film for insulating the floating gate on a single crystal substrate, and A MOS transistor includes a drain formed under a thin oxide film, a source formed under a relatively thick oxide film, and a gate formed from a part of the floating gate, and the MOS transistor is insulated and separated from the source and drain. A one-layer conductive gate layer type electrically writable/erasable nonvolatile memory having a control gate having a trench structure.
［実施例］
以下、本発明を実施例に基づき説明する。第１図は本発
明に係る不揮発性メモリの製法の一例を示す工程図であ
る。[Examples] The present invention will be described below based on Examples. FIG. 1 is a process diagram showing an example of a method for manufacturing a nonvolatile memory according to the present invention.
まず、Ｎ型半導体基板（ｎ−３ｕｂ） １上にフォトリ
ソグラフィ工程、イオン注入工程を経てＰ型拡散層（Ｐ
−１１ａｌｌ） ２を形成した後、素子間分離部にＬＯ
ＧＯ３４Ｃを形成する。その後、単結晶シリコン上に形
成された酸化膜４ｅをマスク材として、将来制御ゲート
となる部分に、ＲＩ Ｅ （Ｒｅａｃｔｉｖｅ ｌ。First, an N-type semiconductor substrate (n-3ub) 1 is coated with a P-type diffusion layer (P
-11all) After forming 2, LO is placed in the element isolation part.
Form GO34C. Thereafter, using the oxide film 4e formed on the single crystal silicon as a mask material, RIE (Reactive I) is applied to the portion that will become the control gate in the future.
ｎ Ｅｔｃｈｉｎｇ）により深さ１４．幅１−のトレン
チ溝６を形成する（第１図（ａ）参照）。depth 14. A trench groove 6 having a width of 1- is formed (see FIG. 1(a)).
次に、マスク材にした酸化１１４ｅを除去した後、イオ
ン注入によりＡｓ”をドープしてＮ型拡散層３ｂ、３ｃ
°を形成し、その後、酸化により酸化膜４ａ、４ｄを形
成する。将来、トンネル酸化膜となるべきところの酸化
膜をフォトリソグラフィ工程、フン酸エンチングにより
除去し、その後に薄い（約１００人）酸化１１４ｂを形
成する（第１図（ｂ）参照）。Next, after removing the oxide 114e used as a mask material, As'' is doped by ion implantation to form N-type diffusion layers 3b and 3c.
After that, oxide films 4a and 4d are formed by oxidation. The oxide film that will become the tunnel oxide film in the future is removed by a photolithography process and hydronic acid etching, and then a thin (approximately 100 layers) oxide 114b is formed (see FIG. 1(b)).
減圧ＣＶＤ （ＬＰＧＶＤ） 工程によりＰＩ’−プ多
結晶シリコンを１．５４堆積させ、２層レジスト工程に
より平坦化を図った後、ＲＩＢによりエッチバックを行
う、フォトリソグラフィ工程とＲＩＢにより、将来、Ｎ
ＭＯＳトランジスタのゲート且つメモリの浮遊ゲートに
なる部分５を残して多結晶シリコンを除去する。その後
、多結晶シリコン５をマスク材としてＡｓ”をイオン注
入、拡散してＮＭＯＳトランジスタのソース３ａとドレ
イン３ｂを形成し、本発明に係る不揮発性メモリを実現
する（第１図（Ｃ）参照）。PI'-type polycrystalline silicon is deposited by a low pressure CVD (LPGVD) process, planarized by a two-layer resist process, and then etched back by RIB.
The polycrystalline silicon is removed leaving a portion 5 that will become the gate of the MOS transistor and the floating gate of the memory. Thereafter, using the polycrystalline silicon 5 as a mask material, As'' is ion-implanted and diffused to form the source 3a and drain 3b of the NMOS transistor, thereby realizing the nonvolatile memory according to the present invention (see FIG. 1(C)). .
次に、上記実施例に係る書き込み電圧について説明する
。書き込み電圧を■、ＮＭＯＳトランジスタの１１４７
０部に設けた薄い酸化膜の両端に印加される電圧をｖｏ
とすると、書き込み電圧■は次式のようになる。Next, the write voltage according to the above embodiment will be explained. The write voltage is 1147 for the NMOS transistor.
The voltage applied across the thin oxide film provided at part 0 is vo
Then, the write voltage ■ becomes as shown in the following equation.
ｖ−（１＋ＣＦＧ／ＣＣＧ）Ｖ。v-(1+CFG/CCG)V.
但し、ＣＣＧは制御ゲート部の容量、ＣＦＧはＮＭＯＳ
ドレイン部の容量である。However, CCG is the capacitance of the control gate section, and CFG is the NMOS
This is the capacitance of the drain section.
電子を注入させるためには、■。は約１’５ＭＶ／ ｃ
ｍ程度必要で、この値はほぼ固定している。従って書き
込み電圧Ｖを下げたい場合、ＣＦＧ／ＣＣＧの値を小さ
くしなければならない。この内ＣＦＧはＮＭＯ３）ラン
ジスタの形でほぼ決まってしまい、結局ＣＣＧを大きく
する必要があり、これは制御ゲートの面積増大を招くこ
とになるが、本実施例のようにトレンチ溝を掘って制御
ゲートを形成することにより、制御ゲートの平面上での
面積を大きくすることなく、制御ゲート部の容量ＣＣＧ
を大きくすることができる。従って、セル面積を増大す
ることなく書き込み電圧Ｖを下げることができるのであ
る。In order to inject electrons, ■. is approximately 1'5MV/c
About m is required, and this value is almost fixed. Therefore, if it is desired to lower the write voltage V, the value of CFG/CCG must be reduced. Of these, the CFG is almost fixed in the form of an NMO3) transistor, and it is necessary to increase the size of the CCG, which results in an increase in the area of the control gate. However, as in this example, it is possible to control it by digging a trench. By forming the gate, the capacitance CCG of the control gate portion can be reduced without increasing the plane area of the control gate.
can be made larger. Therefore, the write voltage V can be lowered without increasing the cell area.
［発明の効果］
本発明は上記のように、トレンチ溝を掘って制御ゲート
を形成したことにより、プロセスが簡単で、保持特性が
良いという長所を生かしつつ、しかもセル面積の小型化
が図れる不揮発性メモリを提供することができた。[Effects of the Invention] As described above, the present invention forms a control gate by digging a trench, thereby making use of the advantages of simple process and good retention characteristics, while also reducing the cell area. It was able to provide sexual memory.
第１図（ａ）〜（Ｃ）は本発明に係る不揮発性メモリの
製法の一例を示す工程図、第２図は従来例を示す断面図
である。
ｌ・・・Ｎ型半導体基板、２・・・Ｐ型拡散層、３ａ・
・ソース、３ｂ・・・ドレイン、３ｃ・・・制御ゲート
、４ａ、４ｄ・・・比較的厚い酸化膜、４ｂ・・・薄い
酸化膜（トンネル酸化膜）、４ｃ・・・素子間分離酸化
膜、５・・・浮遊ゲート、５ａ・・・ゲート。FIGS. 1A to 1C are process diagrams showing an example of a method for manufacturing a nonvolatile memory according to the present invention, and FIG. 2 is a sectional view showing a conventional example. l...N-type semiconductor substrate, 2...P-type diffusion layer, 3a...
- Source, 3b...drain, 3c...control gate, 4a, 4d...relatively thick oxide film, 4b...thin oxide film (tunnel oxide film), 4c...element isolation oxide film , 5... floating gate, 5a... gate.
Claims (1)
膜と、浮遊ゲートを絶縁する比較的厚い酸化膜とを有し
、前記薄い酸化膜下に形成されたドレインと、比較的厚
い酸化膜下に形成されたソースと、前記浮遊ゲートの一
部からなるゲートとで構成されるＭＯＳトランジスタと
、前記ソース及びドレインと絶縁分離された制御ゲート
とを有する１層導電ゲート層型の電気的書き込み／消去
可能な不揮発性メモリにおいて、前記制御ゲートをトレ
ンチ溝構造としたことを特徴とする不揮発性メモリ。(1) A thin oxide film for tunnel current injection and a relatively thick oxide film insulating the floating gate are formed on a single crystal substrate, and a drain formed under the thin oxide film and a relatively thick oxide film are formed on the single crystal substrate. A single-layer conductive gate layer type electrical MOS transistor comprising a source formed under a film, a gate consisting of a part of the floating gate, and a control gate insulated from the source and drain. A writable/erasable nonvolatile memory, characterized in that the control gate has a trench structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2249410A JPH04127477A (en) | 1990-09-18 | 1990-09-18 | Nonvolatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2249410A JPH04127477A (en) | 1990-09-18 | 1990-09-18 | Nonvolatile memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04127477A true JPH04127477A (en) | 1992-04-28 |
Family
ID=17192562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2249410A Pending JPH04127477A (en) | 1990-09-18 | 1990-09-18 | Nonvolatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04127477A (en) |
-
1990
- 1990-09-18 JP JP2249410A patent/JPH04127477A/en active Pending
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