JPH04126399U - semiconductor storage device - Google Patents

Abstract

(57) [Summary] [Purpose] To reduce the standby current consumed in a large capacity memory according to the memory capacity actually used. [Configuration] Arbitrary number of unit memory cell arrays A0 to A
A power supply capable of supplying power to each of the unit memory cell arrays A0 to A7 to activate the memory cell array 1 that can be divided into 7 blocks and the unit memory cell arrays A0 to A7 divided into a plurality of units. The supply circuit 2 and the supply destination of the standby current output from the power supply circuit 2 are set, and the unit memory cell array A0
A power supply destination setting circuit 3 is provided for activating only an arbitrary number of blocks among A7 to A7 according to the memory capacity to be used.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

The present invention relates to semiconductor storage devices, and in particular uses only a portion of a large capacity memory. This is suitable for use in cases where power consumption is reduced.

0002

[Conventional technology]

As is well known, semiconductor memory devices are rapidly increasing in capacity as technology advances. For example, large-capacity memory chips of 256 Mbit or more are now being used. I came. In the case of such a large-capacity chip, depending on the circumstances of the system, the initial Do not use all of the memory capacity in the chip, for example, 1/8 of the total memory capacity. In many cases, only about 1/2 of the storage capacity is used.

0003

[Problem that the idea aims to solve]

However, conventionally, even when only a portion of the storage area is used, memory All memory areas within were activated. For this reason, the amount of energy consumed by semiconductor storage devices is The standby current is constant regardless of the number of bits of memory used; Therefore, even if the number of bits of memory used is small, all of the storage space is used. It was consuming a lot of standby current as well.

0004 Therefore, although it will require a lot of storage space in the future, initially only a small amount of storage space will be needed. If you install a large-capacity semiconductor storage device in a device that is not in use, it will use less storage space. There is an inconvenience that a large amount of standby current is consumed even when the device is not in use. In particular, in battery operation systems, if the current consumption is large, the It is particularly desirable to reduce current consumption, since this reduces the available time. was. For this reason, as mentioned above, it may consume a lot of standby current at first. installs a large-capacity semiconductor storage device in a system that uses only a small amount of storage space. It was a hindrance to the case. In view of the above-mentioned problems, the present invention aims to solve the The current can be reduced according to the amount of memory actually used. purpose.

[0005]

[Means to solve the problem]

The semiconductor memory device of the present invention can be divided into any number of unit memory cell arrays. A memory cell array and each of the above-mentioned unit memory cell arrays divided into multiple pieces. The power supply for activating the above unit memory cell array is divided into multiple units. The power supply circuit that performs each operation and the standby current output from the above power supply circuit. Set the supply destination and select one of the above unit memory cell arrays according to the memory capacity to be used. and a power supply destination setting circuit for activating an arbitrary number of blocks.

[0006]

[Effect]

The storage area of a large-capacity semiconductor storage device is divided into multiple blocks, and each Allows standby current to be supplied to each block so that only the blocks that are used Supplies standby current to the This allows you to start up unused storage space. If you plan to use more storage space in the future, Initially, large-capacity semiconductor storage devices were added to systems that used only a small amount of storage space. To prevent power from being wasted when a device is installed.

[0007]

【Example】

FIG. 1 is a block diagram of the main parts of a semiconductor memory device showing an embodiment of the present invention. Figure 1? As is clear from the above, the semiconductor memory device of this embodiment has a memory cell 1 and a power supply circuit 2. , a power supply destination setting circuit 3, and the like. Memory cell 1 can divide the activation region into multiple blocks. things are used. Such block partitioning is commonly used in SRAM. This is realized using a block division method.

In this embodiment, an example is shown in which the memory cell array 1 is divided into eight blocks. Therefore, which unit memory cell arrays A0 to A7 are divided into eight blocks? A 3-bit control signal _S1 is used as a control signal for setting whether to activate A7. This 3-bit control signal S ₁ is input to a 3-bit decoder 4 provided in the power supply destination setting circuit 3. This 3-bit decoder 4 is provided to activate a predetermined number of unit memory cell arrays based on the input control signal _S1 . In this embodiment, as a specific example of a technique for activating a predetermined number of unit memory cell arrays, the voltage of any one terminal P of output terminals P1 to P7 is set to "L" according to the number of blocks to be activated. An example is shown in which an arbitrary number of blocks can be activated by setting the level.

[0009] For example, if we explain the case of activating four blocks, the operation theory in Figure 2 will be explained. As shown in the diagram, only the third output terminal P3 is set to "L" level, and the other output terminals are set to "L" level. Children P1, P2, and P4 to P7 are set to "H" level. Each output terminal P1 to P7 of the 3-bit decoder 4 receives a control signal of the current supply network 5. No. lines CL1 to CL7 are connected. The current supply circuit network 5 is a power supply circuit 2 to each unit memory cell array A0 to A7. It is provided for supplying these separately.

That is, power supply lines PL0 to PL7 are provided between the power supply circuit 2 and each unit memory cell array A0 to A7, and switching transistors Tr ₀ to Tr are connected to these power supply lines PL0 to PL7. ₇ are interposed respectively. These switching transistors Tr ₀ to Tr ₇ are MOS transistors, and each gate is connected to the output terminals P1 to P7 of the decoder 4 by control signal lines CL1 to CL7.

Transfer gates TG 1 to TG 6 are interposed in these control signal lines CL 1 to CL 6 , and a predetermined transfer gate TG 1 is selected depending on the potentials of the output terminals P 1 to P 7 of the 3-bit decoder 4. By the on/off operation of ~TG6, the switching transistors Tr ₀ to Tr ₇ corresponding to the unit memory cell arrays A0 to A7 to be activated are set to the on state or the off state. As a result, power is supplied to the unit memory cell arrays A0 to A7 of the selected block, and standby current begins to flow. Further, an NMOS transistor is provided between the gate of each switching transistor Tr ₁ to Tr ₆ and the ground, and a potential that is an inversion of the potential of the output terminals P2 to P7 is applied to the gate of each NMOS transistor. It is done like this.

Therefore, when the potential of each output terminal P1 to P7 of the 3-bit decoder 4 is set as shown in FIG. 2, the transfer gates TG1 to TG2 connected to the output terminals P1 and P2 are turned off. Transfer gates TG1 to TG6 connected to output terminals P3 to P7 are turned on. As a result, the "H" voltage of the output terminals P4 to P7 is applied to the PMOS transistors Tr4 to Tr7 provided in the lines PL4 to PL7 that supply power to the fourth to seventh cell arrays _A4 to _A7 . These PMOS transistors Tr ₄ to _{Tr 7} are turned off.

On the other hand, the “L” level voltage of the output terminal P3 turns on the switching transistor Tr ₃ interposed in the line PL3 that supplies power to the third cell array A3. The power supply Vcc is supplied to A3 from the power supply circuit 2. Therefore, a standby current flows through this third cell array A3.

Furthermore, in this case, the switching transistors Tr ₁ and Tr ₂ for the second and third cell arrays A1 and A2 are also turned on, so the power supply Vcc is also applied to these first and second cell arrays A1 and A2. supplied and activated. On the other hand, since the power supply Vcc is not supplied to the fifth cell array A4 to the eighth cell array A7, they are not activated in this case. Note that since the first cell array A0 is always used in any usage method, the transistor Tr ₀ provided for the cell array A0 is always on.

As described above, in the memory cell array of the semiconductor memory device of this embodiment, the memory area to be activated is divided into a plurality of regions using the block division method normally used in SRAM. Therefore, in order to select an arbitrary cell, a row address, a column address, a block address, etc. are required, so three types of decoders are provided. That is, as shown in the configuration diagram of the semiconductor memory device in FIG. 3, three decoders, a row decoder 6, a column decoder 7, and a block decoder 8, are provided, respectively, and a row address signal _SR , a column address signal _SC , and a block address are provided. Signal S _B is applied to each of these decoders 6-8.

The block decoder 8 is provided to generate a signal for activating blocks within a set range, and receives a control signal S ₁ which is commonly applied to the power supply destination setting circuit 3 described above. The activation signal is output to the column decoder 7 and the I/O selection circuit 9 based on the above. In the above embodiment, an example was shown in which the standby current was reduced by not supplying power to the unused storage area, but if the power was not supplied to the decoder corresponding to the unused storage area, the operating current could also be reduced. Therefore, power consumption can be further reduced. In the above embodiment, the case where the cell array is divided into 8 blocks has been described, but any number of divided blocks, such as 16, 32, 64, 128, etc., can be well supported. be able to.

[0017]

[Effect of the idea]

As mentioned above, the present invention is designed to divide the storage area of a large-capacity semiconductor storage device into multiple blocks. In addition to dividing the block into blocks, standby current can be supplied to each block. Therefore, standby current is not consumed in unused storage areas. It can be done. Therefore, the standby current can be reduced depending on the percentage of used area. This enables a significant reduction in power consumption. Therefore, the power consumption High-capacity half-capacity battery operating systems that require reduced power This is particularly effective when a conductive memory device is mounted.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing main parts of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram for explaining the operation of a power supply control circuit.

FIG. 3 is a configuration diagram showing a control system of a semiconductor memory device.

[Explanation of symbols]

1 Memory cell 2 Power supply circuit 3 Power supply destination setting circuit 4 3-bit decoder S ₁ Control signal A0-A7 Unit memory cell P1-P7 3-bit decoder output terminal PL0-PL7 Power supply line CL1-CL7 Control signal line

Claims (1)

[Scope of utility model registration request] 1. A memory cell array that can be divided into an arbitrary number of unit memory cell arrays, and a power supply for activating each of the unit memory cell arrays divided into the plurality of units. A power supply circuit for each memory cell array and a supply destination of the standby current output from the power supply circuit are set, and an arbitrary number of blocks in the unit memory cell array are activated according to the memory capacity to be used. A semiconductor memory device comprising a power supply destination setting circuit.