JPH04125932A - Method of forming bump - Google Patents

Abstract

PURPOSE:To eliminate a surface corresponding with a evaporation copper layer on a wafer, and completely prevent the generation of a copper ring, by forming a metal bump from the state of flat top to a spherical type, eliminating flux, and exfoliating resist. CONSTITUTION:A metal bump is formed by laminating solder-plated layers 103, 104 in order on a lead part 100. Before resist is eliminated, a round solder bump 104b is formed in a spherical type from a state of flat top by low temperature reflow. Flux is eliminated, and resist is exfoliated. A base side surface 104a of the solder-plated layer is vanished by reflow rounding, and a surface corresponding with an evaporation copper layer 105 on a wafer does not exist. When resist is eliminated, very small amount of Sn in release liquid is moved and diffused in the evaporation copper layer 105, and turns to alloy, thereby preventing a copper ring from forming a precurring state. When the next intermediate metal layers 105-107 are eliminated, an alloy layer 105a does not exist.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an intermediate metal layer to be removed after plating when forming a bonding portion (bump) to a printed circuit board on a wafer on which an integrated circuit is formed. (AI, Cr, Cu
) remains in a movable ring shape surrounding each bump.

[Conventional technology]

The integrated circuit manufacturing process includes a bump forming process in which bumps for bonding are formed on the lead portions of ICs formed on the surface of the wafer.

This bump forming process mainly uses a method using vapor deposition and a method using plating, and the present invention is directed to the latter method.

A conventional bump forming method using a plating method will be described below with reference to the drawings. FIG. 3 is a sectional view showing a bump forming process in the conventional process, and FIG. 4 is a flowchart thereof, in which (a) to (e) show each process. Further, FIGS. 5 to 9 show the apparatus for each step used in bump formation, and FIG. 5(A) is a front sectional view of the plating apparatus, and FIG. 5(B) is a side sectional view thereof. FIG. 6 is a schematic diagram of a resist stripping device, FIG. 7 is a schematic diagram of an etching device for Cu, which is one of the intermediate metal layers, and FIG. 8 is a schematic diagram of an etching device for Cr and AI intermediate metal layers. It is. 9th
FIG. 1 is a schematic diagram of a flow device. Also, Figure 10 (a)
2 shows the results of Auger analysis of the vapor-deposited copper outside the copper ring precursor state region, and FIG.

First, each step will be explained based on FIGS. 3 and 4. In step (a), a passivation film 102 is formed on the surface.
A polyimide layer 108 is formed on the wafer W on which the and AI electrodes have already been formed, a resist is formed thereon (not shown), and the lead portions 10 of the IC are formed by exposure and etching.
0 is removed, and then AI, Cr, and Cu are deposited on the wafer surface by vapor deposition as an intermediate metal layer that also serves as a conductive electrode during plating.
From the polyimide layer 108 side, the vapor-deposited aluminum layer 107, the vapor-deposited chromium layer 106. A vapor-deposited copper layer 105 is formed in this order. Next, in step (b), a resist 101 (plating adhesion prevention film) is formed on the front and back surfaces of the wafer W on which the intermediate metal layer has been formed, and the lead portions 100 of each IC are exposed and developed to leave the resist only on the relevant portions. remove. Process (a)
FIG. 3(a) shows the state after steps (b) and (b) have been completed.

Next, step (C) in FIG. 4 is a plating step, and the IC
The lead portion 100 is plated with Cu and solder. The plating shown in FIG. 3(b) is formed using the newly developed cylindrical plating device shown in FIG. The outline of the present cylindrical plating apparatus 110 will be explained with reference to FIG. 5. In FIGS. 5(a) and 5(b), a cylindrical body 113 is housed in a housing 112, and a wafer mounting plate 114 (wafer mounting means) is placed near one end 113a of this cylindrical body 113 at a distance d. and the negative electrode 1 together with the wafer W fixed to the wafer mounting plate 114.
It will be 18. The other end of the cylindrical body 113 is provided with a positive electrode 115 made of solder. Positive electrode 115
A liquid hole 117 is provided in the cylindrical body 113 so that a new plating liquid can enter and exit the cylindrical body 113. The diameter of the cylindrical body 113 and the opening surface formed near one end 113a are formed in a shape that almost matches the planar shape of the wafer, which is effective in obtaining uniform plating. In FIGS. 5(a) and 5(b), 119 is a plating liquid spouting pipe having a nozzle for spouting a liquid for the purpose of stirring around the surface of the wafer W, and uniformly plating within the small head area of the wafer W. It is effective in obtaining. A (+) pole 116a and a (-) pole 116b of a power source are connected to the positive electrode 115 and the negative electrode 118, respectively.

As shown in FIG. 3(b), a copper plating layer 103 is formed on the lead portion 1°O of the IC by the plating process using this device, and a solder layer having a structure similar to that of the copper plating device is formed on the copper plating layer 103. A solder plating layer 104 is formed by a plating device (not shown).
form. The composition of the solder plating layer 104 is 60% Sn.
A material containing 40% Pb is used. However, there is some variation in the composition of Sn within the wafer, and the degree of variation is 50%.
It is around 70%. In step (d) of FIG.
Peeling off the resist 101 as shown in FIG.
A schematic diagram of the resist stripping device will be explained with reference to FIG. 6. 120 is a part of the automatic conveyance device, 121 is a basket grip, 124 is a stripping tank, 124a is an automatic opening/closing lid, and 125 is a part of the automatic conveyance device. It is a self-adjusting heater, and 1
A stirrer 26 constantly stirs the inside of the tank to make the temperature uniform. Although not shown in the figure, the wafer is in stripping tank 1.
24, and when the lid is closed, rocking automatically begins, and the resist peels off. The components of the resist stripper are phenol, dichlorobenzene, tetrachlorethylene, and a surfactant. The temperature of the resist stripping solution is 100C. The phenomenon that occurs during resist peeling will be explained with reference to FIG. 3(b). The solder plating layer 104 is formed to have a substantially constant thickness at both the ends and the center. The shape of the bump formed after plating has a flat top and a bottom surface 104 of the solder plating layer 104.
A faces a vapor-deposited copper layer 105, which is an intermediate metal layer, with a resist 101 having a thickness of 5 microns interposed therebetween. resist 101
As the solder plated layer 104 is peeled off, the stripping liquid instead enters the narrow space and gradually dissolves the Sn in the solder plating layer 104, but since the narrow space is difficult to stir, the concentration of Sn gradually increases. Or the bottom surface 104a of the solder plating layer 104
Since the distance between the evaporated copper layer 105 and the evaporated copper layer 105 is very short, Sn in a high temperature state easily penetrates into the evaporated copper layer 105 through the stripping solution.
It is diffused and alloyed to form a Cu--Sn alloy layer 105a which is a precursor state of a ring as shown by the black area in FIG. 3(C). The above mechanism will be explained using the data in FIG. 10. As can be seen in the Auger analysis in FIG. 10(a), C
Sn is not detected on the U surface portion 105b, but Sn is detected on the Cu surface portion 105a directly below the bottom surface 1°4a of the solder plating layer 104, as shown in FIG.
Since Sn gradually decreased from the surface toward the depth, it is clear that Sn was diffused from the surface toward the inside.

Although not shown, similar results were obtained using an X-sen microanalyzer. Now, in this state, the etching of the intermediate metal layer in step (e) of FIG. 4 begins. This results in a copper ring 105c.

A schematic diagram of an etching apparatus for the vapor deposited copper layer 105 of the intermediate metal layer will be explained with reference to FIG. 7. Reference numeral 123 is a basket for wafers, 128 is a copper ammonia-based copper etching tank with the trade name of Enstrip C, and 129 is an air introduction pipe having an air hole 129b for air stirring.

Next, a schematic diagram of the etching apparatus for Cr and AI of the intermediate metal layers 106 to 107 will be explained with reference to FIG. 8. Reference numeral 131 is a self-adjusting heater, and reference numeral 130 is a heating device in which a mixed solution of Felician northern suum and NaOH is placed. 132 is a Cr and AI etching tank, and 132 is a water washing tank.

The wafer W is first immersed in the Cr, AI etching tank 130 described above, and after uniformly removing the intermediate metal layers 106 to 107 by swinging in the direction of the arrow 130a for a predetermined time, the wafer W is transferred to the rinsing tank 132. Then, wash with water according to the arrow 132a. As a result, the Cu-Sn alloy layer is not etched by the etchant in the Cr and AI etching tank 130, so as shown in FIG.
Everything except a disappears, producing a copper ring 105c. The resulting copper ring 105c moves with a flop because there is no support.

This ease of movement becomes even greater when the shape shown in Figure 3 (E), which shows the state after high temperature reflow in Figure 4 Step (F), is reached.
This may cause a short circuit. To explain a schematic diagram of high temperature reflow using FIG. 9, W is a wafer, 133 is a flux discharge port, 134 is a spinner, 13
5 is a conveyor belt, 136 is a heating section, 137
is a nitrogen inlet, 138 is an exhaust port, and 139 is a flux reservoir. Because the surface oxide is removed by the flux and the bump is melted by heating, the bump is formed into a shiny, completely smooth spherical shape as shown in FIG. 3 (E). Due to this reflow, the above-mentioned copper ring 105c becomes clearly visible and becomes flaky in the vicinity. Finally, in step (g), flux cleaning is performed to complete the bump.

[Problem to be solved by the invention]

In the above-mentioned bump formation method, after plating, the resist is removed (Fig. 3 (c)) and the intermediate metal layer is removed (Fig. 3 (d)).
) and solder layer reflow (see (e) in the same figure), the intermediate metal layer remains as a movable copper ring 105c around each bump, especially in the case of eutectic solder with about 60% Sn. -Once formed, the ring will not break easily;
It moves freely and is conductive, so it can easily connect adjacent bumps and ICs.
There is a risk of short-circuiting due to contact with the outside of the chip. In particular, when the composition of the solder is close to eutectic with about 60% Sn, the Sn content is high, so it dissolves in the stripping solution often, and there is a probability that a copper ring 105c will occur due to migration, penetration, and alloying into the vapor-deposited copper layer 105. is high and large. copper ring 10
Methods for removing 5c are not easy, and methods such as spray cleaning and ultrasonic cleaning are ineffective. Physical removal using a brush may be a relatively effective method, but it is not easy to completely remove the copper rings formed around the huge number of bumps on the wafer. Removal requires strong force, which may result in damage to the surface of the bump 104b or the polyimide layer 108, or cracking of the wafer, leading to a decrease in yield. To avoid this, when brushing under water, the copper ring 105C
is a thin piece with a thickness of about 1 micron and is soft, so it adheres to the wafer surface and is difficult to remove. Furthermore, manual removal not only obstructs automation but also increases costs, making it impossible to meet the demand for cost reduction. still,
As explained above, copper rings appear more prominently as the Sn content of the solder plating layer increases, but when the Sn content exceeds about 20%, the risk of copper rings occurring increases.

The present invention was made in view of these circumstances.
It is an object of the present invention to provide a bump forming method that can fundamentally prevent the occurrence of copper rings 105C, which are the remains of the intermediate metal layer, and can improve the yield of IC chips.

[Means to solve the problem]

In order to achieve the above object, the bump forming method of the present invention includes:
After bump formation by plating, a first reflow is performed at a low temperature before removing the resist, then after the resist is peeled off, the intermediate metal layer is etched, and finally, a reflow is performed at a high temperature.

In a preferred embodiment, reflow is performed at a low temperature of around 210° C. to prevent solder from flowing on the wafer surface before removing the resist. In addition, in a preferred embodiment, a shiny metal surface suitable for bonding can be obtained when using eutectic solder, since it is 260°C or higher, so after removing the resist and intermediate metal layer, high-temperature reflow at 260-280°C is performed. It is possible to form a complete bump without forming a copper ring.

[Effect]

Since the present invention has the above-described configuration, by performing low-temperature reflow before removing the resist, the shape of the solder bump is changed from a flat top to a spherical shape.
Bottom surface 1 of vapor deposited copper layer 105 and solder plating layer on wafer
Therefore, when removing the resist, a narrow and long gap of 5 micrometers between the bottom surface 104a of the solder plating layer 104, which has a flat top as in the conventional case, and the vapor-deposited copper layer 105 can be eliminated. A small amount of Sn is dissolved in the resist stripping solution, and immediately penetrates into the intermediate metal layer, diffuses, and alloys to prevent the formation of a precursor state of a copper ring.

Therefore, when removing the resist after plating as in the past,
It is possible to avoid a situation in which the bottom surface 104a of the solder plating bath 104 having a flat top and the intermediate metal layer 105 face each other over a wide area with a narrow gap of 5 microns,
Therefore, the Sn in the solder dissolved in the stripping solution moves, infiltrates, and diffuses into the vapor-deposited copper layer 105 while maintaining a constant concentration, thereby preventing the formation of an alloy of the Cu5n alloy layer 105a, and thus becoming a precursor state of a copper ring. prevent. Next, when removing the intermediate metal layers 105 to 107, the copper ring 10 is removed because the Cu-Sn alloy layer 105a is not present.
5c does not occur at all.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1C show cross-sectional views of a bump in the main steps of an embodiment of the bump forming method of the present invention. FIG. 2 is a flowchart of the main steps of an embodiment of the bump forming method of the present invention. 1 and 2, steps (a) to (i) of the bump forming process of this example are shown.
) will also be explained. First, steps (a) to (c)
Up to this point, the technology is the same as the conventional technology, and Figure 1 (A) is the same as (C).
This shows the state at the end of the plating process. That is, resist 101 (solder adhesion prevention film) is applied to the front and back surfaces of the wafer.
After exposing the lead part 100 of each IC to remove the resist 101 only in that part, plating is performed using a cylindrical plating bag [110] shown in FIG. A copper plating layer 103 is formed on the copper plating layer 103, and a solder plating layer 104 is further laminated on top of the Cu plating layer.Next, the process moves to step (h), where the resist is not removed and the solder plating layer 104 is laminated at a low temperature for 20 minutes.
By performing low-temperature reflow at 0-230°C, round solder bumps 104b are formed as shown in FIG. 1(b). Low-temperature reflow cannot completely remove surface coatings 109 such as oxide films and cannot provide gloss. However, if the resist is strong, can withstand high temperatures, and does not cause solder flow due to cracks, it is possible to raise the temperature as described above. be. Next, in the flux cleaning step (i), it is necessary to use flux in the solder paste flow rounding, but since the flux used fuses with the resist at the interface, some cysts 101 may be formed when it is dissolved in the flux cleaning tank. Peel off. This causes a problem that leads to partial contamination of the flux cleaning tank, but this can be easily removed by filter filtration. Next, in step (d), the remaining resist portion is stripped off using a resist stripping solution using the resist stripping apparatus shown in FIG. 6 (FIG. 1(c)). At this time, the vapor deposited copper layer 10
The bottom surface 104a of the solder, which faces the solder surface 104a through a thin resist layer with a resist thickness of 5 microns, no longer exists due to disappearance due to reflow rounding, so even if Sn dissolves in the stripping solution, it will not immediately reach the vapor deposited copper layer 1.5. do not have. In addition, Sn is not confined in a narrow space (because it is constantly stirred, Sn is not trapped in a narrow space).
The concentration of n does not become high. Therefore, the Cu--Sn alloy layer 105a, which is a precursor state of a copper ring, is not formed due to Sn entering and diffusing into the vapor-deposited copper layer 105 of the intermediate metal layer. Therefore, in the next step (e), after etching the intermediate metal layers Cu, Cr, AI, the copper ring 1 is etched.
05c does not occur (Fig. 1 (d)). (f) is a high-temperature reflow process, and in a preferred embodiment, a second reflow is performed at a high temperature as a final process to compensate for insufficient gloss on the solder surface, surface oxide film, and insufficient removal of impurities during low-temperature reflow. High temperature reflow is preferably 270C-280C. Finally, flux cleaning is performed in step (g) to complete the bump shape as shown in FIG. 1(d).

A feature of the present invention is that the low-temperature reflow step of step (h) and the flux cleaning step of step (i) are added before the resist stripping of step (d), and the ref opening is formed by the low-temperature reflow step of step (h) and the flux cleaning step of step (i). (f) High-temperature reflow is a two-turn flow system.

〔Effect of the invention〕

As explained above, according to the bump forming method of the present invention, the formation of Cu'J rings after etching the intermediate metal layer can be completely prevented, and therefore bumps can be formed with solders of all compositions including eutectic solder. becomes possible. Furthermore, according to the process of the present invention, it is possible to prevent the formation of the copper ring 105c, which has been thought to be difficult, with a simple configuration and low-cost equipment.

[Brief explanation of drawings]

FIGS. 1A to 1D are cross-sectional views showing the main steps of an embodiment of the bump forming method of the present invention, and FIG. 2 is a flowchart of the main steps of the same. Figure 3 (a)
-(e) are cross-sectional views showing the bump forming process in the prior art, and FIG. 4 is a flowchart of the main steps in the prior art. FIG. 5(A) shows a sectional front view of the wafer plating apparatus, and FIG. 5(B) shows a sectional side view. FIG. 6 is a partially cutaway perspective view of a resist stripping device, FIG. 7 is a perspective view of an etching device for the intermediate metal layer CU, FIG. 8 is a perspective view of the intermediate metal layer Cr and AI etching device, and FIG. 9 is a beam flow. FIG. 3 is a cross-sectional front view of the device. Figure 10 (a) is a diagram showing the Auger analysis data of a part other than the copper ring precursor state on the copper surface of the intermediate metal layer, and Figure 10 (b) is a diagram showing the results of the Auger analysis data of the precursor state part. It is. 100-I C lead part, 101--Resist, 10
3-m-copper plating layer, 104-solder plating layer, 10
5--Vapor deposited copper layer, 105 a--Cu-Sn alloy layer, 105 c-Copper ring, 107...-Vapor deposited aluminum layer, 1
13--Cylindrical body, 114-Wafer mounting plate, 11
5-Positive electrode, 118--Negative electrode, 119-Plating jetting vibe, 121--Basket grip, 123--Basket, 124--Peeling tank, 128
-・Copper etching bath, 129b-・-Air hole, 13 (L
---Chromium, aluminum etching tank, 131-heater,
133-・Flux discharge port, 134-Spinner 1
35--Transport belt, 136-Heating section, 201--Auger analysis data, Auger analysis data.

Claims (1)

[Claims] A step of forming a pattern, a step of applying resist leaving an opening, a step of forming Cu plating on the opening, a step of plating eutectic solder on the Cu plating to form a bump, and applying the resist. In a bump forming method comprising a step of peeling and a step of rolling solder by reflow, a preliminary reflow step is provided between the step of forming the bump bump and the resist peeling step, and then main reflow is performed. A method for forming a bump, characterized in that: