JPH04125686A - Picture signal processor - Google Patents

Abstract

PURPOSE:To operate a hard copy by exact picture data without interrupting other processings by reading out the picture data stored in a picture buffer memory in a longer cycle than the synchronizing signals of video signals, and outputting hard copy signals. CONSTITUTION:The contents of pictures stored in a video memory 16 are stored in a picture buffer memory 21. Then, a timing controlling part 23 reads out the contents stored in the picture buffer memory 21 in the longer cycle than the horizontal synchronizing signals and vertical synchronizing signals of the video signals. Therefore, a hard copy picture can be obtained after printed by a printer device based on the data read out of the picture buffer memory 21, and reading signals from the timing controlling part 23. Thus, the hard copy can be operated by the exact picture data without interrupting the other processings in order to operate the hard copy.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention has a video memory for storing image data, and outputs a video signal for displaying the contents of the image data on a display device. The present invention relates to an image signal processing device configured as follows.

[Conventional technology]

-IIQ, in personal computers, workstations, etc., it is possible to create, edit, process, etc. various image signals depending on the application, and display the created image or the image in the process of being created on the screen of a display device. configured so that it is possible.

For example, in CAD (computer-aided design),
Drawings are created on the screen by operating the keyboard and mouse. However, in addition to displaying these drawings in progress or completed drawings on a screen, there are often cases where it is desired to print them on paper (hard copy) for storage or consideration.

FIG. 9 is a block diagram showing the configuration of a conventional hard copy system 90a.

In FIG. 9, a hard copy system 90a has a computer main body 91 provided with a video signal output connector 91a, and this video signal output connector 91a has a
A display device 92 is connected via a cable 93, a video IF unit 94 is connected to a video signal output connector 91a by branching the cable 93, and a printer device 95 is further connected to an output connector of the video IF unit 94. It is configured.

The frequencies of the video signal S21 output from the video signal output connector 91a are, for example, a video frequency (pixel frequency) of approximately 100 MHz, a vertical synchronization frequency of 60 Hz, and a horizontal synchronization frequency of 64 KHz. The video IF unit 94 has a built-in AD converter for converting the video signal S21 into a digital signal, and is configured to output the converted digital signal to the printer device 95.

FIG. 10 is a block diagram showing the configuration of another conventional hard copy system 90b.

In FIG. 10, a computer main body 91 includes a video signal output connector 91a and an interface specification for a printer device 95 (for example, Centronics compliant, 0F-I
output connectors 91b (such as B) are provided, and are connected to the display device 92 or printer device 95 via cables 93a93b, respectively.

[Problem to be solved by the invention]

However, in the hard copy system 90a shown in FIG. 9, by using the video IF unit 94, it is possible to perform hard copying even from the computer main body 91 having only the video signal output connector 91a. Since the high-frequency video signal S21 is directly converted into a digital signal using an AD converter, it is easily affected by noise, etc., and it is difficult to perform data conversion accurately, resulting in noise in the hard copy image. There are problems in that it is difficult to maintain high image quality, such as distortion and density, and differences in density and hue from the original image.

In addition, since the video IF unit 94 requires the use of an expensive high-speed AD converter and high-speed memory, the video IF unit 94
Another problem was that the manufacturing cost of the unit 94 was high.

The hard copy system 90b shown in FIG. There is also the problem that other processes are often interrupted while the system is running, and processing performance is reduced accordingly.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide an image signal processing device that does not interrupt other processing to perform hard copying and can perform hard copying with accurate image data each time. There is.

(Means for Solving the Problems) In order to solve the above-mentioned problems, an image signal processing device according to the present invention includes a video memory for storing image data, and displays the contents of the image data on a display device. An image signal processing device configured to output a video signal for processing, an image buffer memory for storing at least a part of the image data stored in the video memory; and a timing control section for reading the image data at a longer cycle than the horizontal synchronization signal and the vertical synchronization signal of the video signal and outputting the hard copy signal.

Note that in this specification, the vertical synchronization signal refers to
Frame (includes 1 field in case of ink race)
Or, it is a signal for synchronizing each page, for example, a page break signal is included, and a horizontal synchronization signal is a signal for synchronizing each line or line, for example, a line feed signal is included. .

[Function] The image buffer memory stores part or all of the content of the image stored in the video memory.

The timing control unit reads out the contents stored in the image buffer memory at a cycle longer than the horizontal synchronization signal and the vertical synchronization signal of the video signal.

Based on the data read from the image buffer memory and the read signal from the timing control unit, a hard copy image is obtained by printing by a printer device or the like.

〔Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 8 is a block diagram showing the configuration of the hard copy system 1 according to the present invention.

The hard copy system 1 includes an image signal processing device 2 such as a computer, a display device 3, and a printer device 4, each connected to a dedicated connector provided on the image signal processing device 2.

FIG. 1 is a block diagram of an image signal processing device 2 according to the present invention.

The image signal processing device 2 includes CPUI L ROMI2, R
AM13, input/output interface 14, graphic controller 15, frame memory 16, CPU bus 17
, DA converter 18, and hard copy signal output section 20
have.

The CPU 1 performs creation, editing, processing, etc. of various image signals based on programs stored in the ROM 12, and controls the entire image signal processing device 2.

An input device (not shown) is connected to the input/output interface 14, and data and commands are input thereto.

The graphic controller 15 performs graphic drawing processing of various curves, circles, polygons, etc., and also sends signals S1 for controlling reading and writing of data to the frame memory 16;
It generates a horizontal synchronizing signal H3YNC1, a vertical synchronizing signal VSYNC1, and a video clock signal VCK for display (for video signal SVI).

In this embodiment, the number of frames per second for display is 60 (therefore, the period of the vertical synchronization signal VSYNC is 1/60th of a second), and the number of lines (number of horizontal scanning lines) in one frame for display is 1070. , the number of effective lines is 1024 excluding the beginning and end parts.
It's a book. The effective number of pixels (dots) in one line is 1024 pixels, and the gradation of each pixel is 256 gradations (
8 bits).

The frame memory 16 has R (red), G (green), and B (blue).
This is a bitmap-type rewriteable memory that has a capacity to store one frame worth of images for each color.

The DA converter 18 converts the image data S2 read from the frame memory 16 into a video signal S3 which is an analog signal.
(R signal, G signal, B signal).

The hard copy signal output unit 20 creates and outputs various signals for hard copy (for hard copy signal SHC) from the image data S2, a synchronization signal for display, and the like.

The hard copy signal output section 20 includes a line buffer 21,
It consists of a discrete converter 22 and a timing control section 23.

The line buffer 21 is a FIFO memory (first-in, first-out memory) capable of storing 16 lines of R, G, and B image data S2.

The discrete converter 22 has a line buffer 21 for each color.
The parallel image data S4 read out from the image data S4 is converted into serial image data S5.

The timing control unit 23 stores 1024 lines of image data S2, which are valid lines in the 11th period (1 frame) of the vertical synchronization signal VSYNC for display, in the line buffer 21 for 16 lines for each frame for display. This is controlled so that it is read out within the period of one frame for display and output as image data S5 for hard copy.

FIG. 2 is a block diagram of the timing control section 23.

The timing control section 23 includes a frequency divider 31, an input timing signal generation section 32, a write signal generation section 33, a horizontal counter 34, a clock oscillator 35, and a clock counter 3.
It consists of 6.

The frequency divider 31 is a vertical synchronizing signal VSYN for display.
A vertical synchronizing signal VSYNCH for hard copy is generated by dividing C by 1/65.

The input signal generator 32 generates an input timing signal S6 for controlling the timing of inputting (writing) the image data S2 to the line buffer 21.

The write signal generator 33 generates a write signal S7, which is a write pulse for each pixel of the image data S2 to the line buffer 21.

The horizontal counter 34 receives a horizontal synchronization signal H for hard copy.
An output timing signal S8 for controlling the timing of output (reading) from the 3YNCH3 and the line buffer 21 is generated.

The clock counter 36 counts clock pulses (for example, 10 to 20 MHz) generated by the clock oscillator 35 and outputs a horizontal synchronization signal H3YNCH for display.
data clock signal DACK and data clock signal DA having 8192 pulses in one cycle of
The frequency of CK is divided into 1/8 to output a doso I clock signal DOCK having 1024 pulses.

Next, the operation of the hard copy signal output section 20 will be explained with reference to a timing diagram.

3 to 5 are timing diagrams showing the states of signals in each part.

As shown in FIG. 3, the input timing signal S6 is generated by counting horizontal synchronizing signals H5YNC after the first vertical synchronizing signal VSYNC is output, and counting 16 horizontal synchronizing signals H5YNC after a valid horizontal synchronizing signal H5YNC is output. It remains on until the horizontal synchronizing signal H3YNC finishes counting.

After that, when 1070 horizontal synchronization signals H3YNC are counted, the input timing signal S6 is turned on again and 16
It remains on until the count of horizontal synchronizing signals HSYNC is completed.

This operation is repeated 64 times. Then, during the 65 frames for display, the input timing signal S6
is turned on 64 times, for 1024 lines (16 lines x 64
The image data s2 of times) are sequentially written to the line buffer 21.

In other words, after the first vertical synchronization signal VSYNC, the 1st to 16th lines of the first frame are the same, and after the second vertical synchronization signal VSYNCO, the 17th to 32nd lines of the second frame are the third vertical synchronization signal VSYNC. After that, 16 lines of image data S2 are written to the line buffer 21 every time the vertical synchronization signal VSYNC is output, and so on from the 33rd to the 48th lines of the 3rd frame, and after the 64th vertical synchronization signal VSYNCO. Then, lines 1008 to 1o24, which are the last effective lines of the 64th frame, are written.

In FIG. 4, after the first vertical synchronization signal VSYNC,
The timing at which the image data S2 of the 1st to 16th lines of the frame is written is shown.

That is, while the input timing signal s6 is on, the image data S2 for each pixel is written to the line buffer 21 in synchronization with the write signal S7.

The write signal S7 is a signal synchronized with the video clock signal VCK for display, and is a signal synchronized with the input timing signal S.
It is output while 6 is on. therefore,
The number of pulses of one write signal S7 is 1024 (
(number of pixels in one line)×16 (number of lines). In addition,
Even in this case, the output timing of the write signal S7 is controlled so that only valid pixels excluding pixels at the beginning and end of one line are written to the line buffer 21.

The image data S2 written to the line buffer 21 is
10 for subsequent display immediately after being written.
During a period of 70 lines (1 frame), the contents written first are read out in synchronization with the dot clock signal DOCK.

FIG. 5 shows the horizontal synchronization signal HSYNC for hard copy.
The states of the dot clock signal DOCK and the data clock signal DACK are shown.

Since the image data S4 read from the line buffer 21 is 8-bit parallel data, it is converted into serial data by the parallel-to-serial converter 22 and output as image data S5. The data clock signal DACK is used as a shift clock pulse for the parallel-to-serial converter 22.

In this way, the image data S2 for one frame for display is divided into 64 lines of 16 lines for each frame.
The image data S4 for one frame is read out at a speed of 1/65 of the period of the video signal SVI, and the hard copy signal S4 is stored in the line buffer 21 in batches.
Since the hard copy signal SHC is output as HC (image data S5), the frequency of the hard copy signal SHC is significantly lower than that of the video signal SVI, making signal processing easier, and the circuit elements used for it can be low-speed. It becomes a cost.

Further, since only the valid image area is output as the image data S5, the configuration of the printer device 4 that receives the image data and makes a hard copy becomes simple, and costs can be reduced.

Also, the image data S read out from the frame memory 16
Since the image data S5 is output based on 2, there is no need to use a high-speed AD converter or DA converter as in the past, and there is no influence of noise, etc. on the hard copy image, and there is no need to use a high-speed AD converter or DA converter. There is no problem that the image color or hue is different from the original image.

In addition, since the hard copy signal SHC is always output in parallel with the video signal SVI, hard copies can be made by the printer device 4 or the like whenever necessary, and other processing can be performed to make hard copies. There are no interruptions.

FIG. 6 shows an image signal processing device 2 according to another embodiment of the present invention.
FIG.

In the image signal processing device 2a, the image signal processing bag! Parts having the same functions as those in FIG.

Hard copy signal output section 20a of image signal processing device 2a
has a frame memory 41 separate from the display frame memory 16, a parallel-to-serial converter 42, and a timing control section 43.

The timing control unit 43 outputs a control signal S9 similar to the manual timing signal S6, write signal S7, and output timing signal 38 of the timing control unit 23, and also outputs an address for specifying a read address of the frame memory 41. Outputs designated signal SIO.

According to the write signal Slb and the address designation signal 5lcd, image data with the same content is written to the frame memory 41 at the same time as writing to the frame memory 16.

The image data written in the frame memory 41 is read out by the display readout signal Sl by the control signal S9 and address designation signal SIO from the timing control unit 43.
a or vertical synchronization signal VSYNC and horizontal synchronization signal HS
It is read independently from YNC, and the parallel-serial converter 4
2, it is converted into serial image data S5 and output.

According to the hard copy signal output section 20a of this embodiment,
It is possible to make the synchronization signal for the hard copy completely independent of the signal for the display, the timing control section 43 can be simplified, and appropriate hard copy image quality and processing speed can be obtained. The period of the synchronization signal can be set according to the content of the hard copy image, the performance of the printer device 4, etc. so that

Furthermore, the synchronization signal for hard copy does not require strict periodicity compared to the synchronization signal for display.
The degree of freedom in designing the hard copy signal output unit 20a and the input interface circuit of the printer device 4 is improved, and image quality is less likely to deteriorate due to malfunction.

Further, since data different from that in the frame memory 16 for display can be written in the frame memory 41 for hard copy, it is possible to perform a heart copy by writing data to which, for example, date, time, etc. have been added.

FIG. 7 is a block diagram showing an example of the input interface section 50 of the printer device 4. As shown in FIG.

The input interface unit 50 includes a line counter 51, a dot counter 52, a gradation bit number counter 53, latch units 54 to 56, a memory control unit 57, and a Shirihara jF[H5
s, a frame memory 59, a CPU bus 60, and the like.

A hard copy signal is input to the input interface unit 50 from the image signal processing device 2 .

The line counter 51 receives 1 of the vertical synchronization signal VSYNCH.
The number of horizontal synchronization signals H3YNCH is counted within the period.

The dot counter 52 receives 1 of the horizontal synchronizing signal HSYNCH.
The number of dot clock signals DOCK is counted within a period.

The gradation bit number counter 53 receives the dot clock signal DO.
Within one cycle of CK, data clock signal DACK
Count the number of pieces.

The latch parts 54 to 56 each have a line counter 51.
, dot counter 52, and gradation bit number counter 53
Latch the maximum value counted by .

Therefore, the number of lines of one frame is stored in the latch section 54, the number of pixels of one line is stored in the latch section 55, and the number of pixels of one line is stored in the latch section 56.
The number of gradation bits of one pixel is stored in each.

These data (parameters) are read into the CPU 61 via the CPU hash 60, and then sent to the memory control unit 5.
7, the image data S5 is sequentially written into the frame memory 59. At this time, the frame memory 59 is addressed in accordance with the parameters obtained from the latch units 54-56.

For example, a start address for writing to the frame memory 59 is set in the memory control unit 57, the vertical synchronizing signal VSYNCH is used as a trigger for starting, and 1 byte of image data Sll is written every dot clock signal DOCK.

In this embodiment, since the gradation is 8 bits, the serial image data S5 is converted into byte-based image data Sll for each 1i# element by the serial-to-parallel converter 58 and the data clock signal DACK.

The image data Sll written in the frame memory 59 is read out under the control of the CPU 61, and then subjected to scaling processing such as enlargement or reduction, vertical/horizontal conversion processing, gradation correction, color correction, etc. as necessary. A hard copy image is obtained by printing on paper by a printing mechanism (not shown).

As mentioned above, the image signal processing device! By providing the hard copy signal output units 20, 20a in the hard copy signal output units 2, 2a and the input interface unit 50 in the printer device 4, it is possible to easily make a hard copy of the image displayed on the screen of the display device 3. .

Moreover, the hard copy signal SHC is constantly inputted to the printer device 1:4 from the hard copy signal output units 20, 20a of the image signal processing devices 2, 2a, and in the printer device 4, the line counter 51, dot counter 52. The gradation bit number counter 53 calculates the number of horizontal synchronizing signals H3YN of one frame (vertical resolution), the number of line dot clock signals DOCK (horizontal resolution), and the number of gradation bits. Since it is constantly counted, just by connecting the printer device 4 and the image signal processing device 2.28, the printer device 4 is automatically counted.
The operating mode of is set according to the hard copy signal SHC.

In the above embodiment, the case where the gradation is 8 bits has been explained, but the gradation may have a number of bits other than this. For example, if the gradation is 1 bit (no gradation), , the parallel-to-serial converter 22.42 is converted to 8 of the image data S4.
It suffices to operate to convert each pixel into 1-byte data. In this case, the data clock signal DACK can be omitted because it has the same period as the dot clock signal DOCK. Further, the number of lines in a frame, the number of pixels in one line, the number of lines stored in the line buffer 21, etc. may be set to various values other than those described above.

In the above embodiment, the timing control section 2343, the memory control section 57, the hard copy signal output section 20.20a
, configuration of input interface unit 50, image signal processing device F2.2a, printer device 4, hard copy system l
The configuration of each part and the content of signals can be changed in various ways other than those described above.

[Effects of the Invention] According to the present invention, it is possible to provide an image signal processing device that can perform hard copying using accurate image data without interrupting other processes to perform hard copying.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image signal processing device according to the present invention, FIG. 2 is a block diagram of a timing control section, and FIGS.
6 is a block diagram of an image signal processing device according to another embodiment of the present invention; FIG. 7 is a block diagram illustrating an example of an input interface section of a printer; FIG. 8 is a block diagram showing the configuration of a hard copy system according to the present invention, FIG. 9 is a block diagram showing the configuration of a conventional hard copy system, and FIG. 1O is a block diagram showing the configuration of another example of a conventional hard copy system. FIG. l... Hard copy system, 2, 2a... Image signal processing device, 3... Display device, 16... Frame memory (video memory), 21... Line buffer (image buffer memory), 23 ...Timing control unit, 41...Frame memory (image buffer memory), 43...Timing control unit, VS'l'NC/vertical synchronization signal of the video signal, H3YNC...Horizontal synchronization signal of the video signal , SVI...video signal, SHC...
...Hardcopy signal.

Claims (1)

[Claims] (1) In an image signal processing device having a video memory for storing image data and configured to output a video signal for displaying the contents of the image data on a display device, the image data is stored in the video memory. an image buffer memory for storing at least a part of the image data stored in the image buffer memory; and an image buffer memory for reading out the image data stored in the image buffer memory at a cycle longer than a horizontal synchronization signal and a vertical synchronization signal of the video signal and converting the image data into a hard copy. An image signal processing device comprising: a timing control section for outputting a signal.