JPH04124823A - Manufacture of semiconductor wafer - Google Patents
Manufacture of semiconductor waferInfo
- Publication number
- JPH04124823A JPH04124823A JP24380090A JP24380090A JPH04124823A JP H04124823 A JPH04124823 A JP H04124823A JP 24380090 A JP24380090 A JP 24380090A JP 24380090 A JP24380090 A JP 24380090A JP H04124823 A JPH04124823 A JP H04124823A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- mirror
- mirror surface
- double
- semiconductor wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000005498 polishing Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 abstract description 10
- 230000001681 protective effect Effects 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 230000006866 deterioration Effects 0.000 abstract 1
- 238000005406 washing Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 239000002245 particle Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 101100129500 Caenorhabditis elegans max-2 gene Proteins 0.000 description 1
- 241001609213 Carassius carassius Species 0.000 description 1
- 241000257465 Echinoidea Species 0.000 description 1
- 229910003638 H2SiF6 Inorganic materials 0.000 description 1
- 235000019892 Stellar Nutrition 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- ZEFWRWWINDLIIV-UHFFFAOYSA-N tetrafluorosilane;dihydrofluoride Chemical class F.F.F[Si](F)(F)F ZEFWRWWINDLIIV-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は半導体ウェハ、特にシリコンウェハの表裏の面
の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming the front and back surfaces of a semiconductor wafer, particularly a silicon wafer.
(従来の技術)
シリコンウェハの製造は周知のように、以下ののような
工程で行なわれる。(Prior Art) As is well known, silicon wafer manufacturing is performed through the following steps.
シリコン多結晶の準備−単結晶引上げ
一スライス→ベベリングーラッピング
−エツチング→ポリッシング→洗浄
この工程のうち本発明に関連するのは、ウェハの面を平
坦にして鏡面にするラッピング−ポリッシングの工程で
あり、その部分についての従来の方法を以下に説明する
。Preparation of silicon polycrystal - single crystal pulling - one slice → beveling - lapping - etching → polishing → cleaning Of these steps, the one that is relevant to the present invention is the lapping-polishing process to flatten the surface of the wafer and make it mirror-like. , the conventional method for that part will be explained below.
第2図はラッピング装置の構成を示すものであり、通常
(b)図の両面同時う・リビング法が使用される。これ
は(a)図に示す片面ラッピング法では、ウェハ固定プ
レート13に貼り付けられるウェハ11が該プレート1
3に完全平行とならない点があり、またそのプレート1
3とラップ板12も完全平行にならないので、ラッピン
グ後のウェハ平坦度(通常TTVと呼ばれる)が悪くな
るためである。TTVが悪くなる主な原因はウニへ面が
テーパ状に仕上がることによる。FIG. 2 shows the configuration of the wrapping device, and the double-sided simultaneous wrapping and living method shown in FIG. 2(b) is usually used. This is because in the single-sided lapping method shown in FIG.
3 has a point that is not completely parallel, and that plate 1
This is because the wafer 3 and the lapping plate 12 are not completely parallel to each other, resulting in poor wafer flatness (usually referred to as TTV) after lapping. The main reason for poor TTV is that the surface of the sea urchin is finished in a tapered shape.
(b)図の両面同時ラッピング法は、上ラップ板15と
下ラップ板14が互いに反対方向に回転し、それに挾ま
れる形でキャリア16が自転するため極めて平坦度のよ
いウェハ11が仕上がる。In the double-sided simultaneous lapping method shown in FIG. 12(b), the upper lapping plate 15 and the lower lapping plate 14 rotate in opposite directions, and the carrier 16 rotates on its own axis while being sandwiched between them, resulting in a finished wafer 11 with extremely good flatness.
即ちTTV1μm以下のラップウェハを容易に製作でき
る。That is, a lap wafer with a TTV of 1 μm or less can be easily manufactured.
このラッピング工程が終ると、次にラップによる加工歪
を除去するために薬液によるエツチングを行なう。After this lapping process is completed, etching is performed using a chemical solution to remove processing distortion caused by lapping.
次いで、ウェハの面を鏡面に仕上げるためにボノッシン
グ工程に入る。このポリッシング法にも片面ポリッシン
グ法と両面ポリッシング法とがあり、現状では片面ポリ
ッシング法が用いられている。装置としては前述のラッ
ピング装置と同様の構成であるので割愛するが、両面ポ
リッシング法では両面ラッピング法と同様の理由で平坦
度の良いウェハができる。第3図(a)に片面ポリッシ
ングウェハのTTV値の測定例、同図(b)に両面ポリ
ッシングウェハのTTV値の測定例を示したが、これか
らも解るように両面ポリッシングウェハの方がTTV値
が小さい。これはウェハ面のテーパ成分が小さいことに
よる。しかしながら、両面ポリッシング法では裏面も鏡
面となるため、以下の問題点が生じ現在実用化されてな
い。即ち(a)ウェハの表面と裏面ともに鏡面であるた
め表裏の区別がつきにくい。Next, a bonoshing process is performed to finish the surface of the wafer to a mirror finish. This polishing method also includes a single-sided polishing method and a double-sided polishing method, and the single-sided polishing method is currently used. The device has the same configuration as the lapping device described above, so it will not be described here, but the double-sided polishing method produces wafers with good flatness for the same reason as the double-sided lapping method. Figure 3 (a) shows an example of measuring the TTV value of a single-sided polished wafer, and Figure 3 (b) shows an example of measuring the TTV value of a double-sided polished wafer. is small. This is due to the small taper component of the wafer surface. However, in the double-sided polishing method, the back side also becomes a mirror surface, which causes the following problems and is not currently in practical use. That is, (a) since both the front and back surfaces of the wafer are mirror surfaces, it is difficult to distinguish between the front and back surfaces.
(b)裏面を真空吸着する製造装置では、−度真空吸引
されたウェハが、その真空を切ってもステラ(チャック
)から離れないことがある。(b) In a manufacturing apparatus that vacuum-chucks the back side, a wafer that has been vacuum-suctioned to a certain degree may not separate from the stellar (chuck) even after the vacuum is turned off.
(C)製造工程中各種治工具などを用いるが、それとの
接触により、裏面の汚染が目立つ。(C) Various jigs and tools are used during the manufacturing process, and the back surface becomes conspicuously contaminated due to contact with them.
(d)ステッパなどの露光装置で、ウェハ裏面に付着し
た微小パーティクルにより、ウェハ裏面が局部的に凸状
となりパターン不良が発生し、歩留まりを低下させる。(d) In an exposure device such as a stepper, minute particles adhering to the back surface of the wafer cause the back surface of the wafer to become locally convex, causing pattern defects and reducing yield.
(発明が解決しようとする課題)
前述したように、両面ポリッシング法では面の平坦度は
良いが問題点が多いので使用されてないし、現在使用さ
れている片面ポリッシング法では第3図(a)に示すよ
うに平坦度が悪い。同図で解るように、今後の16M”
DRAMなどで要求されるTTV値MAX2μm以下
は達成できていない。このTTVが大きいのはウェハ面
のテーパ成分が大きいことによる。(Problems to be Solved by the Invention) As mentioned above, the double-sided polishing method has good surface flatness, but has many problems, so it is not used, and the currently used single-sided polishing method is shown in Figure 3 (a). As shown in the figure, the flatness is poor. As you can see in the figure, the future 16M”
The TTV value of MAX 2 μm or less required for DRAM etc. has not been achieved. This TTV is large because the taper component of the wafer surface is large.
本発明はこれら両者の欠点を解決しようとするものであ
り、平坦度が良(、裏面は非鏡面にする方法を提供する
ものである。The present invention aims to solve both of these drawbacks, and provides a method for achieving good flatness (and a non-mirror surface on the back surface).
(課題を解決するための手段)
本発明は前述の課題を解決するために、ウェハを両面ポ
リッシング法で平坦度の良い鏡面ウェハとした後、裏面
のみ平坦度を劣化させることなくエツチングガス雰囲気
(HF系ガス)中で非鏡面にするようにしたものである
。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a mirror-finished wafer with good flatness by polishing both sides of the wafer, and then etching it in an etching gas atmosphere ( It is made to have a non-mirror surface in HF-based gas).
(作用)
本発明は前述のように、ウェハを先ず両面ポリッシング
法で鏡面とした後、裏面のみを非鏡面にするようにした
ので、平坦度は極めて良く、かつ裏面については前述し
た鏡面であるが故の欠点を解消できる。(Function) As described above, in the present invention, the wafer is first polished to a mirror surface on both sides, and then only the back surface is made into a non-mirror surface, so the flatness is extremely good, and the back surface has the mirror surface as described above. The drawbacks caused by this can be resolved.
(実施例)
第1図に本発明の実施例の工程断面図を示し、以下にそ
の説明をする。(Example) FIG. 1 shows a process sectional view of an example of the present invention, and the explanation will be given below.
まず(a)図に示すように、従来の技術の項で説明した
公知の両面ラッピング−ポリッシング法により、平坦度
の良い両面鏡面ウェハlを作る。First, as shown in Figure (a), a double-sided mirror-finished wafer l with good flatness is fabricated by the well-known double-sided lapping and polishing method described in the prior art section.
次ぎに(b)図のように、表面2にエツチング保護膜4
を付ける。これは次ぎの工程でウェハlの裏面3を非鏡
面にするための薬品またはガスから表面2を保護するた
めである。本実施例では、非鏡面エツチングをするため
にHF系ガスを使用したのでホトリソグラフィ工程で用
いるレジストで保護膜4を形成した。無論この保護膜4
は非鏡面にする方法に合わせるものであり、前記レジス
トに限るものではない。Next, as shown in (b), an etching protective film 4 is applied to the surface 2.
Add. This is to protect the front surface 2 from chemicals or gas that will make the back surface 3 of the wafer l a non-mirror surface in the next step. In this embodiment, since HF gas was used for non-specular etching, the protective film 4 was formed with a resist used in a photolithography process. Of course this protective film 4
This is suitable for the method of making a non-mirror surface, and is not limited to the above-mentioned resist.
次いで(c)図に示すよう(二裏面3を非鏡面にするた
め、ウェハ1をエツチングガス雰囲気5中に晒す。本実
施例では、HFとN Haを数lOppm〜11000
pp含む空気中に晒した。この状態で1〜数10時間放
置すると、レジスト4で保護されていない部分即ち裏面
3を主としたシリコン面が通常「(もり」と呼ばれる非
鏡面に仕上がる。これは以下の反応による。Next, as shown in FIG.
exposed to air containing pp. If left in this state for one to several tens of hours, the silicon surface, mainly the part not protected by the resist 4, that is, the back surface 3, will be finished in a non-mirror surface, which is usually called "(mori)". This is due to the following reaction.
(1)HFとシリコン面の自然酸化膜(SiO21が反
応してH25iFa +Hz Oとなる。(1) HF reacts with the natural oxide film (SiO21) on the silicon surface to form H25iFa +Hz O.
(2)このH2SiF6とN H3が反応し、(NH4
)2SiF6となる。(2) This H2SiF6 and NH3 react, and (NH4
)2SiF6.
(3)(NH4)2 S iFeは完全結晶化するまで
H2Oを保持しているため、雰囲気中のHFが高濃度に
溶は込みSiO2をエツチングする。(3) (NH4)2SiFe retains H2O until it is completely crystallized, so HF in the atmosphere penetrates into the SiO2 at a high concentration and etches the SiO2.
(4)SiO2をエツチングする過程で微小なエッチビ
ットが発生し、このため面が非鏡面状態6になる。(4) In the process of etching SiO2, minute etch bits are generated, resulting in a non-mirror surface state 6.
本反応により非鏡面6を得るには自然酸化膜で良いが、
予め50人〜100人の5in2を成長させておくとよ
り効果的である。A natural oxide film may be used to obtain a non-specular surface 6 through this reaction, but
It is more effective to grow 5in2 of 50 to 100 people in advance.
最後に、ウェハlを前記雰囲気から取り呂し、洗浄およ
び保護膜4の除去を行なうと(d)図に示すように、表
面2が鏡面で裏面3が非鏡面6であるウェハ1が得られ
る。Finally, the wafer 1 is removed from the atmosphere, cleaned, and the protective film 4 is removed. As shown in FIG. .
本実施例では、裏面を非鏡面とするためにガス雰囲気を
用いたが、公知の方法であるレーザスキャンや粒子吹き
付は法を用いても良く1本実施例の方法に限るものでは
ない。In this example, a gas atmosphere was used to make the back surface a non-mirror surface, but the method is not limited to the one used in this example, and any known method such as laser scanning or particle spraying may be used.
(発明の効果)
以上説明したように、本発明によれば両面ポリッシング
法で極めて平坦度の良い面を有するウェハを提供できる
とともに、裏面を非鏡面にしたために後の工程における
歩留まり低下の要因(従来技術の項で述べた両面ポリッ
シング法における問題点)を解消できる。(Effects of the Invention) As explained above, according to the present invention, it is possible to provide a wafer having an extremely flat surface using a double-sided polishing method, and since the back surface is made non-mirrored, it is possible to reduce the yield in subsequent steps. The problems with the double-sided polishing method described in the prior art section can be solved.
従って、今後発展していくサブミクロン超LSI製造の
歩留まり向上に寄与すること大である。Therefore, it will greatly contribute to improving the yield of submicron VLSI manufacturing, which will develop in the future.
第1図は本発明の実施例の工程断面図、第2図はラッピ
ング装置の構成図、第3図はポリッシングウェハのTT
V測定例である。
l・・・−・・・・ウェハ、 2−・・・・・・・
表面、3・・・・・・・・裏面、 4・・・・・
・・・保護膜、5・・・・・・・・エツチングガス雰囲
気、6・・・・・・・・裏面(非鏡面)。
第1図
圧
万
○
(0)フナ面うゾ〔′ンク゛
(b)
両面同所ラッピシグ′Fig. 1 is a process cross-sectional view of an embodiment of the present invention, Fig. 2 is a configuration diagram of a lapping device, and Fig. 3 is a TT of a polished wafer.
This is an example of V measurement. l...-...Wafer, 2-......
Front side, 3... Back side, 4...
...Protective film, 5... Etching gas atmosphere, 6... Back surface (non-mirror surface). Figure 1 Pressure Man○ (0) Crucian carp face Uzo〔'unk゛(b) Both sides same place rappisig'
Claims (3)
坦度の良い鏡面とした後、裏面を非鏡面とすることを特
徴とする半導体ウェハの製造方法。(1) A method for manufacturing a semiconductor wafer, which comprises polishing both the front and back sides of the semiconductor wafer to make it a mirror surface with good flatness, and then making the back surface a non-mirror surface.
るガス雰囲気中に晒しておくことを特徴とする請求項1
記載の半導体ウェハの製造方法。(2) Claim 1 characterized in that the means for making the mirror surface non-mirror includes exposing it to a gas atmosphere in which the mirror surface is etched.
A method of manufacturing the semiconductor wafer described above.
いることを特徴とする請求項2記載の半導体ウェハの製
造方法。(3) The method for manufacturing a semiconductor wafer according to claim 2, wherein a mixed gas of HF and NH_3 is used as the gas atmosphere.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24380090A JPH04124823A (en) | 1990-09-17 | 1990-09-17 | Manufacture of semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24380090A JPH04124823A (en) | 1990-09-17 | 1990-09-17 | Manufacture of semiconductor wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04124823A true JPH04124823A (en) | 1992-04-24 |
Family
ID=17109133
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24380090A Pending JPH04124823A (en) | 1990-09-17 | 1990-09-17 | Manufacture of semiconductor wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04124823A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0588055A2 (en) * | 1992-09-18 | 1994-03-23 | Mitsubishi Materials Corporation | Method for manufacturing wafer |
US5800725A (en) * | 1996-01-31 | 1998-09-01 | Shin-Etsu Handotai Co., Ltd. | Method of manufacturing semiconductor wafers |
-
1990
- 1990-09-17 JP JP24380090A patent/JPH04124823A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0588055A2 (en) * | 1992-09-18 | 1994-03-23 | Mitsubishi Materials Corporation | Method for manufacturing wafer |
EP0588055A3 (en) * | 1992-09-18 | 1994-08-10 | Mitsubishi Materials Corp | Method for manufacturing wafer |
US5429711A (en) * | 1992-09-18 | 1995-07-04 | Mitsubishi Materials Corporation | Method for manufacturing wafer |
US5800725A (en) * | 1996-01-31 | 1998-09-01 | Shin-Etsu Handotai Co., Ltd. | Method of manufacturing semiconductor wafers |
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