JPH04123624A - Frame synchronization detecting circuit - Google Patents

Abstract

PURPOSE:To suppress the issue of a counter station alarm even if a counter station alarm bit is detected erroneously by setting an error detecting circuit to a state that an error is present thereon when frame synchronizing step-out occurs. CONSTITUTION:When a code error by a transmission line 1 rises and a frame detecting circuit 2 is in the frame synchronizing step-out, an error detecting circuit 3 is set to a state that an error is present thereon by the output signal '1' of a frame detecting circuit 2, and outputs a signal '0'. An AND circuit 6a takes the AND gate of an output of the frame pattern detecting circuit 2 and the output of the error detecting circuit 3, and an AND circuit 6b takes the AND gate of an output of the AND circuit 6a and the output of a counter station alarm detecting circuit 4. Subsequently, the outputs of the frame pattern detecting circuit 2, the AND circuit 6a and the AND circuit 6b are generated as the alarm signals of this frame synchronization detecting circuit in this receiving terminal station.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a frame synchronization detection circuit of a receiving terminal station in digital transmission, and in particular to setting the status of various alarms issued when a code error occurs in a signal on a transmission path. This invention relates to an improved frame synchronization detection circuit.

[Conventional technology]

A frame synchronization detection circuit in a conventional digital transmission receiving terminal station is, for example, a frame pattern detection circuit that detects a frame pattern from a unipolar signal in which a signal sent from an AMI transmission path is decoded by an AMI encoder/coder. , code errors in the signal caused by the transmission path can also be AM
an error detection circuit that detects error pits notified from the AMI decoder according to the I code coding rule;
It has a match alarm detection circuit that detects a match alarm signal included in a frame pattern sent from an opposing station. The frame pattern detection circuit issues an out-of-synchronization alarm, the error detection circuit issues a transmission line error detection alarm, and the game alarm detection circuit issues a game game alarm, which are used as warning outputs.

This conventional frame synchronization detection circuit clears (resets) the error detection circuit that detects code errors caused by the transmission path when the synchronization detection circuit detects frame synchronization loss.
By doing so, the issuance of transmission line error detection alarms was suppressed. Therefore, when the number of code errors increases and the frame synchronization detection circuit repeats two states, an out-of-synchronization state and a synchronization state, the game alarm may become erroneous before the error detection circuit issues an alarm, and in this case, the game alarm is issued. The state will be as follows.

[Problem to be solved by the invention]

In a conventional frame synchronization detection circuit, when a frame synchronization state occurs due to a large number of code errors in a signal on a transmission path, the error detection circuit is reset. Therefore, before issuing a new code error alarm due to the transmission path,
There has been a problem in that the game warning signal may be erroneously detected. If the transmission line interface is currently in the working/standby configuration, and the priority for switching from the working interface to the standby interface is the synchronization frame is out of order, then the game alarm, then the above error detection circuit is reset. However, even if there is no frame synchronization loss, a game warning is erroneously issued and the current interface is switched to the standby interface.

[Means to solve the problem]

The frame synchronization detection circuit of the present invention includes a frame pattern detection circuit that detects a frame pattern of a digital signal input from a transmission path, and a frame pattern detection circuit that detects a code error in the digital signal and detects an error when this error exceeds a predetermined value. Frame synchronization has occurred in a frame synchronization detection circuit that has an error detection circuit that issues an alarm and a game alarm detection circuit that detects a game alarm signal indicating a transmission path abnormality in the opposing transmission device and issues a game alarm. a frame pattern detection circuit that keeps the error detection circuit in a state where the error alarm is issued; and game alarm generation prohibiting means that prohibits the generation of the game alarm as an alarm output when the error alarm is generated. ing.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The transmission path l contains a frame format signal according to the transmission path,
In this example, an AMI signal is flowing. AMI code encoder encoder 5 converts the AMI signal into a unipolar signal. If there is a code error in the signal, the code error is detected according to the code rules of the AMI code, and a code error signal is output to the error detection circuit 3.

The frame pattern detection circuit 2 detects a frame pattern from the unipolar signal output from the AMI code encoder 5 and establishes frame synchronization. The error detection circuit 3 is an AM
The I-code encoder 5 counts the output code error signals and detects error bits caused by the transmission line 1. The match alarm detection circuit 4 is a circuit that detects a match alarm signal included in the frame pulse.

Here, FIG. 2 is a diagram showing an example of a frame format of a signal flowing through the transmission path 1. In FIG. This digital signal is an example in which the -order group is 1.544 Mb/s, one frame has a 24 channel (TS) configuration, and one multiframe configuration is made up of 12 frames. The frame synchronization bit (F) at the beginning of the 1st to 12th frames contains “10001”.
101110'' code is included.The last (12th) signal of the frame synchronization bit is a signal (SEND) for alerting the opposing station and indicates that there is an abnormality in the transmission path in the transmission equipment of the opposing station. If there is an alarm indicating
is specified.

Returning to the explanation of FIG. 1 again. One of the five outputs of the AMI code encoder is sent out as a main signal line to a code decoding circuit or the like in the receiving terminal station. The frame pattern detection circuit 2 detects the aforementioned "10001101110" pattern and establishes frame synchronization. When the frame is out of synchronization, a signal "1" is output as a frame synchronization alarm, and when the frame is in synchronization, a signal "0" is output. Error detection circuit 3
counts code error signals, and outputs a signal "0" as an error alarm when the error exceeds a predetermined constant value. In addition, the error detection circuit 3 detects that the frame detection circuit 2 is out of frame synchronization due to an increase in code errors on the transmission path 1, and the above-mentioned output signal "1" of the frame detection circuit 2.
”, the error state is set and the signal “0” is output at this time as well.This setting method includes a method such as using an error counter as the error detection circuit 3 and setting the counter to a count-up state. The match alarm detection circuit 4 detects the match alarm signal (SEND) of the 12th frame of the frame synchronization signal and outputs a match alarm.

The AND circuit 6a takes an AND gate of the output of the frame pattern detection circuit 2 and the output of the error detection circuit 3, and
The D circuit 6b takes an AND gate of the output of the AND circuit 6a and the output of the game alarm detection circuit 4. Then, the frame pattern detection circuit 2°AND circuit 6a and the AND circuit 6
The output of b is issued as an alarm (monitoring) signal of the frame synchronization detection circuit in this receiving terminal station. According to this configuration, if a frame synchronization loss alarm is issued, an error alarm is issued and a game alarm is not issued. Further, even if frame synchronization is achieved, if an error alarm is issued, a game alarm will not be issued. In this way, the priority order of the alarms to be issued is determined by the AND circuits 6a and 6b, and is in the following order: frame synchronization loss, increase in code errors due to the transmission path, and game alarm detection.

〔Effect of the invention〕

As explained above, in the present invention, even when the number of code errors in the transmission path increases and the two states of frame synchronization state and frame synchronization state are repeated, if frame synchronization occurs - degree, the error detection circuit Set to error status. Therefore, even if the game warning bit is erroneously detected in this state, it is possible to suppress the game game warning from being issued.

Furthermore, when the transmission line interface has a working/standby configuration, by using the frame synchronization detection circuit of the present invention, switching of the interface will not occur only due to an alarm (error alarm) of an increase in code errors caused by the transmission line. There is an effect that there is no.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a transmission line signal frame format. 1... Transmission line, 2... Frame pattern detection circuit,
3...Error detection circuit, 4...Game alarm detection circuit,
5...AMI code encoder encoder at 6b...AND
circuit.

Claims (1)

[Claims] 1. A frame pattern detection circuit that detects a frame pattern of a digital signal input from a transmission path, and an error alarm that detects a code error in the digital signal and generates an error alarm when the error exceeds a predetermined value. When frame synchronization occurs in a frame synchronization detection circuit that has an error detection circuit that issues an error, and a game alarm detection circuit that detects a game alarm signal indicating a transmission line abnormality in the opposing transmission device and issues a game alarm. A frame pattern detection circuit that keeps the error detection circuit in a state in which the error alarm is issued, and a game alarm generation prohibiting means that prohibits the generation of the game alarm as an alarm output when the error alarm is in the generation state. A frame synchronization detection circuit featuring: 2. A frame pattern detection circuit that detects a frame pattern of a digital signal input from a transmission path, and an error detection circuit that detects a code error in the digital signal and issues an error alarm when the error exceeds a predetermined value. , a frame synchronization detection circuit having a game alarm detection circuit that detects a game alarm signal indicating a transmission path abnormality in an opposing transmission device and issues a game alarm, wherein the frame synchronization detection circuit issues a frame synchronization loss alarm; The apparatus is characterized by comprising means for issuing the error alarm as an alarm output at certain times and preventing the game alarm from being issued as an alarm output when the error alarm is issued, and means for preventing the game alarm from being issued as the alarm output when the error alarm is issued. Frame synchronization detection circuit.