JPH04123253A - Configuration detecting system for super parallel computer - Google Patents

Abstract

PURPOSE:To improve the flexibility and reliability of application by arranging a monitoring means for monitoring the transmission of a prescribed rack ID from each rack in a controller and deciding a connection form between the controller and the rack based upon the existence of the transmission. CONSTITUTION:Respective rack ID transmitting means 21a to 23a ... arranged in respective racks 21 to 23 ... send prescribed rack IDs to the controller 11 through respective signal cables 31 to 33 ... and the rack ID monitoring means 51 in the controller 11 monitors whether the prescribed rack IDs are sent from respective racks or not. When the rack ID is sent, the existence of the pre scribed rack in a prescribed position is decided, and when the rack ID is not sent, absence of the rack in the prescribed position is decided. Consequently, the existence of each rack, its position and the connection from between the rack and the controller 11 can be automatically detected, the constitutional form or a constitutional miss can be automatically and surely inspected or recognized from the application side and the flexibility and reliability of the application can be improved.

Description

[Detailed Description of the Invention] [Table of Contents Overview Industrial Application Fields Prior Art Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Effects (Fig. 1) Example (a) Overall configuration of parallel computer (Figure 2) (b) Configuration of rack ID monitoring means and rack ID transmission means (Figure 3) (c) Operation of rack ID monitoring means (d) Board monitoring means and board ID transmission Configuration of means (Figs. 4 to 6) (e) Operation of board ID transmitting means (Fig. 7) (f) Inter-rack connection detection processing (Figs. 8 and 9) (g) According to the present invention Other Examples Effects of the Invention [Summary] Detecting the connection form of the controller and rack that constitute the massively parallel computer, the type and position of the processor board stored in the rack (rack configuration), and the cable connection status between the racks. Regarding the configuration detection method of a massively parallel computer that determines the configuration of a massively parallel computer, the configuration and configuration errors can be automatically and reliably checked from the application side (controller side) without limiting the configuration of the massively parallel computer. , vl, the purpose of this is to provide a method for detecting the configuration of a massively parallel computer that can identify the configuration of a massively parallel computer and improve the flexibility and reliability of applications.
Rack ID sending means is provided on each rack side, monitoring means is provided on the controller side to monitor whether a predetermined rack ID is sent from each rack, and based on whether or not a predetermined rack ID is sent, The controller is configured to determine the connection type between the controller and the rack.

[Industrial Application Field] The present invention relates to a method for detecting the configuration of a massively parallel computer, and in particular the connection configuration of a controller and a rack that make up a massively parallel computer, the type and position of a processor board housed in a rack (the configuration of a rack), etc. ), relates to a configuration detection method for a massively parallel computer that determines the configuration of the massively parallel computer by detecting the cable connection state between racks.

Computers are closely connected to our lives, and the amount of processing that computers do will continue to increase in the future, and the processing content will become more complex, but there is a limit to the processing power that a single computer can handle. Therefore, by parallel processing using multiple computers,
Research and development of methods to increase processing power are actively being conducted.

Modern massively parallel computers consist of thousands to tens of thousands of processors. Although the degree of integration of processors has increased due to advances in VLSI technology, massively parallel computers have
More than 10 racks containing several printed boards (processor boards) are required. Furthermore, these processor boards and racks must be connected to each other with cables for adjacent communication, etc., and it is also necessary to connect the racks and controllers with cables, which increases the number of cables required to configure a massively parallel computer. The number can reach up to several dozen.

When trying to actually configure a massively parallel computer using these components, such as racks, processor boards, and cables, there are problems such as inserting the processor board in the wrong place, inserting the processor board insufficiently, connecting the cables in the wrong place, or connecting the cables incorrectly. Mistakes such as insufficiency may occur, and it may not be possible to configure a massively parallel computer as designed.

Therefore, there is a need for a detection method for easily determining the configuration of a massively parallel computer and the connection state of cables.

[Prior art] However, in the past, it was not possible to automatically recognize the configuration of a massively parallel computer, and the presence or absence and position of racks, the type and insertion position of processor boards in racks, and the cables between racks were determined visually and using a tester. Understand the connection type and the connection type between the rack and controller, and check whether the rack and processor board are placed in the correct position, and whether there are any cable connection errors.

We are investigating whether there are any insufficient cable connections.

Also, recently, a method has been proposed for automatically recognizing the configuration form of a massively parallel computer. This method is.

Possible combinations of racks, processor boards, and adjacent communications that are the components of a massively parallel computer are fixed, a configuration table is prepared based on those combinations, and the massively parallel computer is configured according to the configuration table. do. Then, the application reads parameters indicating the configuration state based on the configuration table and executes a program that recognizes the configuration of the massively parallel computer.

[Problems to be Solved by the Invention] In the former method, it takes a long time to discover a configuration error when it occurs, and the configuration of the massively parallel computer cannot be easily and reliably grasped.

Furthermore, in the latter method, the combination of configurations of the massively parallel computers is fixed, so there is a problem that application flexibility is lost.

From the above, it is an object of the present invention to enable the application side (controller side) to automatically and reliably inspect and recognize configuration forms and configuration errors without limiting the configuration of a massively parallel computer, thereby increasing flexibility and reliability of the application. An object of the present invention is to provide a configuration detection method for a massively parallel computer that can improve performance.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

11 is a controller that controls the entire massively parallel computer; 2
1.22, 23... are racks that house processor boards, 31.32.33... are signal cables that connect the controller and each rack, 41.42.43...
This is a signal cable for adjacent communication that connects predetermined racks.

In each rack, 21a, 22a, 23a, . . . are rack ID transmitting means for sending a predetermined rack ID to the controller via signal cables 31, 32, 33, .
, 22b, 23b... are processor board groups,
Processor boards include real processor boards on which many processors are mounted, and pass-through boards for passing signals. 21c, 22c, 23c... are processor interface boards 21d that perform the role of an interface between the controller and each processor, and control the operation of the processor based on instructions from the controller.
, 22d, 23d, . . . are signal cables connecting the boards.

51 is each rack ID transmitting means 21a, 22a.

This rack ID monitoring means monitors whether a predetermined rack ID is sent from 23a, . . . .

[Function] Rack ID provided on each rack 21, 22, 23... side
The transmitting means 21a, 22a, 23a... send a predetermined rack ID (for example, "0") to the controller 11 via the signal cables 31, 32, 33... Monitor whether the specified rack ID is sent from the rack, and check whether the specified rack ID is sent from the rack.
0") is sent, it is determined that a rack exists at a predetermined position, and when a rack ID is not sent, it is determined that a rack does not exist at a predetermined position.This allows the presence or absence of a rack to be determined. , its position, and the connection form between the rack and controller can be automatically detected.

Further, a board ID transmitting means is provided in the processor board group 21b of each rack (for example, the rack 21), and each board ID
Sending a predetermined board ID from the transmitting means to the processor interface board 21c via the signal cable 21d,
The interface processor board monitors whether the first board ID (in the case of a real processor board) or the second board ID (in the case of a passing board) is sent from each boat, and determines whether the first and second board IDs are sent. Based on whether or not the board is present, the presence or absence of the board and the type and position of the processor board are determined and notified to the controller 11. This allows the type of processor board and its insertion position to be automatically detected.

Furthermore, the controller 11 operates as a processor interface board to transmit predetermined signals from the processor boards constituting each column to adjacent communication cables for each of the top row, bottom row, leftmost row, and leftmost row of the rack 21. 41.
42..., detects the processor board that receives the signal, and determines the cable connection form between the rack 21 and other racks, thereby automatically determining the connection status between each rack. Can be detected.

[Embodiment 1 (a) General J Calculation Figure 2 is a block diagram of an embodiment of a massively parallel computer according to the present invention.

Reference numeral 11 denotes a controller that controls the entire massively parallel computer, including a management processor (CPU) 11 al, a memory l
Rack ID monitoring means 51 is comprised of part of the functions of the processor lla, the memory 11b, and the rack ID importing section 11c.

The rack ID monitoring means 51 monitors the presence or absence of a rack and its position by checking whether or not a rack ID is sent from each rack. 21.22, . . . are racks that house processor boards, 31.32, . . . are signal cables that connect the controller and each rack, 41.42.4
3...A signal cable for adjacent communication that connects predetermined racks.

In the rack 21, 21a is rack ID transmitting means;
1b is a processor board group, 21c is a processor interface board, and 21d is a signal cable connecting the processor interface board and the processor board.

The rack ID sending means 21a sends low-level 1-bit data (referred to as rack ID) to the rack ID monitoring means 51 of the controller 11 via the signal cable 31.

The processor board group 21b includes a plurality of processor boards 2.
1b-1, 21b-2, . . . 21-n.

The processor boards include a real processor board (on which a large number of processors are mounted) and a pass board for passing signals, and each processor board 21b-1, 21b-2
1b-2, . . . 21-n includes board ID transmitting means 21
e-1, 21e-2, . . . 21e-n are provided.

These board ID transmitting means send a 2-bit boat ID to the board ID monitoring means (described later) of the interface processor board 21c via signal cables 21cl-1, 21cl-2, . . . 21d-n. .

The processor interface board 21c connects each processor board 21b based on instructions from the controller 11.
-1, 21b-2, . . . 21b-n, an interface processor 21cm1. It has a memory 21cm2 and a board ID importing section 21c-3 that imports board IDs sent from each processor board. Then, the board ID monitoring means 61 is implemented by a part of the functions of the interface processor 21cm1, the memory 21-2, and the board ID importing section 21cm3.
is configured. This board ID monitoring means 61 is used for each processor board 21b-1, 21b-2, . . . 21b-n.
Monitor whether the first board ID (in the case of a real processor board) or the second board ID (in the case of a passing board) is being sent from the board, and check whether the first and second board IDs are being sent. Based on the presence or absence of a processor board,
The type of processor board and its position are determined and notified to the controller 11.

The other racks 22, 23, . . . have the same configuration as the rack 21, and differ in the number and type of processor boards.

FIG. 3 is a configuration diagram of a rack ID monitoring means for monitoring the presence or absence of racks constituting a massively parallel computer, their positions, and the connection form between the controller and the racks, and a transmission means from the racks.

The controller 11 and each rack 21, 22... are connected by signal cables 31, 32..., and each signal cable 31
．． 32... are 3 between the controller 11 and the rack, respectively.
1 included in the signal cable.
Book lines 31a, 32a.

. . via the rack ID transmitting means 21a, 22a.

...lower level 1-bit data (rack ■D) is now sent.

The rack ID capturing section 11c of the rack ID monitoring means 51
Each rack has a selector SL and a resistor R5, one end of each resistor is connected to a power line of voltage Vcc, and the other end is a signal line 31 a +' for transmitting the rack ID.
32 a... are connected.

The rack ID is input to one input terminal of each selector SL, one bit of communication data is input to the other input terminal, and the output terminal is the first I10 terminal (i
=1.2. ...) is entered. Furthermore, a memory control block lla' (a part of the function of the processor lla) is connected to the selector terminal of each selector SL, and the rack ID and communication data are appropriately selected under the control of the memory control block. . Note that the memory control block 11a' is the memory llb.
It has a function of storing the rack ID and its low communication data, and reading and outputting desired data from the memory Ilb.

(c) When the power is turned on to the rack ID supervisor's massively parallel computer, the configuration detection processing routine of the massively parallel computer is activated as necessary.

This causes the memory control 118' to.

Generate address FFFF, (H means hexadecimal number) and select rack from all selectors SL,
Each rank ID transmitting means 21a, 22a is placed at the address position.
Write the rack ID sent from , etc., if the rack does not exist or if the cable connection is bad.

The rack ID will be high level (“1”), and will be low level (“1”) if the rack exists and the cable connection is good.
"0").

After that, read the contents of address F F F F,
It is determined that a rack exists at a location corresponding to the bit position of "jlo#", and a rack does not exist at a location corresponding to a bit position of "1", or there is a poor connection.

As described above, the presence or absence of a rack and its position can be automatically detected.

(d) Board ID monitoring means and board ID transmitting means Figure 4 is a configuration diagram of the boat ID monitoring means and board ID transmitting means that monitor the presence or absence of a processor board in a rack and its position (rack configuration). .

A signal cable 2 is connected between the processor interface board 21c and each processor board 21b-1, 21b-2...
1d-1, 21d-2, etc., and the board ID transmitting means 21e is connected via two wires included in each signal cable.
-1, 21e-2... 2-bit board ID [B
DO, BDI] is transmitted. When the processor board is a real processor board, as shown in FIG. 5(a), the board ID transmitting means 21e-1, 21e-2, etc.
= high level ("1"), BD1 = low level ("0") 2-bit first board ID [1,01 is sent, and if the processor board is a passing board, as shown in Figure 5 (b) Then, send the 2-bit second board ID [0, 1] with BDO=low level (“O”) and BD1=high level (“1”).

Board ID capturing section 21cm3 of board ID monitoring means 61
are selectors SL1 and SL2 for each rack, respectively.
Nantes Gate NG1. With NG2.

Inverter (knot gate) Nl, N2 and resistor R3I
, R82, one end of each resistor R8I and R52 is connected to a power supply line of voltage Vcc, and the other end of resistor R8I is connected to a signal line for transmitting the first bit data BDO of the board ID. A signal line for transmitting second bit data BDI of the board ID is connected to the end.

The first input terminal of each selector SLI has a Nant gate N
The output RB of the GI is inputted, and the output TB of the NAND game (NG2) is inputted to the second input terminal.

The output of each Nant gate NGI, NG2 [RB.

TB] is [0, 1] when the real processor board is connected, and becomes [1, 0] when the pass-through board is connected, as shown in Figure 6. If there is no connection, it will be [1, 1], and if some abnormal connection has occurred, it will be [0, O].

The output signal of the selector SL1 is input to one input terminal of each selector SL2, one bit of communication data is input to the other input terminal, and the output terminal is the memo +J 1 l b
(7) i-th I/O terminal (i=1.2. . .)
has been entered. In addition, a memory control block 21cm is connected to the selector terminal of each selector SLI and SL2.
1' (partial function of interface processor 21cm1) is connected, and selector SLI is set to NAND NG as appropriate.
I, NG2 output signal RB.

Selector SL2 selectively outputs one side of TB, and selector SL2 outputs signal R.
B, TB, or communication data is selectively output.

(e) Board ID Supervisor When the power is turned on to the massively parallel computer 61, the configuration detection processing routine of the massively parallel computer starts, and the interface processor of each rack 21, 2-2, etc. Rack configuration detection is instructed.

According to the rack configuration detection instruction, the memory control 21c
m1' generates the address F F F F, and causes selectors SLI and SL2 to select the output signal RB of NAND NGI. As a result, each rack ID transmitting means 21a, 22a is placed at the address location of the memory 21c-2.
A signal RB corresponding to the board ID sent from , . . . is written. Note that when a real processor board is connected, RB="0", and when a passing board is connected or nothing is connected, RB="1" (see Figure 6). reference).

Then, the memory control 21cm1' generates the address FFFEM and selectors SLI and SL2.
to select the output signal TB of NAND NG2. As a result, each rack I
D transmission means 21a.

A signal TB corresponding to the board ID sent from 22a, . . . is written. Note that when the pass-through board is connected, TB="O", and when the real processor board is connected or nothing is connected, RB="1" (Figure 6). reference).

Next, the contents of addresses FFFF□ and FFFE are read out, exclusive OR operation is performed on the corresponding bits, and if there is a bit of HVT, a processor board is inserted in the position corresponding to the bit position, and the bit of 110'1 is inserted. It is determined that the processor board is not inserted at the location according to the position. Further, when a processor board is inserted, if the first bit RB is "0", it is determined that the actual processor is inserted, and if the second bit TB is "0", it is determined that the passing board is inserted.

Thereafter, the rack configuration detection process is completed by notifying the controller 11 of the rack configuration (the type of processor board and the insertion position) as a result of the first determination.

FIG. 7 is an explanatory diagram of the correspondence between the processor board positions of a rack into which a total of 16 processor boards can be inserted in a 4×4 grid pattern and the memory bit positions. Each boat insertion position Pij (iyj=1 to 4) and the address FFF FIl in the memory 21c-2.

There is a correspondence between the bit positions of FFFEH. For example, the first bit of address FFFFFH and address FFFE corresponds to board insertion position 1iP11, and the second bit of address FFFF and address FFFE corresponds to board insertion position 1iP11. [corresponds to PI3, and there is a similar correspondence below.

Therefore, the first bit of address FFFFH is "0".
", if the first bit of address FFFEM is "1", it can be determined that the actual processor board is inserted at board insertion position P11, and if the second bit of address FFFEM is "1", then the address If the second bit of FFFE is “0”, the board is inserted! It can be determined that the passage board is inserted at P12, and the board insertion position and the type of board inserted, or whether no board is inserted, can be determined in the same manner.

(f) Rack source ring As shown in Figure 8, in a massively parallel computer, processor boards BO-B15 are arranged in a grid in each rack R1,
The processor boards constituting the top row, bottom row, rightmost row, and leftmost row of 2, R3, R4, etc. are connected to the top row, bottom row, and bottom row of other racks for adjacent communication. It is connected by a signal cable to the processor boards that make up the rightmost and leftmost columns. This inter-rack connection form is also necessary to understand the configuration of a massively parallel computer.

Therefore, once the process of detecting the type and insertion position of the processor board in each rack (rack configuration detection process) is completed, the controller 11 performs the process of detecting the cable connection form between the racks according to the flowchart shown in FIG. .

First, from the processor board position of the i-th rack (the initial value of i is 1) obtained by the rack configuration detection process, the processor boards (B3, B7,
．． Bll, B15), and simultaneously sends a predetermined signal (for example, 101) from each processor to the right side via the adjacent communication cable (step 101), and the processor board that received the signal stores it in the built-in memory. (step 102).

After that, the controller 11 checks whether the above signal has been written to each processor board in the leftmost row of each rack (steps 103 and 104), and if the above signal has not been written to the leftmost processor board in any rack, It is determined that the rightmost processor group of the i-th rack is not connected to other racks or that there has been a cable connection error (step 105).

On the other hand, 1. If the above signals are written to all the leftmost processor boards of a predetermined rack, for example, the j-th rack, the rightmost processor board of the i-th rack is the leftmost processor board of the j-th rack. (step 106). In this case, if the above signals are written to only some of the leftmost processor boards, there may be a cable connection error, etc. It is determined that there is a malfunction.

Thereafter, the processor boards in the leftmost row, topmost row, and bottommost row of the i-th rack are determined, and the steps 10 above are performed for each row.
The processes from 1 to 106 are repeated to determine the cable connection form between the i-th rack and other racks (step 107).

In addition, in the case of the leftmost column, the topmost column, and the bottommost column, it is determined whether a transmission signal is written to the processor board of the rightmost column, the bottommost column, and the topmost column, respectively.

Next, check if the above process has been completed for all racks (Step 108), and if it has not been completed, increment i (Step 109), and perform Step 1 for the new rack.
The processing from 01 onward is repeated, and when the processing is completed for all racks, the inter-rack connection configuration detection processing is completed.

(g) The above describes the cable connection configuration between the rack and controller,
When detecting the cable connection form between each rack, the configuration of each rack, etc., for example, if the designed or desired connection form between racks and controls is registered in advance, the detected actual connection form can be detected. By comparing the results with the above, it is possible to automatically detect incorrect rack positions, signal cable connection problems, etc. Similarly, if you register the designed or desired rack configuration (processor board type and insertion position) in each rack in advance, you can avoid mistakes in board insertion by comparing it with the detected actual rack configuration. It is possible to automatically detect incorrect board types, signal cable connection problems, etc.Furthermore, if the designed or desired inter-rack connection configuration is registered in advance,
By comparing with the detected actual connection configuration between racks, connection defects and connection errors in cables between racks can be automatically detected. Various modifications can be made in accordance with the gist of the invention as described, and the invention does not exclude these.

[Effects of the Invention] According to the present invention, each rack is configured to transmit a rack ID, and each processor board in the rack is configured to transmit a board ID. Depending on whether or not the ID has been received, the presence/absence and position of the rack, as well as the type and position of the processor boards constituting the rack, can be automatically detected.

Also, predetermined signals are sent from the processors in the rightmost row, the leftmost row, the topmost row, and the bottommost row, and the processors in the rightmost row, the leftmost row, the topmost row, and the bottommost row of the racks correspond to the processors in the rightmost row, leftmost row, topmost row, and bottommost row. Since the system is configured to identify the cable connection form between racks depending on whether a signal is received, the cable connection form between all racks can be automatically detected in a short time.

Furthermore, by registering the cable connection form between the rack and controller, the connection form between each rack, and the configuration of each rack in advance, and configuring it to compare with the detection results,
Insertion errors, forgotten insertions, cable connection problems, connection errors, etc. can be automatically detected.

In other words, according to the present invention, without limiting the configuration of a massively parallel computer, the configuration form and configuration errors can be automatically and reliably checked and recognized from the application side (controller side), thereby increasing the flexibility and reliability of the application. can improve sexual performance.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, and Fig. 2 is a configuration diagram of a massively parallel computer. FIG. 3 is a block diagram of rack ID monitoring means and rack ID transmitting means, FIG. 4 is a block diagram of board ID monitoring means and board ID transmitting means, and FIG. 5 is an explanatory diagram of board ID transmitting means. Figure 6 is a diagram explaining the board ID of the processor board. Figure 7 is a diagram explaining the correspondence between processor board positions and memory bits. Figure 8 is a diagram explaining the connection type between racks. Figure 9 is a flowchart of the process of determining the connection type between racks. be. 11...Controller 21.22.23...Rack 31.32.33...Signal cable 41.42.43...Signal cable for adjacent communication 21a,
22a, 23a...Rack ID transmitting means 21b, 22b
, 23b... Processor board group 21c, 22c, 23
c...Processor interface boards 21d, 22d, 23d...Signal cable 51...Rack ID monitoring means 61...Board ID monitoring means (a) (b) Explanatory diagram of actual processor board passing JD transmission means FIG. 5 Processor Figure 6: Explanation diagram of the board ID of the board Figure 6: Explanation of the correspondence between the processor board position and memory bit position Period 7 Figure: Diagram explaining the connection form between the board and the seat Figure 8

Claims (3)

[Claims] (1) Equipped with a controller that controls the overall operation and multiple racks that house a large number of processor boards, and a signal cable that connects the controller and each rack.
In a configuration detection method for a massively parallel computer in which predetermined racks are connected by a signal cable for adjacent communication, a predetermined rack ID is sent to the controller via the signal cable.
Rack ID sending means is provided on each rack side, and monitoring means is provided on the controller side to monitor whether a predetermined rack ID is sent from each rack. A configuration detection method for a massively parallel computer, characterized by determining the connection configuration between a controller and a rack. (2) A plurality of real processor boards on which a large number of processors are mounted and a processor interface board equipped with an interface processor that controls the operation of the processors are housed in a rack, and a passage is provided for passing signals as necessary. Several boards are stored in a rack, and the first one is connected to the interface processor via a signal cable.
A board ID transmitting means for transmitting the board ID is provided on the actual processor board side, and a second
A board ID transmitting means for transmitting the board ID of each board is provided on the passing processor board side, a monitoring means for monitoring whether the first or second board ID is sent from each board is provided on the interface processor side, 2. The configuration detection method for a massively parallel computer according to claim 1, wherein the type and position of the processor board stored in the rack are determined based on whether or not a board ID of the processor board has been sent. (3) From the determined processor board positions, determine the processor boards that make up each row for each of the top row, bottom row, rightmost row, and leftmost row of the rack, and configure the row for each row. Claim 2, wherein a predetermined signal is sent from a processor board connected to the rack via an adjacent communication cable, and the processor board that receives the signal is detected to determine a cable connection form between the rack and another rack. A configuration detection method for the massively parallel computer described.