JPH04122985A - Display driving circuit - Google Patents

Abstract

PURPOSE:To offer the display driving circuit which is adaptive to various LCDs and CRTs without varying a fundamental clock by adding a circuit which controls the period of a subordinate clock SCP in various modes to the display driving circuit. CONSTITUTION:The display driving circuit 200 constituted by adding a variable shift register to a display driving circuit drives both an LCD 201a and a CRT 202a. Thus, the display driving circuit 200 is adaptive to even a terminal equipped with an LCD interface 201b and a CRT interface 202b. The fundamen tal clock of the display driving circuit is varied to adapt the circuit to various LCDs, but the display driving circuit 200 to which the simple circuit controlling the period of the subclock SCP in various modes is added can generate the best interface signals for various LCDs without varying the frequency of the fundamental clock and can drive even the CRT.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a display drive circuit using a liquid crystal and a cathode ray tube as a display device.

(Prior Art) In recent years, large liquid crystal screens with binary display have been widely used as various display devices. These liquid crystal display devices (hereinafter referred to as LCD) have a display pixel count of 640 horizontal x 400 vertical pixels or 640 horizontal x 480 vertical pixels, and a frame frequency of 60 Hz or 7
In many cases it is 0Hz.

Although each of the above-mentioned LCDs requires a suitable drive circuit, from the viewpoint of productivity, it is desirable to be able to drive various LCDs with one drive circuit. This can be achieved by changing the frequency of the basic clock that operates the drive circuit.

On the other hand, in addition to LCDs, cathode ray tubes (C
(written as RT). However, data for LCD and CR
The data for T is basically a sampling clock. Another problem with CRTs is that correct signals cannot be supplied to the CRT unless the basic clock is fixed. Therefore, when attempting to provide drive circuits that are compatible with LCDs and CRTs, there are conflicting manufacturing requirements.

(Problem to be Solved by the Invention) As mentioned above, compatibility with various types of LCDs can be achieved by changing the basic clock of the display drive circuit.
In RT, the basic clock must be fixed.

Therefore, an object of the present invention is to provide a display drive circuit that can be used with various types of LCDs and CRTs without changing the basic clock of the display drive circuit.

[Structure of the Invention (Means for Solving the Problems) Shift register means is supplied with a basic clock, changes its cyclic period in accordance with various mode settings, and outputs as its output a sub-tallock corresponding to each mode; means for generating a clock signal for reading liquid crystal data from the output of the shift register; first and second address counter means for generating display addresses in the horizontal and vertical directions of the liquid crystal display according to the clock signal; The device is equipped with means for combining the outputs of two address counter means and supplying a read address for liquid crystal display data to the memory, and a register means for latching the data read from the memory according to the address.

(Function) According to the above means, on the one hand, since the basic clock does not need to be changed, it can be used as a clock for CRT at any time, and on the other hand, by changing the cycle period of the shift register, it can be used as a clock for various types of liquid crystal display devices. It can be used as

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

For example, (3215) fsc (fsc
: carrier color signal frequency) is input. This basic clock is input to the variable shift register circuit 41. The variable shift register 41 can change its cycle period by a mode switching signal. The serial subclock SCP output from the variable shift register circuit 41 is input to the display drive circuit 100.

The variable shift register circuit 41 is the essential circuit of the present invention, but first, the configuration and operation of the display drive circuit 100 will be explained.

A subclock SCP for operating the display drive circuit 100 is applied to the LX counter 21. This LX counter 21
is a circuit that generates addresses corresponding to pixels in the horizontal (X) direction of a liquid crystal display screen. Also, sub clock SC
P is sent to the display interface as a sampling signal for reading unit data of the liquid crystal display device.

The LX counter 21 is, for example, a hexadecimal counter. For example, if data for a liquid crystal display has a 4-bit configuration, 160 pixels (-640 pixels) are required to display 640 pixels.
This is because if an address of /4) is generated, 640 bits of data can be read.

The address output from the LX counter 21 is an 8-bit output (L X o =L X 7 ), and is supplied to the address synthesis circuit 27 and the LX decoder 22 as an address in the horizontal direction of the screen.

The LX decoder 22 generates a latch pulse signal LP for each line of the liquid crystal display screen and a reset pulse signal RLX for making the LX counter 21 a hexadecimal counter. The latch pulse signal LP is also applied to the LY counter 23.

The LY counter 23 is for generating an address in the vertical (Y) direction of the liquid crystal display screen. The LY counter 23 is constructed on a scale that generates half the address of the liquid crystal display screen in order to reduce its hardware.

The LY counter 23 indicates that the Y direction of the liquid crystal display screen is 400.
In the case of pixels, the counter is switched to operate as a 200-decimal counter, and in the case of 480 pixels, it is switched to operate as a 240-decimal counter. This switching is realized by the LY decoder 24.

That is, the 8-bit output of the LY counter 23 (L Y o
-L Y 7 ) is added to the LY decoder 24 and the adder circuit 26 . Further, LYo-LY7 is used as line address data in the upper half of the liquid crystal display screen by the address synthesis circuit 27.
It can also be added to The line address data in the lower half of the LCD screen is LY.

~LY7 is corrected by the adder 26 and then input to the address synthesis circuit 27.

The LY decoder 24 generates a frame pulse signal FP and a reset pulse signal RLY for the LY counter 23. This reset pulse signal RLY corresponds to 400 pixels or 480 pixels and is set so that the LY counter 23 becomes 200 base or 240 base under the control of the mode setting circuit 25.

The adder circuit 26 receives an offset signal for creating an address for the lower half of the screen under the control of the mode setting circuit 25 and the 8-bit output of the LY counter 23 (L Y o =
LY? ) is added. The value of this offset signal is also switched when the LY counter 23 operates as a 200 or 240 system.

The address synthesis circuit 27 synthesizes the count values from the LX counter 21, the LY counter 23 and the adder circuit 26, and
Generates a read address for CD data and creates a memory circuit 3
Output to 0.

The memory circuit 30 outputs data corresponding to the read address to the data latch circuit 28 and the data latch circuit 29.

The outputs of the data latch circuit 28 and the two data latch circuits are data to be displayed on the upper half of the LCD (U D
o = U D 3 ) and lower half data (L D
o = L D s ) as the other control signal (SCP
signal, LP signal, and FP double signal together with the LCD interface.

Below, basic clocks (ie, SCP signals) of various LCDs in the above circuit configuration will be shown.

Number of display pixels: 640 x 400 pixels.

Frame frequency: In the case of 60Hz, LP-60HzX200=12kHz.

5CP-LPX160-1.92MHz.

That is, the basic clock frequency is 1.92 MHz. Number of display pixels: 640 x 400 pixels. When the frame frequency is near 0 Hz, it is LP-70 Hz x 200-14 kHz.

5CP-LPX160-2.24MHz.

That is, the basic zero clock frequency is 2.24 MHz and the number of display pixels is 640 x 480 pixels.

Frame frequency: In the case of 60Hz, LP-60HzX240=14.4kHz.

5CP-LPx160-2.304MHz.

That is, the basic clock frequency is 2.304 MHz. Number of display pixels: 640 x 480 pixels.

Frame frequency: In the case of 70Hz, LP-70HzX240=16.8kHz.

5CP=LPX160=2.688MHz.

That is, the basic clock frequency is 2.688MHz.

By setting the basic clock as described above, it is possible to provide a display drive circuit compatible with various types of LCDs, but in order to make it compatible with CRTs, a variable shift register circuit 41 is connected in this embodiment.

That is, while the basic clock is fixed, the variable shift register circuit 41 can obtain a subclock SCP that can be applied to various liquid crystal display devices.

The basic principle of this system will be explained.

For example, when this system is used for a rank 3 terminal in a cab, the dot clock of the screen display data of this terminal is 3215 fsc (-22.9 MHz).

Hereinafter, when the basic clock is (3215)fsc, the subclocks SCP corresponding to various liquid crystal display devices are as follows.

Number of display pixels: 640 x 400 pixels.

When the frame frequency is 60Hz, the SCP is 3215f 5c12 clocks, and the FP multiplied signal is 59.7Hz.

Number of display pixels: 2640 x 400 pixels.

When the frame frequency is 70 Hz, the FP multiplied signal is 71.6 Hz for SCP: 3215 fsclO clocks.

Number of display pixels: 640 x 480 pixels.

When the frame frequency is 60 Hz, the FP multiplied signal is 59.7 Hz for SCP: 3215 fsclO clocks.

Number of display pixels: 640 x 480 pixels.

Frame frequency: 70Hz, SCP: 3215 fs c8.5 clocks,
At this time, the FP multiplied signal becomes 70.2 Hz.

In other words, the basic clock (3215
) It is sufficient to generate sub-clocks sep at 8.5 clock cycles, 10 clock cycles, and 12 clock cycles of fSC.

Here, obtaining the 8.5 clock period can be achieved by switching between the 8 clock period and the 9 clock period.

FIG. 2 is a diagram for explaining the principle of operation of the variable shift register circuit 41.

The variable shift register circuit 41 is a free knob flop (
The 8-bit shift register 51 consisting of LSFI to LSF8) is basically divided into one, and the second is the 8-bit shift register 5.
1 can be switched to an 8/9-bit shift register, a 0-bit shift register, and a 12-bit shift register depending on the LCD mote used.

That is, when forming an 8/9 bit shift register, L
There is an 8-bit register consisting of SFI to LSF8, and a register for one pin between LSF7 and LSF8 (
A 9-bit shift register constructed by inserting a flip-flop 54) can be switched (see Figure 2(b)).
. When forming a 10-bit shift register, use LSFI
This is realized by inserting 1-bit registers (flip-flop 52, flip-flop 54) between LSF2 and LSF2, and between LSF7 and LSF8.
(See figure (c)). When forming a 12-bit shift register, similarly, registers for 2 bits (flip-flops 52, 53 and 54°5) are placed between LSFI and LSF2 and between LSF7 and LSF8.
5) is realized by inserting (see (d) in the same figure).

FIG. 3 shows a specific example of the variable shift register circuit 41 described above. 51 is a flip-flop (LSFI to LSF
8).

The output terminal of flip-flop LSFI is connected to selection circuit 56 and to the input terminal of flip-flop 52. The output terminal of flip-flop 52 is connected to a selection circuit 56 and also to the input terminal of flip-flop 53.

The output terminal of the flip-flop 53 is connected to a selection circuit 56. The output terminal of the selection circuit 56 is connected to the input terminal of LSF2.

Therefore, the selection circuit 56 selects between the output terminal of LSFI and the output terminal of LSF
A flip-flop 5 is connected between the output terminal of LSFI and the input terminal of LSF2.
It is possible to selectively form a state in which the flip-flops 52 and 53 are connected between the output terminal of LSFI and the input terminal of LSF2.

As described above, the switching signals for switching each state of the selection circuit 56 are the mode switching signals MS1. It is MS2.

Furthermore, the output terminal of the flip-flop LSF7 is connected to the selection circuit 57 and also to the input terminal of the free tube flip-flop 54. The output terminal of the flip-flop 54 is connected to the selection circuit 57 and the output terminal of the flip-flop 55
connected to the input terminal of

An output terminal of the flip-flop 55 is connected to a selection circuit 57. The output terminal of the selection circuit 57 is connected to the input terminal of the LSF8.

Therefore, the selection circuit 57 selects the output terminal of LSF7 and the output terminal of LSF7.
A flip-flop 5 is connected between the output terminal of LSF7 and the input terminal of LSF8.
It is possible to selectively form a state in which the flip-flops 54 and 55 are connected between the output terminal of the LSF7 and the input terminal of the LSF8.

The switching signals for switching each state of the selection circuit 57 are the mote switching signal M S 1 applied to the input terminal 71 and the output signal of the control circuit 59 .

The mode switching signal MSI input to the input terminal 71 is
This is a signal for switching the frame frequency. In the example, examples of 60 Hz and 70 Hz are shown.

Mode switching signal M S 2 input to input terminal 72
is a signal for switching the screen mode. In the embodiment, examples of 200 pixels and 240 pixels are shown.

This mote switching signal MSI is supplied to one input terminal of a NAND circuit 59H that constitutes the control circuit 59. The output terminal of the flip-flop 58 is connected to the other input terminal of the NAND circuit 59B. nand circuit 59
The output terminal of a is connected to one input terminal of the ant circuit 59b. The previous mode switching signal MS2 is input to the other input terminal of the AND circuit 59b. The mode switching signal MS2 is further input to the control input terminal B of the selection circuit 56, and the mode switching signal MSI is input to the selection circuit 56.5.
It is input to the control input terminal A of No.7.

The mode switching signal MS1 is also input to one input terminal of each of the NAND circuit 60a and the NOR circuit 60b that constitute the pulse generation circuit 60, and the control circuit 59 is input to the other input terminal of each of the NAND circuit 60a and the NOR circuit 60b. The output of is input. The output of the control circuit 59 is further supplied to a selection circuit 57.
is input to the control input terminal B of. The control circuit 59 selects the selection circuit 57 and the pulse generation circuit 6 using the mode switching signals MSI and MS2 and the output signal of the flip-flop 58.
A switching signal is sent to 0.

The flip-flop 58 converts the 8-bit shift register 5 in each cycle to realize an 8/9-bit shift register.
1 and a 9-bit shift register including a flip-flop 54.

The outputs of the NAND circuit 60a and NOR circuit 60b are input to one input terminal of the NAND circuit 60c and NAND circuit 60cl, respectively. The output terminal of the flip-flop 54 is connected to the other input terminal of the NAND circuit 60c via an inverting buffer 60f, and the output terminal of the flip-flop 55 is connected to the other input terminal of the NAND circuit 60d via an inverting buffer 60g. It is connected.

A NAND circuit 60c is connected to the input terminal of the NAND circuit 60e.
, 60d and the flip-flops LSFI to LSF
7,52,53 outputs are added. Nando circuit 6
The output of 0e is applied to flip-flop LSFI.

A pulse generating circuit 60 generates pulses that control the cyclic synchronization of this system according to various modes.

NAND circuit 65a forming subclock generation circuit 65
, 65b has a flip-flop LS.
The outputs of FI and LSF5 are added respectively. Further, the output terminal of the NAND circuit 65b is connected to the other input terminal of the NAND circuit 65a, and the output terminal of the NAND circuit 65a is connected to the other input terminal of the NAND circuit 65b.

The output terminal of the NAND circuit 65a is also connected to the output terminal 73.

The subclock generation circuit 65 sends out the subclock SCP of this system to the output terminal 73. Below, number of display pixels: 640 x 480 pixels, frame frequency: 70Hz
The operation of the variable shift register circuit 41 will be explained using the case as an example. In this case, the variable shift register circuit 41 is 8/
Operated as a 9-bit shift register.

First, the relationship between the selection operations of the selection circuits 56 and 57 and control signals will be explained.

(1) Control input terminals A and B are both high level “H” (
(hereinafter referred to as "Ho"), the signal at the input terminal 3 is introduced into the flip-flop LSF2.

(2) When control input terminals A and B are A-"H" B-low level "L6 (hereinafter referred to as "Lo") or A-"
When Lo, B-“H”, the signal at the input terminal 2 is introduced into the flip-flop LSF2.

(3) When the control input terminals A and B are both "Lo", the signal at the input terminal O is introduced into the flip-flop LSF2.

Therefore, in order to operate as an 8/9-bit shift register, both the mode switching signal MSI and the mode switching signal MS2 are set to "H". Therefore, the output of the control circuit 59 is set to "H" according to the output of the flip-flop 58.
H', "Lo" is repeated. That is, the output of the flip-flop 58 is "H".

At this time, the output of the control circuit 59 becomes "Lo", and when the output of the flip-flop 58 is "Lo", the output of the control circuit 59 becomes "H".

Next, the operation of the pulse generating circuit 60 will be explained. The output of the NAND circuit 60a becomes "H" when the output of the flip-flop 58 is "H", and becomes "L".

When , it becomes "L". Therefore, the output of the NAND circuit 60c becomes active/inactive in accordance with the H/L level of the output of the flip-flop 58 and is input to the NAND circuit 60e. Also, at this time, the output of the NOR circuit 60b is always “
Since it is Lo, the output of the NAND circuit 60d is always "H', and the NAND circuit 60e is connected to the flip-flop LSFI ~
Output of LSF8゜52.53 and NAND circuit 60c, 6
A cyclic pulse is generated in response to the output of 0d.

The sub clock generation circuit 65 is set by the output signal of LSFI and reset by the output signal of LSF5, and generates the sub clock SCP.

Figure 4 shows the output of each flip-flop during 8/9-bit shift register operation, basic clock (3215) fsc
and a timing chart of the subclock SCP.

In FIG. 4, period T1 indicates the operating period of the 8-bit shift register, and period T2 indicates the operating period of the 9-bit shift register.

Note that the same operation is performed when the 10-bit shift register and the 2-bit shift register operate, so a description thereof will be omitted.

FIG. 5 shows a variable shift register 4 in the display drive circuit 100.
LCD 201a and CR in the display drive circuit 200 with 1 added
The case where both T202a are driven is shown.

In this way, the display drive circuit 200 can also be used in terminals equipped with an LCD interface 201b and a CRT interface 202b.

[Effects of the Invention] According to the present invention, it is possible to correspond to various LCDs by changing the basic clock of the display drive circuit 100, but the display drive circuit further includes a simple circuit for controlling the period of the sub-clock ScP in various modes. 200 can create optimal interface signals for various LCDs without changing the frequency of the basic clock, and can also drive a CRT.

Particularly, when this display drive circuit 200 is integrated, it is effective in terms of versatility.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a chart showing the basic concept of the variable shift register circuit shown in FIG. 1, and FIG. 5 is a diagram showing an example of how the circuit shown in FIG. 1 is used. be. 10.71.72...Input terminal, 73...Output terminal, 21...LX counter, 22...LX decoder,
23...LY counter, 24...LY decoder, 2
5...Mode setting circuit, 26...Adder, 27...Address synthesis circuit, 28.29...Data latch circuit,
3o...Memory circuit, 41...Variable shift register circuit, 51...8-bit shift register, 52-55...
・Flip-flop circuit, 56.57 River selection circuit, 58
...Flip-flop circuits, 5...Control circuits, 6
0...Pulse generation circuit, 65...Sub clock generation circuit, 100, 200...Display drive circuit. Applicant's agent Patent attorney Takehiko Suzue Figure □ - Figure 1

Claims (1)

[Scope of Claims] Shift register means to which a basic clock is supplied, a cyclic period changes according to various mode settings, and outputs a sub-clock corresponding to each mode as an output thereof; and liquid crystal data from the output of the shift register. means for generating a clock signal for reading out the data; first and second address counter means for generating display addresses in the horizontal and vertical directions of the liquid crystal display in accordance with the clock signal; and outputs of the two address counter means. 1. A display drive circuit comprising: means for synthesizing and supplying a read address of liquid crystal display data to a memory; and register means for latching data read from the memory according to the address.