JPH04122034A - Field effect transistor - Google Patents

Abstract

PURPOSE:To reduce an L (inductance) element which is parasitic on wiring and to restrain dispersion thereof by forming a wiring between each electrode and header on a semiconductor chip of thick plating layers 6, 7 which reach a chip rear from each electrode. CONSTITUTION:Not only a source electrode 2 but also a gate electrode 3 and a drain electrode 4 are connected to each of electrode terminals 13, 14 of a header 9 through an L-shaped thick plating layer 7 formed toward an outside of the chip from a semiconductor substrate side. Therefore, an L (inductance) element which is parasitic on the wiring is extremely small, thereby reducing dispersion thereof. Furthermore, since the L-shaped thick plating layer 7 formed toward the outside of the chip has an effect as a buffer material for strain caused by thermal stress, etc., element reliability can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of Ryuto] The present invention relates to a field effect transistor that can reduce the inductance component added to the input and output electrodes of a peer-hole type semiconductor chip and suppress the variation in voltage.

[Conventional technology]

The field effect transistor C (hereinafter referred to as FET) uses Schottky barrier gate structure G, A, and the field effect transistor C (hereinafter referred to as GaAB M E S F E T) uses Galliwam arsenide (hereinafter referred to as Ca) as a single crystal semiconductor substrate. The following explanation will be given using the case of (call) as an example.

Pierhole type GaA4 M E S F ): T is X
It is well known that this method is effective in maintaining high gain in the high frequency region above the band. This is the effect of reducing the parasitic inductance (rLs) due to the source electrode of the FET chip being grounded through the pier hole.

This is largely due to the effect of reducing thermal resistance due to the thinner substrate of the FET chip. By the way, even in the case of this ET, Au wire is generally used for wiring between the gate and drain electrodes on the FET chip and each electrode terminal on the header or the metallized pattern on the dielectric substrate added on the header. It is used in

Figures 3 and 4 show the conventional G1A6 M E S of this type.
In the cross-sectional view of FET, figure @3 shows the chip structure, l! FIG. 4 is an assembly diagram showing the state in which the chip of FIG. 3 is assembled.

In FIG. 3, the source electrode is connected to the back surface of the semiconductor substrate through a through hole (c) formed in the semiconductor substrate 0 by a thick plating layer ω. On the other hand, the gate electrode and the drain electrode are separated from the back surface of the semiconductor substrate.

FIG. 4 shows the assembled state of such a FET chip. The source electrode is grounded from the inside of the through hole to the source electrode of the microwave header via the thick plating layer formed on the back surface of the chip and the solder material surface. On the other hand, the gate electrode and drain currents t@ (to) are added to the header ■ by the Au wire ω, and the dielectric substrate (
b) Pass through the metallized pattern on the gate electrode terminal (
) or drain electrode terminal -.

[Problems to be Solved by the Invention] The conventional FET is configured as described above. Therefore, it is inevitable to use Au wire for wiring from the gate electrode and drain electrode to each chamber I@terminal of the header. For certain reasons, in devices that operate at high frequencies, variations in the inductance component of this Au wire or variations in the AuJ length (variations in inductance) are factors that impede performance.

Father, when the dielectric substrate and metallized pattern added to the header 〇2 constitute an impedance matching circuit, such as in a large signal element, variations in this L (inductance) component become a major factor that inhibits matching. There is one problem.

This invention has been made with the aim of solving the above-mentioned problems, and the object is to obtain an FET that can reduce the Ll inductance component added to the chip electrode and its variation.

[First Means to Solve the Problem] This FET has two pairs of grounded poles (sources), a pair of grounded poles (sources), a pair of grounded poles (sources), a pair of grounded poles (sources), a pair of grounded poles (sources), a pair of grounded poles (sources), a pier hole that penetrates the semiconductor substrate (this is filled with a thick plating layer, and an input pole). For the (gate) and output electrode (drain), a thick plating layer is formed on the side wall of the chip, and a thick plating layer corresponding to each pole is placed on each it pole terminal-1 echenocou of the microwave header. The sidewall thick plating layer is formed in an L-shape on the back side of the chip toward the outside of the chip. A thick plating layer, also formed on the outside of the chip, is added to each electrode end preform of the microwave header or header, and one is directly bonded to the metallized pattern on the dielectric substrate.

[Effect]

In this invention, the thick plating layer is formed in an L-shape from the side of the chip 11 to the outside of the chip, and the connection between the input/output electrodes on the semiconductor chip and each electrode terminal of the header is achieved by the thick plating layer. Therefore, the L (inductance) component due to wiring is reduced, and at the same time, the variation thereof is also reduced, making circuit design easier. This is because adhesion to the t-pole terminal of a microwave header or the metallized pattern on the rusted dielectric substrate added to the header is done at the edge of the thick plating layer, which is formed facing away from the outside of the chip. Distortion in the header and chip connection caused by heat, heat, and heat is absorbed in this part, which is effective in increasing reliability.

[Embodiment] ~ Hereinafter, one embodiment of the present invention will be explained in detail. Figures 1 and 2 are GaAsM
A cross-sectional view of the ESFET, and Figure 2 shows the chip structure.

FIG. 2 is an assembly diagram showing the assembled state of the chip shown in FIG. 111. In the figure, the source electrode (2) is on the semiconductor substrate It)
It is connected to the back surface of the semiconductor substrate m through a through hole (5) formed in the first plating layer (C?). - direction,
The gate electrode (3) and drain electrode (4) are connected to each chamber ffl.
i3).

(4) reaches the back surface of the semiconductor substrate +11, and the substrate (1) q
The second thick plating layer (connected by a sword) is formed from the top and bottom sides to the outside of the chip.
A second thick coating layer (7
), which can be easily obtained by applying two well-known pier hole formation techniques, thick hole formation techniques, and chip separation techniques.

From a thermal point of view, the width of the thick plating layer (6) formed on the back surface of the semiconductor substrate 11) is seen as a problem, but in reality, the semiconductor substrate fl) is thinned to several 10 μm, so heat generation on the chip surface increases. Even if we put the spread of heat flow from the region into *[, it doesn't pose much of a problem.

Figure 2 shows the chip in Figure 1 connected to a microwave header (9
) This is a schematic configuration when one is implemented. In this figure, a dielectric substrate G is added to the electrode (to) corresponding to the input and output of the header (9), α◆, and the metal laz pattern 0 on its surface is
2 is formed and acts as an impedance matching circuit.

As can be seen from the figure, the source electrode (2) is not as strong as G, and the gate voltage ffl +31 and the drain electrode (4
) is also formed in an L-shape from the side of the semiconductor substrate toward the outside of the chip, and the header (9) is formed by the T-thick plating layer (7).
Each electrode terminal 03. It is bound to n41.

Therefore, the L (inductance) component parasitic to the wiring is extremely small, and its variation can also be reduced. First, there is a thick plating layer in an L-shape (7 mm) formed toward the outside of the chip.
) is effective as a buffer material for distortion caused by thermal stress, etc., and leads to improved reliability of the γ-instrument element.

In the figure, (8) is a solder material, and the pin is a source electrode terminal (0).It goes without saying that the structure of the microwave header (9) must be designed in accordance with the shape of the chip.

It should be noted that although the above embodiment has been explained using the G&^8 MESFET as an example, the present invention is not limited thereto, and it goes without saying that it can be similarly applied to other device structures.

〔Effect of the invention〕

As described above, according to the present invention, the wiring between each electrode on the semiconductor chip and the header is formed of a thick plating layer extending from each electrode on the semiconductor chip to the back surface of the chip. ) The components can be made small and their variations can be suppressed, and the device performance can be improved. In addition, the thick plating layer is formed into an L-shape (this is because the chip and the header or the metallized pattern on the dielectric substrate attached to the header are in contact at the ends of the L-shaped thick plating layer). Since the portion acts as a buffer against distortion caused by thermal stress, etc., it is effective in increasing the reliability of the device.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views showing one embodiment of the FET of the present invention, and FIGS. 3, 3, and 4 are cross-sectional views of conventional FETs. In the figure, (1) is a semiconductor substrate, and (2) is a source electrode. (3) is a gate electrode, (4) is a drain electrode, (5) is a through hole, (6) is a first thick plating layer, and (7) is a second thick plating layer. (8) is solder material, (9) is microwave header, ■
0]) is a dielectric substrate, 02 is a metallized pattern, Q3 is a gate electrode terminal, and (2) is a drain electrode terminal. In Figure 1, the same symbols indicate the same or equivalent parts.

Claims (1)

[Claims] A coupling medium between a semiconductor chip having a plurality of electrodes having different properties and an electrode terminal formed on a microwave header or a dielectric substrate having a desired electrode pattern on the surface added to the header is a via in the source electrode section. A field effect transistor characterized in that the metal layer is a metal layer filled in holes and via holes, and a sidewall-shaped metal layer formed on the side surface of a chip in the gate and drain electrode parts.