JPH04116484U - signal detection circuit - Google Patents

Abstract

(57) [Summary] [Purpose] A signal detection circuit for television receivers that is capable of high-speed response signal judgment without detection lag and without false judgments due to video signal leakage. [Structure] A circuit including an inverter 6 that outputs a first state indicating a period in which a horizontal synchronizing signal of a composite synchronizing signal separated from an image signal exists and a second state indicating a period in which the horizontal synchronizing signal does not exist. 1 to 6) and the above inverter 6
a sampling circuit 7 that samples the output from the sampling circuit 7 a fixed number of times at a period corresponding to the vertical scanning period or an integral multiple thereof; a counting circuit 8 that counts the output from the sampling circuit 7; Judgment circuit 11 that compares with a reference number of times and outputs a judgment output
It is equipped with [Effect] In the minimum case, signal judgment can be made in one vertical scanning period, and a signal judgment circuit with high-speed response without malfunction can be realized.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This invention is a signal detection circuit used for detecting regular tuning points in television receivers, etc. Regarding.

0002

[Conventional technology]

In conventional signal detection circuits, logic outputs the AND of the tuning signal and the horizontal pulse. The detection voltage was obtained by integrating the output of the product circuit.

0003

[Problem that the idea aims to solve]

However, in the above-mentioned conventional technology, synchronization is separated depending on the receiving state or detuning state. There are times when the image signal leaks into the separation output, and there is no signal (or it is out of tune) Despite this, there were cases where it was incorrectly determined that there was a signal. In addition, these misjudgments can be reduced. If you increase the integral constant of the AND circuit to reduce the However, this has disadvantages such as a detection delay.

0004 Therefore, in view of the above-mentioned problems of the conventional technology, the present invention aims to solve the problem of image signal leakage. It is possible to judge signals with high-speed response without causing false judgments or detection delays. Signal detection circuit for detecting presence or absence of image signal reception in a television receiver The purpose is to provide

[0005]

[Means to solve the problem]

In order to achieve the above object, according to the present invention, a shadow in a television receiver is provided. A signal detection circuit that detects the presence or absence of image signal reception, and is separated from the image signal. The first state indicating the period in which the horizontal synchronization signal of the composite synchronization signal exists and the horizontal synchronization output means for outputting a second state indicating a period in which no signal exists; Samples the output of the a first state and a second state of the output from the output means; The states are counted at the above sampling period, and the first state or the second state is the reference. determining means for determining whether the output is in the first state or the second state when the number of times is reached; A signal detection circuit is proposed.

[0006]

[Effect]

That is, according to the signal detection circuit of the present invention described above, the multiplex signal separated from the image signal is It is possible to clearly determine the period in which the horizontal synchronization signal exists and the period in which it does not exist. By integrating with an integral constant such as The leakage of image signals mistakenly extracted as signals occurs periodically in the vertical scanning period. Therefore, detection is performed at a sampling period equivalent to the vertical scanning period or an integral multiple thereof. When the ratio of the period in which the horizontal synchronization signal exists and the period in which it does not exist exceeds a certain value This is prevented by determining the presence or absence of a signal.

[0007]

【Example】

Hereinafter, the present invention will be explained with reference to the drawings.

[0008] Figure 1 shows the composite tuning signal output to the synchronization separation output, and (a) shows the synchronization separation output obtained when normal broadcast waves are received. Ma In addition, (b) shows the synchronization separation output when detuned to a high degree from the normal tuning point. It is. When detuned to a high degree from the normal tuning point, the frequency characteristics of the video intermediate frequency amplifier will change. Because the video signal level decreases and the audio level increases due to Ideally, the power supply inside a television set is powered by a flyback transformer. Because it is extracted from the secondary winding of (FBT), the vertical scanning period may change due to load fluctuations. Ripples tend to occur, especially when detuned to a high point, this ripple becomes large. This causes the slice level of the sync separation output to fluctuate, causing vertical running to the sync separation output. Periods with and without synchronization are mixed in the scan cycle, and a synchronization signal that fluctuates periodically is output. may be done. Similarly, when detuned to a high degree, the characteristics of the video detection circuit , the video signal is inverted and the video signal is mistakenly extracted as the sync signal, resulting in sync separation output. In some cases, some image signal components are output. At this time, it appears on the synchronous separation output. The repetition period of the synchronization signal or image signal component is the vertical scanning period.

[0009] FIG. 2 shows an example of a commonly used signal detection circuit. 1 is the synchronization signal input terminal child, 2 is a horizontal pulse input terminal, 3 is an AND circuit, 4 and 5 are AND circuits, respectively. A resistor and a capacitor for integrating the output of circuit 3, 6 an inverter circuit, 7 This is a signal detection output terminal. In such a signal detection circuit, resistor 4 and capacitor The period in which the horizontal synchronization signal exists and the period in which it does not exist can be clearly obtained by using the sensor 5. If the integral time constant is set as 3(a) and 3(b) are obtained at the input of the inverter 6. It will be done. Here, Vth in FIG. 3 indicates the threshold voltage of the inverter 6. FIGS. 4(a) and 4(b) show the output voltage of the inverter 6. The period indicates a state in which there is no synchronization signal (period in which there is no synchronization signal), although it may exist, The L level period indicates a period in which no synchronization signal exists. In this way, the normal tuning point also Regardless of the situation, the output is a mixture of periods without synchronization and periods with synchronization, and H Alternatively, it is not possible to determine whether there is a signal using only L. Generally, as shown in Figure 4(b) It is preferable to determine that there is no synchronization signal (no signal) during the period when a certain output is obtained. As a way to improve these, when using an integrating circuit consisting of 4 resistors and 5 capacitors, The constant is large enough to smooth out the signal components that appear in the vertical scanning period. It is possible to reduce the With this method, waveforms like those shown in Figures 5(a) and (b) are obtained. Therefore, it is possible to detect the presence of a signal in (a) and the absence of a signal in (b). but In this way, when the time constant is increased, the detection response time becomes longer, so the detection time It takes a long time and is not suitable for devices that require a quick response such as auto search. .

0010 FIG. 6 shows an embodiment of a signal detection circuit according to the present invention. 1 to 6 are the times mentioned above. It is the same as the road. 7 is the output of the inverter 6 at the vertical scanning period or an integral multiple thereof. A sampling circuit that performs sampling a certain number of times in a period, 8 is a sampling circuit Detection count count that counts the number of times the output goes to H level or L level. 9 is a timing pulse for the sampling circuit 7 and the detection number counting circuit. 10 is a timing pulse generation circuit that generates a timing pulse. The start and stop of timing pulse generation from 9 is controlled by the H level and L level, respectively. A control signal input terminal 11 is used to control the count number and reference number of the detection number counting circuit 8. Compare the number of times, and when the number of H level or L level detection reaches the standard number, the logic Judgment circuit that outputs whether the inverter 6 output of the product output circuit is H level or L level , 12 are signal judgment output terminals.

[0011] In FIG. 7, the output of the inverter 6 of the logic circuit has a waveform as shown in (a), and H During the level period, there is a horizontal synchronizing signal, and on the other hand, during the L level period, there is no horizontal synchronizing signal. Connect the control signal input terminal 10 to the type shown in (b) whose period is approximately equal to the vertical scanning period. When the pulse that determines the timing pulse generation period is input, the almost vertical pulse as shown in (c) A timing pulse occurs only for a period equal to the scan period, and this pulse The signal is input to a counting circuit 7 and a detection number counting circuit 8. By the sampling circuit 7, The output of the inverter 6 is sampled at the timing of this timing pulse, and each Counts the number of times H level or L level occurs for sampling. It is detected by the detection circuit 8. The count number of H level of this detection count circuit 8 indicates the period during which the horizontal synchronization signal exists. The judgment circuit 12 determines whether the H level or compares the count number of L level with the reference number and determines H level or L level The result is output from the signal judgment output terminal. Here, for example, sampling period 2 If sampling is performed 9 times in ms and the number of H level detections is 5, the horizontal The point in the judgment circuit 1 is that the ratio of the period in which the period signal exists and the period in which it does not exist is approximately 1:1. This is the threshold level for determining the presence or absence of a signal of 1. Therefore, this thread In the case of the hold level, in this example, for the waveform shown in FIG. 7(a), Since the H level is narrower than the L level, it outputs the L level, and the judgment result is water. There will be no flat synchronization signal. Here, in this embodiment, as the input of the sampling circuit 7, can be explained by using the integrated output of the AND of the synchronization signal and the horizontal pulse. As explained above, by providing the sampling circuit 7 with a counter function, the synchronization signal can be Similar results can be obtained by directly counting the pulses of Wear. Furthermore, the signal input to the control signal input terminal 10 has a period equal to the vertical scanning period. Although we explained using a pulse with a period that is an integer multiple of the vertical scanning period, Similar results can be obtained with pulses. In addition, this pulse is a several series synchronization signal There is no problem even if the phase relationship is asynchronous, and there is no problem as long as the period is close to the vertical scanning period.

0012

[Effect of the idea]

According to the present invention, periods in which a horizontal synchronization signal exists and periods in which it does not exist coexist. Even in such a case, it is possible to judge the signal in one vertical scanning period in the minimum case. A high-speed response signal determination circuit without malfunction can be realized. In addition, the circuit described in this invention can be easily realized using a microcomputer, so it can be constructed at low cost. Ru.

[Brief explanation of drawings]

[Fig. 1] (a) and (b) are waveform diagrams showing synchronous separation output waveforms,

FIG. 2 is a circuit diagram showing a conventional signal detection circuit;

FIG. 3 is a waveform diagram showing waveforms of the signal detection circuit in FIG. 2;

FIG. 4 is a waveform diagram showing waveforms of the signal detection circuit in FIG. 2;

FIG. 5 is a waveform diagram showing waveforms of the signal detection circuit in FIG. 2;

FIG. 6 is a circuit diagram showing an embodiment of the signal detection circuit according to the present invention;

FIG. 7 is a waveform diagram showing waveforms of main parts in FIG. 6;

[Explanation of symbols]

1...Synchronization signal input terminal, 2...Horizontal pulse input terminal, 3...Logic product circuit, 7...Sampling circuit, 8...Detection count circuit, 9...timing pulse generation circuit, 11... Judgment circuit.

Claims (1)

[Scope of utility model registration request] 1. A signal detection circuit for detecting whether or not a video signal is received in a television receiver, the circuit comprising: a first state indicating a period in which a horizontal synchronization signal of a composite synchronization signal separated from the video signal exists; output means for outputting a second state indicating a period in which the horizontal synchronization signal does not exist; sampling means for sampling the output from the output means a fixed number of times at a period corresponding to the vertical scanning period or an integral multiple thereof; The first state and the second state of the output from the output means are counted at the sampling period, and when the first state or the second state reaches a reference number of times, the output changes to the first state or the second state. 2. A signal detection circuit characterized by comprising: determination means for determining whether the state is in the above state.