JPH04115313A - Solar battery power controller - Google Patents

Abstract

PURPOSE:To reduce a switching loss and the generation of noise and to supply a large part of power from a solar battery array to a load side even when a power stage is in a fault by allowing only one power conversion state to execute switching operation and holding other power conversion stages always at an ON or OFF state. CONSTITUTION:When a bus voltage VBUS is included in VBH<1> to BBL<1>', only a control signal (b) to a switching power conversion stage 8 is included in a pulse width control area and other switching power conversion stages are turned off. When the bus voltage is in VBH<2> to VBL<2>, only a control signal (c) is included in the pulse width control area, the conversion stage 8 is turned on and the conversion stages 10, 11 are turned off. When the bus voltage VBUS is in the VBH<k> to VBL<k>, only a control signal (d) is included in the pulse width control area, a 1st to (k-1)th conversion stages are turned on and the (k+1)th to N-th stage conversion parts are turned off. When the bus voltage VBUS is in VBHN to VBLN, only a control signal (e) to the N-th conversion stage 11 is included in the pulse width control area and all the other stages, i.e. the 1st to the (N-1)th stages, are turned on.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a solar cell power control device used on the ground and in artificial satellites.

[Prior Art] FIG. 9 is a block diagram showing a conventional solar battery power control device, in which (1) is a solar battery array, (5) is a power supply bus, (6) is a capacitor bank, and (7) is a solar battery array. is the load, (8
) is a pulse width controlled switching power conversion stage, (12
) is an error detector.

The operation will be explained below. An embodiment of a pulse width controlled switching power stage (8) is shown in FIG. 9, in which a transistor.

A buck-type switching power conversion stage is configured by an inductor, a diode, and a pulse width control circuit. The output current of the solar cell array (1) is:

It is switched in a switching power stage (8) and smoothed by an inductor and capacitor bank (6) within the switching power stage (8). The voltage of the power supply bus (5) is detected by an error detector (12).

The error detector (12) compares the voltage of the power supply bus (5) with the reference voltage (''/r*r) and amplifies it, and outputs an error detection signal f7) fV, -.Error detection The signal (■.r,,) is.

Lrr ・G+ [K+X”/Bus-Vr*r)
(1) However ■. 8: Power supply bus (5)
The bus voltage G, , : is given as a constant.

This error detection signal (A) is transmitted to the switching power conversion stage (8
) is sent to the pulse width control circuit in the power supply bus (5), which performs pulse width control in the switching power conversion stage (8).
) Feedback control works to keep the voltage (Viug) constant.

Here, the current scale generated by the solar cell array (1) is NX
Assume that I s (N: integer) and the current flowing into the load (7) are ■.

As long as NxIg≧IL(2) holds true, the bus voltage (Vaus) is regulated.

N XIII<IL
(3), switching power stage (8)
is always on, i.e. the transistors in the power stage (8) do not switch, are always on and the bus voltage (
Vmus+) is lower than the regulation voltage and becomes a voltage that balances the voltage/current characteristics of the solar cell array (1) and the load characteristics of the load (7).

Furthermore, when eIL becomes almost 0, the bus voltage (Vsus) is regulated, but it approaches the upper limit bus voltage of regulation and the transistor switching is turned on.
The duty approaches 0%.

[Problem N to be solved by the invention] Since the conventional solar battery power control device is configured as above 9, during bus voltage (Vsug) regulation, the switching power conversion stage (8) It is necessary to switch all the current corresponding to .

In particular, when the load current (2) is large, switching losses occurring in the transistors and diodes in the switching power stage (8) become large. Another problem is that large amounts of noise are generated due to the switching of large currents.

In addition, since the power of the solar cell array (1) is handled by only one switching power stage (8), if the switching power stage (8) fails, the solar cell array (1)
There was a problem that the electric power was not effectively supplied to the load (7).

This invention was made to solve the above-mentioned problems, and it reduces switching loss in the switching power stage that controls the supply of solar cell power, further reduces the generated noise, and also reduces the switching loss in the switching power stage that controls the supply of solar cell power. An object of the present invention is to obtain a solar cell power control device that can supply most of the power of a solar cell array to a load side even if a failure occurs.

[Means for Solving the Problems] A first power control device according to the present invention divides a solar cell array into N pieces in parallel, and provides an individual pulse width control type switching power conversion stage for each solar cell array. and connecting the outputs of these switching power conversion stages to a power supply bus, and sequentially performing switching operations of the N pulse width control type switching power conversion stages according to the divided bus voltage control range, Within the control range of each stage, the on-duty of the switching power conversion stage is varied between 0% and 100%.

The second power controller replaces the pulse width controlled switching power conversion stage in the first power controller.
Using off switches, the switching operations of these N on/off switches are performed sequentially according to the nine divided bus voltage control ranges, and on/off limit cycle operations are performed within the control range of each stage. It was made by

[Operation 1] The first power control device according to the present invention performs a switching operation on only one power conversion stage in a control region divided into two among N pulse width control type switching power conversion stages, and controls other power conversion stages. The stage is always kept on or off.

The second power control device performs on/off limit cycle operation on only one on/off switch in a nine-divided control region among the N on/off switches, and controls other on/off switches. The switch is always kept on or off. Further, the on/off switch does not include an inductor, and the capacitor bank of the power supply bus is coupled to form a secondary pole in the control system loop.

[Example] Hereinafter, an example of the first power control device of the present invention will be described using FIG. 1. In Figure 1, (1) to (4
) is the divided solar cell array (5) is the power supply bus,
(6) is the capacitor bank, (7) is the load, (8) ~
(11) is a pulse width controlled switching power conversion stage;
(12) is an error detector, and (13) is a stage number switch for sequentially operating the N pulse width controlled switching power conversion stages.

The solar cell array is divided into N pieces.

(1) represents the first stage solar cell array, (2) represents the second stage solar cell array, (3) represents the second stage solar cell array (l≦≦N), ( 4) shows the Nth stage solar cell array. Voltage of power supply bus (5) (VBus)
is input to the error detector (12), and an error detection signal (7) (V, , , ) is output as in the conventional technique.

This error detection signal (■.,,?) is expressed as V*rr"G+X (K+X VBug-Vr, r
) is given by (1).

In response to this error detection signal (A) (V,,,), the one-stage number switch (13) outputs an error detection signal (A) (V,,,)
That is, control signals (a) to (e) for sequentially operating the switching power conversion stages (8) to (11) in accordance with the bus voltage (Vaug) are output.

Fig. 2 shows control signals (A) to (O) to the first to Nth stages of the switching power conversion stage according to the error detection signal (A) (V, , , ) and the bus voltage (vBus). shows how it changes.

In Figure 2, the horizontal axis is the error detection signal (A) (V,...
) and Vlltll, and the vertical axis shows the level of the control signal. The control signals (A) to (C) are input to each pulse width control circuit in the switching power conversion stages (8) to (11). Regarding the control signal levels in Figure 2, the dashed line marked (even) is the level at which the on-duty is 0% in pulse width control (PWM), and the broken line marked (ch) is the level at which the on-duty is 0% in pulse width control (PWM). On duty is 10 in
Indicates the level of 0%.

At control signal levels between (ri) and (h), the pulse width control (PWM) on-duty changes between 0% and 100%, and at lower levels (event), the switching power conversion stage changes. is off, and at a level higher than (h), the switching power conversion stage is on (always conductive).

When the bus voltage (Vsug) is between VIIM' and Vat,', only the control signal (a) to the first stage (8) of the switching power conversion stage is in the pulse width control region (on and
(duty varies from 0 to 100%), the control signals of the other stages are all at a level lower than the (evening) level, and the other switching power conversion stages are turned off.

When the lotus voltage (Vaull) is between Vllll'' and vIIL'', only the control signal (two) to the second stage (9) of the switching power conversion stage is in the pulse width control region, and the control signal (two) of the first stage is in the range of pulse width control. A) is higher than the level of (H), and the first switching power conversion stage (8) is turned on, and the third stage ~
The control signals (1) to (O) to the Nth stage are lower than the level of (Y), and the control signals (1) to (O) to the Nth stage are lower than the level of (Y), and the control signals (1) to (O) to the Nth stage to the switching power conversion stage (
10) to (11) are off.

Similarly, the bus voltage (V!
Between VaL'(7), only the control signal (1) to the switching power conversion stage (lO) is in the pulse width control region, and the control signals for the first to eleventh stages are (chi). ), the switching power conversion stages from the 1st stage to the 11th stage are turned on, and the control signals from the +1st stage to the Nth stage become (
(evening), and the +1st to Nth switching power conversion stages are turned off.

Sarani, Hass voltage (Vaus) is VmH”~VW+t
, ', the Nth switching power conversion stage (11)
Only the control signal C) is in the pulse width control region,
The control signals from the first stage to the N-1th stage are all higher than the level (H), and the switching power conversion stages from the first stage to the N-1th stage are all turned on.

Figure 3 shows how the operating state of each pulse width controlled switching power stage changes sequentially according to the error detection signal +7) (V, r, ) and the bus voltage (Vsus) as described above. It is. Bus voltage■,'~VB+,,'
The area between is the bus voltage regulation region.

FIG. 4 shows the output current of each switching power stage when pulse width control is performed in the first stage (10) of the switching power stages. I1 is the output current of the first stage (8), I2 is the output current of the second stage (9), Ik is the output current of the first stage (10), and is the output of the Nth stage (11). Indicates current. Is, Iz.

--, Ik-1 is a direct current because the switching power conversion stage is on (always in a conductive state).

Since the switching power conversion stage (lO) performs switching under pulse width control, (2) is a DC current that includes a ripple component. Engineering. 3. --- IN is zero because the switching power conversion stage is off.

In this way, only the first switching power conversion stage (10) performs switching.

For convenience of explanation, the generated current of each solar cell array (1) to (4) is assumed to be 18, and the output current of each solar cell array is made equal, but without losing generality. ), calculate the load current,
When the first stage performs pulse width control,

It is. Ik is + O""' I depending on the size of IL
Varies between s.

The losses in the switching power conversion stages (8) to (11) are as follows.

Each loss in the 1st stage to the 11th stage is on-voltage x I8 The loss in the 1st stage is the maximum, on-voltage x on-duty + switching loss + each loss in the 1st to Nth stage is zero, and in particular, only the first stage generates switching loss, so the overall loss is kept low, and the current that contributes to the switching loss in the first stage is also the largest, so this switching Losses are also low (reduced).

Furthermore, only the switching current value in the first stage (which is approximately equal to the output current Il) contributes to noise generation, which is less than the maximum value, so noise generation is also small.

Note that which switching power conversion stage performs pulse width control switching changes depending on the magnitude of the load (7) and the magnitude of the current generated by the solar cell arrays (1) to (4). The equation (4) determines which stage performs pulse width control switching, but it also depends on where the bus voltage (VSυ, ) is balanced in the regulation voltage width and its relationship with the magnitude of the load and the magnitude of the current generated by the solar cell. This is shown in FIG.

In FIG. 5, the first quadrant represents the number of switching power conversion stages supplying to the load side and the bus voltage (Vsug).

It shows the relationship between the magnitude of the load (7) and the solar cell generated currents (1) to (4), and the second quadrant shows the bus voltage (■.,) and the error detection signal (A) (V,,,,) The relationship with
The four quadrants show the movement of the switching power conversion stages in the stage number switch.

For example, when the first stage is performing pulse width control,
The characteristic of load (7) is (e), and the bus voltage is maintained at Pk and balanced.

Here, when the resistance value of the load (7) decreases, the load voltage increases, and the load characteristic changes toward the characteristic (ri), the stage that performs pulse width control shifts toward the Nth stage. Moving.

When the load current increases to the extent that NXl5=IL, the Nth stage performs pulse width control, the bus voltage operating point becomes PM, and the bus voltage becomes vBL''', the lower limit of regulation.

Note that even when the current (Is) generated by the solar cell array decreases, the operating point Pk moves in the direction of PN.

On the other hand, the resistance value of load (7) is thick (load electric lacquer,
When IL decreases and the load characteristics change toward (force) characteristics, the stage that performs pulse width control moves in the direction of the first stage. The first stage performs pulse width control, the bus voltage operating point becomes Pl, and the bus voltage approaches the regulation upper limit v,'.

Next, a sixth embodiment of the second power control device of the present invention will be described.
This will be explained using figures. In FIG.

(1) to (4), f5) to (7), (12
) and (13) have the same functions as those in FIG. 1, and (14) to (17) are on/off switches.

Similar to the first power control device shown in FIG. 1, the error detector (12) receives an error detection signal (
A) (V, r,) is output, and the one-stage number switch (13) outputs a control signal (all )~
(ce) is output.

In this second power control device, the control signal may be a binary signal that can simply drive the on/off switches (14) to (17).

Figure 7 shows how the on/off switch control signal is changed according to the error detection signal (A) (V, , ) and the bus voltage (VBus), and the on/off switch changes sequentially. .

The method of sequentially changing the electronically controlled on/off switch is the same as that of the first power control device. however,
The operation of the power stages within each membrane is different and is explained below.

In FIG. 7, when the on/off switch in the 1st stage is performing a control operation, the bus voltage (Vsug) is VB)l
', the on/off switch (6) turns off,
Eventually, the bus voltage decreases, and when it reaches Lk, the on/off switch (6) is turned on again, raising the bus voltage.

Limit cycle operation is controlled by repeating this process.

Calculate the current generated by each solar cell array (1) to (4).

, the load current is expressed as rL, and the following holds true when the first stage is performing limit cycle operation.

However, Fig. 8 shows the stage (16) of the on/off switch.
) shows the output current of each on/off switch when it is performing limit cycle operation.

1,, I2. ...* Ik-1 is a direct current equal to , since the on/off switch is on. ■、The switch is on/off limit/
Since the cycle operation is repeated, it becomes a pulse current with a high peak value. Here Im out.

Since only aIK is supplied to the load (7) side, while the on/off switch (16) is on,
(1-α) The current for Ik is the capacitor bank (6)
is charged and the bus voltage (Vmus) becomes V! It rises to IN'. In addition, during the period when the on/off (16) is off, the current for α is discharged from the capacitor bank (6) and is supplied to the load (7), and the bus voltage drops to VIL'. and go (.

It will be shown below that the on-time and off-time of the pulse current shown in FIG. 8 are determined by the parameter α that depends on the load resistance and the solar cell array generated current I3.

The parameter α that depends on the load resistance (the ratio of the current supplied to the load side of the current generated by the solar cell array in the 1st stage when the 1st stage is operating) and the generated current of the solar battery array Determined by engineering.

In this way, in control by limit cycle operation, etc., the transfer function to the bus voltage (Vsus) due to the operation stage of the on/off switch and charging/discharging of the capacitor bank (6) is as follows.

Therefore, the operating frequency (f) of limit cycle control
teeth.

1+RC5 where R: resistance value of load resistor (7) S function in Niraplus conversion C: capacitance of capacitor bank (6), and has the -order form. This is the on/off switch (
14) to (I7) do not include inductors, so
This is because no secondary pole is generated.

The loop transfer function of the entire voltage control system is easily formed by equation (9). Therefore, a stable voltage control system can be easily obtained.

In addition, which stage of the on/off switch operates depending on the magnitude of the load (7) and the magnitude of the current generated by the solar cell arrays (1) to (4) is determined by equation (5). bus voltage,
The diagram showing the relationship between the magnitude of the load current, the magnitude of the current generated by the solar cell, and the operating stage of the on/off switch is the same as FIG. 5.

[Effects of the Invention] As described above, in the first power control device and the second power control device of the present invention, the entire solar cell array is divided into N pieces, and pulse width control type switching is applied to each of the solar cell arrays. Since the power stage or on/off switch is connected and only one pulse width controlled switching power stage or on/off switch is operated for bus voltage control, the power stage and switch Switching loss is reduced, and the switching current is smaller than the current generated by one divided solar cell array, so it is small (it has the effect of reducing noise generation).

Furthermore, even if a failure occurs in one solar cell array divided into nine parts, a switching power stage, or an on/off switch, other solar cell arrays, switching power stages, or on/off switches
Power is effectively supplied to the load side by the off switch,
This has the effect of providing a highly reliable power control device.

Furthermore, since the second power control device performs limit cycle control without including an inductor in the on/off switch, it has the effect of easily obtaining a stable linear transfer function of the voltage control system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the first power control device of the present invention, FIG. 2 is an explanatory diagram of the operation of the stage number switch of the first power control device, and FIG. Figure 4 is an explanatory diagram of the operation of the switching power conversion stage of the power control device.
Figure 5 shows the waveform of the output current of the switching power conversion stage of the power control device. 6 is a block diagram showing the configuration of an embodiment of the second power control device of the present invention, FIG. 7 is an explanatory diagram of the operation of the on/off switch of the second power control device, FIG. 8 is a diagram showing the waveform of the output current of the on/off switch of the second power control device, and FIG. 9 is a block diagram showing the configuration of the conventional power control device. (11 to (4) are solar cell arrays, (5) is a power supply bus, (6) is a capacitor bank, and (7) is a load. (8) to (11) are pulse width controlled switching power conversion stages, ( 12) is an error detector, (13) is a stage number switcher. (■4) to (17) are on/off switches, (A) is an error detection signal, (A) to (O) are control signals, ( Power)~(
ri) is the load characteristic, (su) to (ce) are the control signals, C9)
(h) is the signal level. In addition, in FIG. 9, the same reference numerals indicate the same.

Claims (2)

[Claims] (1) In a device that supplies power from a solar cell array, the solar cell array consists of N parallel arrays, and the output of each solar cell array is connected to the input of N pulse width controlled switching power conversion stages. and the outputs of the N switching power conversion stages are connected to a power supply bus;
A capacitor bank and a load are connected to the power supply bus, the voltage of the power supply bus is input to an error detector, the output of the error detector is input to a stage number switch, and the stage number switch is connected to the N number of stages. outputs N control signals for sequentially operating the pulse width controlled switching power conversion stages according to the bus voltage, and outputs the N control signals to respectively operate the N pulse width controlled switching power conversion stages. solar cell power input to the switching power stage and changing the on-duty of each switching power stage between 0% and 100% within the bus voltage control range handled by each pulse width controlled switching power stage. Control device. (2) In a device that supplies power from a solar cell array, the solar cell array consists of N parallel arrays, the output of each solar cell array is connected to the input of N on/off switches, and the above The outputs of the N on/off switches are connected to a power supply bus, a capacitor bank and a load are connected to the power supply bus, and the voltage of the power supply bus is input to an error detector, which detects the error. The stage number switcher outputs N control signals for sequentially operating the N on/off switches in accordance with the bus voltage, and the N number of control signals Input the signals to each of the above N on/off switches,
Within the bus voltage control range that each on/off switch is responsible for, each on/off switch can be set to the on/off limit.
A solar battery power control device characterized by performing cycle operation.