JPH04115231A - Semiconductor device for light valve substrate - Google Patents

Abstract

PURPOSE:To obtain the semiconductor device which is finely integrated to a high density by providing MOSFETs for switching elements having a high breakdown strength structure. CONSTITUTION:Since a polished silicon single crystal thin-film layer 1 is laminated on a quartz glass substrate 7, the film thickness thereof is settable freely. Then, an impurity is diffused limitedly only to the surface part of the thin film 1 having a desired film thickness, by which source regions and drain regions having shallow junction depths are formed. The semiconductor device for light valve substrates which has extremely high reliability and hardly generates a breakdown is provided in this way. The finer switching elements are formed by adopting this breakdown strength structure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a drive substrate for a flat light valve used in a direct view display device, a projection display device, etc., and particularly relates to a drive substrate on which a semiconductor integrated circuit is formed. . Such a driving board is used, for example, in assembling a liquid crystal panel and constitutes an active matrix type light valve device.

[Conventional technology]

In order to facilitate understanding of the present invention, the principle of a conventional active matrix device will first be briefly explained.

An active matrix device is composed of a group of pixels arranged in rows and columns. A switch element group is provided on the substrate surface corresponding to each pixel, and when a specific pixel is selected, the corresponding switch element is made conductive, and when non-selective, the switch element is kept in a non-conductive state. This switch element is formed on a glass substrate of an active matrix device consisting of a liquid crystal panel. Therefore, technology for thinning the switch element is important. As this element, an insulated gate field effect thin film transistor is usually used. Hereinafter, in this specification, this type of transistor will be referred to as a thin film MO.
It is called 3FET.

Conventionally, in active matrix devices, thin film MO
The 8FET was formed on the surface of an amorphous silicon thin film or a polycrystalline silicon thin film deposited on a glass substrate. Amorphous silicon thin films can be easily deposited on glass substrates by vacuum evaporation or sputtering, and polycrystalline silicon thin films can be easily deposited on glass substrates using chemical vapor deposition, making them suitable for manufacturing relatively large-screen active matrix devices. Are suitable.

[Problem that the invention seeks to solve]

Active matrix devices using conventional amorphous silicon thin films or polycrystalline silicon thin films are widely used in direct-view display devices because they can relatively easily form a large-area image plane. However, it is not necessarily suitable for miniaturizing active matrix devices and increasing pixel density. Recently, in addition to direct-view display devices, there has been an increasing demand for ultra-compact display devices or light valve devices that have miniaturized, high-density pixels. Such a microscopic light valve device is used, for example, as a primary image forming surface of a projection type image device, and can be applied as a projection type high-definition television. In order to manufacture such an ultra-small light valve device, it is necessary to form a pixel electrode with dimensions on the micron order and a switch element with dimensions on the submicron order.

However, when using conventional amorphous or polycrystalline silicon thin films, fine semiconductor processing technology (hereinafter referred to as LSI)
It is not possible to form thin gMO8FETs with sub-micron device dimensions using manufacturing techniques (referred to as 100%). For example, in the case of an amorphous silicon thin film, the film formation temperature is about 300'C, so it is only possible to perform high-temperature processing required for LSI manufacturing technology. In addition, in the case of polycrystalline silicon thin films, the size of crystal grains is on the order of a few centimeters, so
This inevitably limits the miniaturization of thin film MO5FETs.

Furthermore, the film forming temperature of a polycrystalline silicon thin film is approximately 600° C., making it impossible to fully apply LSI manufacturing technology that requires high-temperature processing of rooo° C. or higher. As mentioned above, in semiconductor devices for light valve substrates using conventional amorphous or polycrystalline silicon Ha, it is extremely difficult to achieve the same level of integration density and chip size as ordinary semiconductor integrated circuit elements. The problem was that it was difficult.

In view of the above-mentioned problems of the conventional technology, the present invention is directed to a fine and high-density thin film M formed directly using LSI manufacturing technology.
A general object is to provide a semiconductor device for a light valve substrate having a switch element group consisting of O5FETs.

However, when the switch element is miniaturized, its voltage resistance becomes a problem. That is, a relatively high voltage drive signal is applied to each pixel of the light valve device or the active matrix device. Therefore, the switching elements for selectively supplying power to each pixel must also withstand such high voltage drive signals. Therefore, a characteristic object of the present invention is to provide a semiconductor device for a light valve substrate in which MO5FETs for switch elements having a particularly high breakdown voltage structure are integrated in a fine and dense manner.

Means for Solving Problem C] In order to achieve the above-mentioned general and characteristic objects, the semiconductor device for light valve substrate according to the present invention uses a laminated substrate having a special two-phase structure. This laminated substrate has a semiconductor single crystal thin film formed on the surface of an electrically insulating substrate.

This semiconductor single crystal thin film is, for example, a high-quality silicon wafer used in LSI manufacturing technology, which is made thinner by polishing or the like. A pixel electrode group is formed on the surface of the substrate, and a switch element group for selectively supplying power to each pixel electrode is formed in the semiconductor single crystal thin film. The switch element group is formed in an integrated manner and at high density on a semiconductor single crystal thin film to which LSI manufacturing technology can be directly applied. The switch element group is composed of MOSFETs and has a special high voltage structure to withstand relatively high voltage drive signals.

[Action of the invention]

As described above, according to the present invention, an electrically insulating substrate coated with a semiconductor single crystal thin film is used, and the semiconductor single crystal thin film is equivalent to a silicon wafer for LSI manufacturing made of a semiconductor single crystal bulk. It has high quality. Therefore, the pixel electrode group and the switch element group can be formed in a high-density integrated manner on such a semiconductor single-crystal thin film by making full use of LSI manufacturing technology. The resulting semiconductor device chip for light valve substrate has extremely high pixel density and element density, and can constitute an ultra-small and high-definition light valve device, such as an active matrix liquid crystal device.

In addition, the MOSFETs constituting the switch element group have a high breakdown voltage structure and can withstand relatively high voltage drive signals applied to the pixels of the light valve device despite being miniaturized. For example, a MOSFET has a source region and a drain region formed apart from the interface between a substrate and a semiconductor single crystal thin film, and has a voltage-resistant structure that can effectively prevent so-called back channel. There is. Alternatively, the MO5FET has a so-called LDD type breakdown voltage structure comprising a source region and a train region with a low impurity concentration existing at both ends of the channel region, and a source region and a drain region with a high impurity concentration connected to each of these regions. has. Therefore, punch-through, short channel effect, etc. can be effectively prevented. Furthermore, the MO3FET is
It has a butting contact structure that can fix the potential of the semiconductor single crystal thin film through the source region. By fixing the potential of the semiconductor single crystal thin film, the breakdown voltage characteristics of the transistor are improved.

〔Example〕

Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is an enlarged schematic plan view of one pixel portion of a semiconductor device for a light valve substrate. The surface of the electrically insulating substrate is coated with a semiconductor single crystal thin film, such as a silicon single crystal thin film 1. A MOSFET 2 having a high breakdown voltage structure is formed on the surface of the silicon single crystal thin film 1. The M
O3FET2 has a source region S and a drain region. A channel region C is formed between the double head regions S and D. A gate electrode G is overlaid on the channel region C with a gate insulating film interposed therebetween. Further, a pixel electrode 3 defining a pixel is formed on the surface of the substrate. This pixel electrode 3 and the drain region of the high voltage MOSFET 2 are electrically connected to each other via a contact hole 4a. Further, a signal line 5 is formed on the surface of the substrate, and a high voltage MO5FET 2 is connected via a contact hole 4b.
It is electrically connected to the source region S of. Further, a scanning line 6 is formed, a part of which extends to form a gate electrode G.

Next, referring to FIGS. 2 to 4 (B), high voltage MO
A specific configuration example of the 3FET 2 will be explained in detail. FIG. 2 shows an example in which a back channel prevention type high breakdown voltage structure MOSFET 2 is formed. The surface of a transparent electrically refractory substrate, such as a quartz glass substrate 7, is coated with a silicon single crystal thin film 1. This silicon monocrystalline thin Ml is selectively thermally oxidized to form a field oxide film 8 so as to surround the element region.

Since the silicon single crystal thin film 1 is completely thermally oxidized, the element region M 8 is made of substantially transparent silicon dioxide. A source region S and a drain region made of shallow impurity diffusion layers are formed in the surface portion of the silicon single crystal thin film 1 left in the element region. The impurity diffusion depth in this double-headed region does not reach the interface between the substrate 7 and the silicon single crystal thin film 1, and the double-headed regions S and D are separated from this interface. A gate electrode G is formed on the upper side of the channel region C formed between the two head regions with a gate insulating film 9 interposed therebetween. Furthermore, a transparent pixel electrode 3 made of ITO or the like is formed on the surface of the field oxide film 8. One end of this pixel electrode 3 is electrically connected to the drain region via a contact hole 4a. Further, a scanning line 6 is also formed, and is connected to the source region S through the contact hole 4b.
electrically connected to. Finally, the quartz glass substrate 7
is entirely covered with a transparent protective film jO.

In the second example, the protective films 10 are stacked on each other.
Since the pixel electrode 3, field oxide film 8, and quartz glass substrate 7 are transparent, a transmissive pixel can be constructed.

Incidentally, in conventional semiconductor devices for light valve substrates, MOSFETs are formed in silicon amorphous or V films deposited by vacuum evaporation or sputtering, or silicon polycrystalline thin films deposited by chemical vapor deposition. These thin films were extremely thin, and the source and drain regions, which were impurity diffusion layers, reached the interface between the substrate and the thin film, as shown by dotted lines in the figure. Therefore, a so-called back channel is formed at this interface, resulting in a problem of poor pressure resistance. In contrast, in the present invention, since a polished silicon single crystal thin film is laminated on the quartz glass substrate 7, the film thickness can be set freely. Therefore, it is possible to form source and drain regions having shallow junction depths by diffusing impurities only in the surface portion of silicon single crystal thin film 1 having a desired thickness.

In the example shown in FIG. 3, a high voltage MOSFET having a so-called LDD structure is used. As shown in the figure, the surface of the substrate 7 has a thin P-type silicon single crystal. 11 is coated. Here, P type indicates a state in which the impurity concentration is relatively low. This silicon single crystal thin film is selectively oxidized to form a field oxide film 8 surrounding the element region. In the element region, a high voltage MO8FET 2 is formed using LSI manufacturing technology. This MOSFET2 is LDD
At both ends of the channel region C, an N-type source region S1 with a low impurity concentration and an N-type drain region D2 with a low impurity concentration are arranged. Furthermore, the source area S
An N+ type source region S2 with a high impurity concentration is formed in connection with the N+ type source region S2.

On the other hand, N with a high impurity concentration is connected to the drain region D1.
A type drain region D2 is formed.

Therefore, MOSFET 2 has an N-type LDD structure. In the LDD structure, a source region S1 and a drain region D1 with low impurity concentration are provided at both ends of the channel region C.
There is an intervention. Therefore, the generation of hot carriers can be effectively prevented, and bunch-through and short channel effects, which cause insulation defects, can be effectively suppressed. As a result, the MOS
The pressure resistance of FET2 is significantly improved. Components not particularly mentioned in the explanation of FIG. 3 will be given the same reference numerals as in FIG. 2, and the explanation will be changed.

Next, FIGS. 4(A) and 4(B) show an example of a high voltage MO5FET having a so-called butting contact structure. Figure 4 (^) shows the high voltage MOS F
It is a top view of ET2. As shown in the figure, a source region S is formed on the left side of the element region, and a drain region S is formed on the right side.

A gate electrode G is provided in the center of the source region with a gate insulating film interposed therebetween. The channel region C directly under the gate electrode consists of a P type impurity diffusion layer. Further, the drain region consists of an N type impurity diffusion layer. Further, the source region S is also made of an N type impurity diffusion layer. however,
In this example, inside the north region S, N+
The type impurity diffusion layer is divided into left and right sides by P+ type impurity diffusion layers. The contact hole 4b opened in the source region S is arranged so as to expose both the N+ type impurity diffusion layer and the P+ type impurity diffusion layer. The source region S is electrically connected to a scanning line 6 (not shown) via this contact hole 4b. Therefore, the N+ type impurity diffusion layer and the P'' type impurity diffusion layer are held at the same potential.

On the other hand, a contact hole 4a is opened in the drain region to establish electrical continuity with a pixel electrode (not shown).

FIG. 4(B) is a cross-sectional view of the transistor shown in FIG. 4(A) taken along the longitudinal direction of the channel region C.

Components that are the same as those of the transistor shown in FIG. 2 are given the same reference numerals. As shown in the figure, the source region S includes a P+ type impurity diffusion layer in addition to an N+ type impurity diffusion layer. Therefore, the P'' type silicon single crystal thin film 1 left in the element region and the P+ type impurity diffusion layer formed inside this source region S have the same conductivity type, and the ohmic Therefore, the P type silicon single crystal thin film 1 is held at the same potential as the source region S.

Therefore, the generation of hot carriers due to potential fluctuations can be prevented, and punch-through and short channel effects that cause insulation deterioration can be effectively suppressed.

Next, referring to FIG. 5, an active matrix liquid crystal display device constructed using the semiconductor device for light valve substrate according to the present invention will be described. As shown in the figure, a light valve device or an active matrix liquid crystal display device is provided between a semiconductor device 11 for a light valve substrate, a counter substrate I2 disposed opposite to the semiconductor device 11, and a counter substrate I2 between the semiconductor device 11 and the counter substrate 12. It is composed of an electro-optic material layer, ie, a liquid crystal layer 13, arranged therein. The semiconductor device 1 is formed with a plurality of pixel electrodes 3 that define pixels, and a switch element, ie, a high voltage MOSFET 2, for driving the pixel electrodes 3 in accordance with a predetermined signal. The plurality of pixel electrodes 3 are arranged in rows and columns to form a matrix. Moreover, MO5FET2 is also arranged so as to correspond to each pixel electrode.

As described above, the semiconductor device 11 has a laminated structure consisting of the quartz glass substrate 7 and the silicon single crystal thin film 1. In addition, a polarizing plate 2 is adhered to the back side of the quartz glass substrate 7. Further, the surface side thereof is coated with an alignment film I4 for aligning the liquid crystal layer 13. The drain electrode of each MOSFET 2 is connected to the corresponding pixel electrode 3, the gate electrode is connected to the scanning line 6, and the source electrode is connected to the signal line 5. X drivers 15 are formed roughly in an integrated manner on the silicon single crystal thin film 1, and are connected to the column-shaped signal lines 5. Furthermore, the Y driver 16 is also formed integrally and is connected to the row scanning lines 6. According to the present invention, since a high-quality silicon single crystal thin film is used, in addition to the switch element group, peripheral circuits such as the above-mentioned X driver area 5 and Y driver 18 can be simultaneously integrated at high density using LSI manufacturing technology. things are possible.

Therefore, the number of external connection terminals of this semiconductor device can be significantly reduced, contributing to reduction in chip size. The counter substrate 12 includes a glass carrier 17, a polarizing plate 18 bonded to the outer surface of the glass carrier 17, a counter electrode 19 formed on the inner surface of the glass carrier I7, and an electrode coated on the surface of the counter electrode 19. It has a laminated structure consisting of a light film 2o.

For example, a nematic liquid crystal material is used as the liquid crystal layer 13 constituting the electro-optic material layer. Nematic liquid crystal molecules have the property that their long axes are easily aligned.

The orientation of liquid crystal molecules is determined by the flat semiconductor device opening and the counter substrate 12.
is controlled by a pair of alignment films 14 and 20 formed on the inner surface of the.

Next, the operation of the active matrix device shown in FIG. 5 will be briefly explained. As described above, the gate electrodes of the individual switch element transistors 2 are connected to the scanning line 6, and a scanning signal is applied by the Y driver 16 to control conduction and cut-off of the individual transistors 2 line-sequentially. The image signal output from the X driver 15 is applied via the signal line 5 to the selected transistor 2 which is in a conductive state. The applied image signal is transmitted to the corresponding pixel electrode 3, and the liquid crystal layer 1 existing between the pixel electrode and the counter electrode 20
3 is partially excited. As a result, the orientation of the liquid crystal layer 13 is partially changed, and the optical rotation of the incident light is lost. This loss of optical rotation is detected by a pair of polarizing plates [8 and 2] and observed as a change in intensity. The image signal applied at this time has a value of several volts to several tens of volts in order to sufficiently excite the liquid crystal layer 13. Note that the magnitude of this voltage is appropriately determined depending on the voltage response characteristics of the electro-optical material used.

Even if a relatively high voltage image signal is applied, each switch transistor 2 will not suffer dielectric breakdown because it has a high breakdown voltage characteristic as described above. Therefore, a light valve device constructed using the semiconductor device according to the present invention has extremely high reliability. Note that when a pixel is not selected, the switch transistor 2 becomes non-conductive and maintains the image signal written to the corresponding pixel electrode as a charge. The on/off current ratio is commonly used to express the high speed switching performance of transistor 2. The current ratio required for liquid crystal operation can be easily determined from the write time and retention time.

For example, in the case of an image signal or a television signal, 1
900 of the image signal during approximately GOflsec of scan line period.
You must write more than ゜. On the other hand, more than 9,000 charges must be held for approximately 16 m5ec, which is one cycle period. As a result, the current ratio needs to be five orders of magnitude or more. Regarding the second point, in the present invention, high withstand voltage ~
Since the 105FET is formed in a silicon single crystal thin film with extremely high charge mobility, it is possible to secure an on/off ratio of 6 orders of magnitude or more.

Therefore, an active matrix device having extremely high-speed signal response can be obtained. In addition, by utilizing the high mobility characteristics of the silicon single crystal thin film, the X driver 1
It becomes possible to form the peripheral circuits including the driver 5 and the Y driver 16 in the same silicon single crystal thin film.

Next, a method of manufacturing a semiconductor device for a light valve substrate in which MOSFETs having various high breakdown voltage structures shown in FIGS. 2 to 4B are integrally formed will be described in detail. First, the 6th
A method of manufacturing a semiconductor device for a light valve substrate including the hack channel prevention type high breakdown voltage MO5FET transistor shown in FIG. 2 will be described with reference to FIGS. 6(A) to 6(F). In the step shown in FIG. 6(A), a quartz glass substrate 61 and a single crystal silicon semiconductor substrate 62 are prepared.

It is preferable to use a high quality silicon wafer used for LSI manufacturing as the single crystal silicon semiconductor substrate 62, and its crystal orientation has uniformity in the range of <ioo>o, o±1.0, and the single crystal Lattice defect density is 500/cd
It is as follows. First, the surfaces of the prepared quartz glass substrate B1 and the silicon wafer 62 are precisely smoothed. Subsequently, the quartz glass substrate and the silicon wafer are thermocompression bonded to each other by overlapping and heating the smoothed surfaces. Through this thermocompression bonding process, the quartz glass substrate 61
and silicon wafer 62 are firmly fixed to each other.

Subsequently, in the step shown in FIG. 6(B), the surface of the silicon wafer is polished. As a result, a polished silicon single crystal thin film 63 is formed on the surface of the quartz glass substrate 61 to a desired thickness (for example, several nodes). Incidentally, in order to reduce the thickness of the silicon wafer, etching treatment may be used instead of polishing treatment. The silicon single-crystal thin film 63 obtained in this way maintains the quality of a silicon wafer and is therefore able to obtain a semiconductor substrate material which is extremely excellent in terms of uniformity of crystal orientation and lattice defect density.

By the way, various semiconductor device substrates having a laminated structure consisting of an electrically insulating carrier layer and a silicon single-crystal thin film layer are conventionally known. This is what is called a Sol substrate. For example, an SOI substrate is made by depositing a silicon polycrystalline thin film on the surface of a carrier substrate made of an insulating material using a chemical vapor deposition method, etc., and then applying heat treatment such as laser beam irradiation to recrystallize the polycrystalline thin film to form a single layer. It was obtained by converting it to a crystal structure. However, in general, single crystals obtained by recrystallization of polycrystals do not necessarily have --like crystal orientation and have a large lattice defect density. For these reasons, it is possible to use LSI as well as high-quality single-crystal silicon wafers for Sol substrates manufactured by conventional methods.
The first step in applying manufacturing technology is difficult.

Next, in the step shown in FIG. 6(C), selective thermal oxidation of the silicon crystal thin film 63 is performed. This thermal oxidation is F
This is done through a mask that covers only the device region where the viO5FET is to be formed, and a field oxide film 64 is formed to surround the device region.

This field oxide film 64 is obtained by completely thermally oxidizing the total thickness of the silicon single crystal thin film 63, and is optically transparent and forms an ideal device region M.

Subsequently, in the step shown in FIG. 6(D), the surface of the silicon single crystal thin film 63 remaining only in the element region is thermally oxidized again. As a result, a gate insulating film 65 having an extremely thin film thickness is formed on the surface of the silicon single crystal thin film.

Furthermore, a silicon polycrystalline thin film is deposited on the substrate surface using, for example, chemical vapor deposition. This polycrystalline thin film is etched through a mask processed into a desired pattern to form a gate electrode 66. At this time, a scanning line (not shown) connected to the gate electrode 66 is also formed at the same time.

Furthermore, in the step shown in FIG. 6(E), an impurity introduction process is performed. For example, an ion/man method is used to implant ionized impurities into the silicon (11-crystal thin film 63) through the gate insulating film 65 using the gate electrode 66 as a mask.

At this time, by appropriately adjusting the acceleration energy of the impurity ions and controlling the implantation time, it is possible to limit the diffusion depth of the impurity layer only to the surface portion of the silicon single crystal thin film 63. As a result, the source region 67 and the toluin region 6 have a relatively small junction depth as shown in the figure.
8 is formed. The lower portion of the silicon single crystal thin film 63 is left without ion implantation, and the source region 67 and drain region 68 do not reach the interface between the substrate 61 and the silicon single crystal thin film 63. Therefore, back channels that cause insulation deterioration can be effectively prevented.

Finally, in the step shown in FIG. 6(F), a pixel electrode 69 is laminated on the surface of the field oxide film 64.

One end thereof is electrically connected to the drain region 68 via a contact hole 70a formed in a part of the gate insulating film 65. A signal line 7] is also formed and electrically connected to the source region 67 via a contact hole 70b. Finally, the entire surface of the substrate is covered with a transparent protective film 72 made of PSG or the like.

FIGS. 7(A) to 7(E) show other examples of a method for manufacturing a semiconductor device for a light valve substrate in which bank channel prevention type MOSFET transistors are integrally formed. The impurity adsorption diffusion method is used instead of the ion implantation method used. According to this method, the source region and drain region made of extremely thin impurity diffusion layers can be formed, thereby promoting further miniaturization. In the step shown in FIG. 7(^), a semi-finished product having an element region surrounded by a field oxide film 64 is prepared. This semi-finished product is similar to that manufactured by the steps shown in FIGS. 6(^) to 6(D). Identical components are therefore provided with the same reference numerals. The element region consists of a silicon single crystal thin film 63, on which a gate electrode 66 is formed with a gate insulating film 65 interposed therebetween.

Subsequently, in the step shown in FIG. 7(B), the gate insulating film 65 is removed using the gate electrode 66 as a mask to expose the surface of the silicon single crystal thin film 63. However, in most cases, the surface of the silicon single crystal thin film 63 may still be covered with a natural oxide film of about 30 Å or less. In order to completely remove this natural oxide film, the substrate is heated to about 850° C. or higher in a vacuum or an atmosphere below about IO'Pa.

After stabilizing the atmosphere for several minutes, hydrogen gas of about 1.0'Pa is introduced. This hydrogen removes the natural oxide film left on the surface of the silicon single crystal thin film. R purification is performed. As a result, activated silicon atoms are exposed on the surface.

In the step shown in FIG. 7(C), an impurity adsorption layer 73 is formed on the surface of the activated silicon single crystal thin film 63. This impurity adsorption layer is formed, for example, by supplying a gas containing impurity components to the activated surface while keeping the substrate at a high temperature. Adsorbed: The gas undergoes thermal decomposition and an impurity adsorption layer 73 is deposited on the activated surface. for example,
When forming a P-type impurity adsorption layer, siphorancus containing P-type impurity boron is used. Further, when forming an N-type impurity plate layer, for example, arsine gas containing arsenic or the like is used.

In the step shown in FIG. 7<D), solid phase diffusion is performed using the impurity diffusion layer 73 as a diffusion source, and the silicon single crystal thin film 6
A source region 67 and a drain region 68 are formed on the surface portion of 3. The diffusion depth and diffusion concentration of the impurity diffusion layers constituting the source region 67 and drain region 68 can be freely set by appropriately adjusting the film thickness of the impurity adsorption layer 73 deposited as a diffusion source or the solid phase diffusion treatment temperature. I can do that. For example, it is possible to limit the diffusion depth to about several hundred people from the surface. This diffusion depth is extremely small compared to the value obtained by ion implantation, making it possible to form very thin source and drain regions.

As a result, a back channel prevention structure can be easily realized, and the MOSFE
Refinement of T is further promoted.

Finally, in the step shown in FIG. 7(F), the pixel electrode 69
Then, the signal line 71 is formed by patterning. In this example, since the surfaces of the source region 67 and drain region 68 are not covered with the gate insulating film 65, it is possible to obtain direct electrical continuity through surface contact. After these steps are completed, a transparent protective film 72 is coated over the entire substrate.

Next, referring to FIG. 8(A) to FIG. 8(E), the LD
A method for manufacturing a semiconductor device for a light valve substrate in which high voltage MO5FET transistors having a D structure are integrally formed will be described in detail. In the step shown in FIG. 8(A), the illustrated semi-finished product is prepared.

This semi-finished product is shown in FIGS. 6(A) to 6(D) described above.
) can be obtained by a method similar to that shown in . In this semi-finished product, a field oxide film 82 is formed on the surface of a substrate 81 so as to surround the element region. The element region is constituted by a silicon single crystal thin film 83.

This silicon single crystal thin film 83 is obtained by polishing a silicon wafer. A gate electrode 85 is formed on the silicon single crystal thin film 83 with a gate insulating film 84 interposed therebetween. In this example, a P-type silicon 1μ crystal thin film 83 is used.

In the step shown in FIG. 8(B), N-type impurity ions are implanted. That is, using the gate electrode 85 as a mask, N-type impurity ions with relatively low acceleration energy are implanted through the gate insulating film 84 for a relatively short period of time.

As a result, an extremely shallow N-type source region 86 and an N-type drain region 87 are formed on the surface of the P-type silicon single crystal thin film 83.

In the step shown in FIG. 8C, a silicon dioxide film is deposited over the entire surface using, for example, chemical vapor deposition. It is preferable that the film thickness is approximately the same as that of the gate electrode 85. Subsequently, anisotropic etching is performed to remove the deposited silicon dioxide film.

Since this is anisotropic etching, a sidewall 88 made of etching residue is formed around the gate electrode 85.
is formed. This sidewall 88 is formed to cover the tip portions of the previously formed N~ type source region 86 and drain region 87.

In the step shown in FIG. 8(D), ion implantation of N-type impurities is performed again. This ion implantation is performed for a longer time and with higher acceleration energy than the previous ion implantation.

Using the gate electrode 85 and the sidewall 88 formed around it as a mask, ion implantation is performed through the gate insulator [84] to form an N+ type source region 89 and an N+ type drain region 90. As shown in the figure, immediately below the sidewall 88 is an N type source region 86 and an N type source region 86.
Since only the drain region 87 of the mold remains, the so-called L
A DD structure is formed. This LDD II structure has source and drain regions with low impurity concentration at both ends of the channel region, which prevents the generation of NAND electrons and effectively eliminates punch-through and short channel effects that cause insulation deterioration. It is possible to suppress it.

Finally, in the step shown in FIG. 8(E), the pixel type riA
91 is formed. One end of the pixel electrode 91 is electrically connected to the toluin region 90 through a contact hole opened in the gate insulating film 84 .

A signal line 92 is also formed and electrically connected to the source region 89 via another contact hole.

After these steps are completed, a protective film 93 is coated over the entire surface of the substrate.

Finally, with reference to FIGS. 9(A) to 9(F),
High voltage resistant M with so-called butting contact structure
A method of manufacturing a semiconductor device for a light valve substrate in which O5FET transistors are integrally formed will be described in detail. First, the 9th
In the process shown in Figure (A), a semi-finished product is prepared.

This semi-finished product is manufactured by a method similar to the steps shown in FIGS. 6(A) to 6(C). That is, as shown in the figure, an element region surrounded by a field oxide film 102 is formed on the surface of a substrate 101. This element region is composed of a P-type silicon single crystal thin film 103. This single crystal thin film 103 is formed by adhesion and polishing. FIG. 9(B) is a plan view of the semi-finished product shown in FIG. 9(A). Field l-oxide film 102
The rectangular element area surrounded by is open.

Next, in a step shown in FIG. 9(C), a gate electrode 104 is formed along the width direction of the central portion of the element region. Isn't it shown in the figure that the gate electrode 104 and the portion of the Norikono single crystal 14 film 103 exposed in the element region? ? ] is interposed with a gate insulating film.

In the step shown in FIG. 9(D), selective ion implantation using P-type impurities is performed. This ion implantation is selectively performed only in the center portion in the width direction in the left side portion of the element region to form a P+ type impurity diffusion layer 105. This p-type impurity diffusion layer 105 is
It is in electrical contact with the silicon single crystal thin film of the mold. Therefore, the potential of the P type silicon single crystal thin film can be fixed via the P+ type impurity diffusion layer 105.

In the step shown in FIG. 9E, selective ion implantation using N-type impurities is performed. This ion implantation is P
This is done while avoiding the + type impurity diffusion layer 105. As a result, an N+ type impurity diffusion layer 106 is formed in the left side portion of the element region divided in the longitudinal direction by the gate electrode 104. This N+ type impurity diffusion layer 106 forms a source region. Further, an N+ type impurity diffusion layer 107 is also formed on the right side of the element region. This diffusion layer 107 constitutes a drain region. Although not shown, the surfaces of the source region and the train region are covered with a gate insulating film.

Finally, in the step shown in FIG. 9(F), a partial opening process is performed on the gate insulating film existing on the surface of the source region to form a hole 108. This contact hole 108 is formed by an N+ type impurity diffusion layer 106 and a P
It is formed to cross the + type impurity diffusion layer 105. The source region is electrically connected to a signal line (not shown) through this contact hole 108. So-called batting contact is not formed. That is, the P- type silicon single crystal thin film can be held and fixed at the voltage level supplied to the signal line via the P+ type impurity diffusion layer 105. On the other hand, an opening process is also performed on the gate insulating film existing on the surface of the drain region, and a contact hole 109 is formed.
or formed. A pixel electrode (not shown) is electrically connected to the drain region through this contact hole 109. A cross-sectional structure obtained by cutting the semiconductor device shown in FIG. 9(F) along the longitudinal direction of the element region is shown in FIG. 4(B).

〔Effect of the invention〕

As explained above, according to the present invention, LSI can be applied to a high quality silicon single crystal thin film formed on an insulating substrate.
A semiconductor device for a light valve substrate is obtained by integrally forming a pixel electrode group and a switch element group using manufacturing technology. Therefore, it is possible to obtain a semiconductor device for a light valve substrate having an extremely high pixel density. Another advantage is that the chip size of the semiconductor device according to the present invention can be reduced to the same size as a normal LSI chip.

In particular, since a silicon single-crystal thin film is used, LSI manufacturing technology can be directly applied and miniaturization of switching elements can be promoted. Furthermore, as a characteristic effect of the present invention, the switch element is constructed of an insulated gate field effect transistor with a high withstand voltage structure of This has the effect that it is possible to provide a device.By adopting the second king-resistant structure, further miniaturization of the switching element is promoted.

[Brief explanation of drawings]

Fig. 1 is an enlarged partial bottom view of one pixel portion of a semiconductor device for a light valve substrate, and Fig. 2 is a schematic part of a semiconductor device for a light valve substrate that integrates switching element transistors having a pack channel prevention type withstand voltage structure. 3 is a schematic cross-sectional view of a semiconductor device for a light valve substrate that integrates switch element transistors having an LDD type voltage-resistant structure, and FIG. 4 (A) shows a switch element having a voltage-resistant structure equipped with a butting contact. An enlarged plan view of a transistor, FIG. 4(B) is a schematic partial cross-sectional view of a semiconductor device for a light valve substrate in which switching element transistors having a pressure-resistant structure equipped with a butting contact are integrated, and FIG. 5 is a diagram for a light valve substrate. 6 (A) to 6 (F) are schematic exploded perspective views of an active matrix liquid crystal display device constructed using a semiconductor device. , process diagrams showing a method of manufacturing a semiconductor device for a light valve substrate equipped with a semiconductor device, FIGS. 7(A) to 7(E)
) A process diagram showing an example of another method of manufacturing a soil conductor device for a light valve substrate in which a switching element transistor having a voltage-resistant structure of a high-channel prevention type is formed, FIG. 8(A)
8(E) to 8(E) are process diagrams showing a method for manufacturing a semiconductor device for a light valve substrate equipped with a switch element transistor having an LDD-type breakdown voltage structure, and FIGS. 9(A) to 9
Figure (F) is a process diagram showing a method of manufacturing a semiconductor device for a light valve substrate including a switch element transistor provided with a butting contact. ]...Silicon single crystal thin film 2・High voltage MO8FET 3・Pixel electrode 4a・・Contact hole 4b・Contact hole 5・・Signal line 6・・P scan line 8・Field oxide film 10・・Protective film S - Source chain acid C-channel area 7 - Quartz glass substrate 9 - Gate insulating film G - Gate electrode D - Train chain acid Applicant Seiko Electronics Co., Ltd. Agent

Claims (1)

[Claims] 1. An electrically insulating substrate, a semiconductor single crystal thin film formed on the surface of the substrate, a group of pixel electrodes formed on the substrate, and selective power supply to each pixel electrode. 1. A semiconductor device for a light valve substrate, comprising an insulated gate field effect transistor having a breakdown voltage structure integrally formed on the semiconductor single crystal thin film. 2. The optical device according to claim 1, wherein the insulated gate field effect transistor has a back-channel prevention type breakdown voltage structure comprising a source region and a drain region formed apart from the interface between the substrate and the semiconductor single crystal thin film. Semiconductor device for valve board. 3. The insulated gate field effect transistor is an LDD comprising a source region and a drain region with a low impurity concentration existing at both ends of the channel region, and a source region and a drain region with a high impurity concentration connected to each of these regions. 2. The semiconductor device for a light valve substrate according to claim 1, having a pressure-resistant structure of the type. 4. The insulated gate field effect transistor has a voltage-resistant structure including a butting contact capable of fixing the potential of the semiconductor single crystal thin film through its source region.
A semiconductor device for a light valve substrate according to . 5. A first step of bonding and fixing an electrically insulating substrate and a semiconductor single crystal substrate to each other and then polishing the semiconductor single crystal substrate to form a semiconductor single crystal thin film; and an insulated gate having a voltage-resistant structure on the semiconductor single crystal thin film. A method for manufacturing a semiconductor device for a light valve substrate, comprising: a second step of forming a field effect transistor; and a third step of forming a pixel electrode selectively supplied with power by the transistor on the substrate. 6. The second step includes an activation step for partially activating the surface of the semiconductor single crystal thin film, and an adsorption step for supplying a gas containing impurities to the activated surface to form an impurity adsorption layer. and a diffusion step of performing solid phase diffusion using an impurity adsorption layer as a diffusion source to form a source region and a drain region limited only to the surface portion of the semiconductor single crystal thin film.
A method for manufacturing a semiconductor device for a light valve substrate according to .