JPH04114445A - Semiconductor testing system - Google Patents

Abstract

PURPOSE:To discover an open place on each transfer line in a short time, easily and accurately by a method wherein a semiconductor testing system is provided with an open place detector, which specifies the open place in each transfer line on the basis of the state of the waveform of each reflected signal that a signal inputted in each transfer line is reflected at the open place in each transfer line and is returned. CONSTITUTION:An open place detector 12 is provided with a waveform generating register 14, a variable voltage generating circuit 16 for waveform generation use, a waveform detecting register 18 and a waveform voltage comparison circuit 20 for waveform detection use. The circuit 20 compares the waveforms of reflected signals returned in an inspection of verification of an actual connection with the waveform of reference data being stored in the register 18. In case the waveforms of the reflected signals coincide with the normal waveform signal, the normal waveform signal is sent out to a control device 2 and in case the normal waveform signal coincides with either of open waveform signals, an open place indicating signal is sent out to the device 2 and when the indicating signal is different from any one of the above signals, data on the waveforms of the reflected signals is sent out to the device 2 along with an abnormal signal.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention provides a connection device that has a large number of transmission lines and has a plurality of contact points on each transmission line. It relates to a semiconductor test system that performs a functional test and an electrical characteristic test of a semiconductor device by individually connecting each of a large number of test pins in a semiconductor device to each of a large number of pin terminals in a semiconductor device, and particularly relates to a semiconductor test system that performs a functional test and an electrical characteristic test of a semiconductor device. The present invention relates to a technique for finding open points due to poor contact or disconnection in each transmission line prior to conducting an electrical characteristic test.

<Prior Art> FIG. 5 schematically shows a conventional semiconductor testing system in which a semiconductor testing device and a semiconductor device to be tested are connected via a physical and electrical connection device. be.

The semiconductor test apparatus A0 includes a control device 2, a waveform generator 4, a waveform detector 6, a DC measuring device 8, and a signal generation circuit 10.
It is equipped with A plurality of waveform generators 4, a plurality of waveform detectors 6, and a plurality of DC measuring instruments 8 are each provided, and several hundred signal generation circuits 10 are provided.

The waveform generator 4, the waveform detector 6, and the signal generation circuit 10 are for performing a functional test of the semiconductor device C, and generate various voltage and current waveforms as test data from the waveform generator 4 to generate signals. It is output to the corresponding pin terminal 38a of the semiconductor device C via the circuit 10 and the physical and electrical connection device B (which will be described later), and is output to the corresponding pin terminal 38a of the semiconductor device C in accordance with the voltage/current waveform. 38
A waveform detector 6 detects output data inputted through a device B consisting of a device B and a signal generating circuit 10.

In this case, the control device 2 specifies the test data to be generated by each waveform generator 4 according to the test program of the built-in microcomputer, and also specifies the test data to be generated by the semiconductor device C input from each waveform detector 6. A functional test of the semiconductor device C is performed by analyzing the output data.

The signal generation circuit 10 distributes and supplies test data from each waveform generator 4 to a large number of pin terminals 38a in a semiconductor device C, and also supplies output data from a large number of pin terminals 38a to each waveform detector 6. distribute.

The DC measuring device 8 is used to test the electrical characteristics of the semiconductor device C, and uses the DC signal specified by the control device 2 as test data to test the semiconductor device via the relay in the signal generation circuit 10 and the connecting device B. The output data is outputted to the corresponding pin terminal 38a of the semiconductor device C and inputted via the relay in the device B and the signal generation circuit IO, which are made up of the pin terminal 38a of the semiconductor device C in response to the DC signal. The data is inputted and sent to the control II device 2. The control device 2 tests the electrical characteristics of the semiconductor device C by analyzing the output data.

When a functional test and an electrical characteristic test are performed, the semiconductor device C is placed on an external device 40 such as a blower μ or a handler. A blow μ is used when the semiconductor device C is formed on a wafer, and a handler is used when the semiconductor device WC is packaged.

The connecting device B that physically and electrically connects the semiconductor testing device A0 and the semiconductor device C is configured as follows (when using a profer).

The connection device IB is connected to the first to third connection boards 30.3
2.34 and a probe card 36.

A large number of lands 30a and 30b are formed on both upper and lower surfaces of the first connection board 30 by pattern wiring.

A large number of pogo pins 32a and 32b are provided on both upper and lower surfaces of the second connection board 32, and are movable in and out and biased to protrude. A large number of lands 3 are provided on the upper surface of the third connection board 34.
4a, and a number of pogo pins 34b are provided on the lower surface thereof. A large number of lands 36a are provided on the top surface of the probe card 36, and a large number of probes 36b are provided on the bottom surface.

Semiconductor test equipment A. A test pin 10a consisting of a large number of pogo pins is connected to the output line of each of the large number of signal ordering circuits 10 in , and these test pins t
Oa is provided on the bottom surface of the semiconductor testing device A0. This test pin 10a and the land 30 of the first connection board 30
a forms the first contact P1, and the land 30b of the first connection board 30 and the pogo pin 32a of the second connection board 32
The pogo pin 32b of the second connection board 32 and the land 34a of the third connection board 34 form a third contact P3, and the pogo pin 34b of the third connection board 34 and the probe The land 36a of the card 36 forms a fourth contact P4, and the probe 3 of the probe card 36
The tip of the needle 6b and the pin terminal 38a of the semiconductor device C form a fifth contact P5.

There are as many transmission lines as the number of pin terminals 38a in the semiconductor device C, each having one such first to fifth contacts P1 to P5.

If there is a contact failure in even one of the contact groups of these many transmission lines, or if there is a disconnection in even one of the connection boards 30, 3234 and the probe card 36, the function test of the semiconductor device C by the semiconductor tester A0 and may interfere with electrical characteristic tests.

Second, before testing, use semiconductor test equipment A.

A connection confirmation inspection of the transmission line from the test pin 10a of the semiconductor device C to the pin terminal 38a of the semiconductor device C is performed.

The method of this connection confirmation test will be explained below with reference to FIG.

FIG. 6 shows an equivalent circuit of one line of transmission line in connection device B for one pin terminal 38a.

The first to third connection boards 30, 32.34 and the probe card 36 are respectively represented as equivalent first to fourth line sections 301.32N, 347!361. The DC measuring device 8 is represented as a constant current source 8a and a voltmeter 8b.

This DC measuring device 8 is connected to the first contact P1 via a relay in a signal generating circuit 10, but the signal generating circuit 10 is omitted here.

Since this is a connection confirmation test, an aluminum solid wafer C0 is used instead of the semiconductor device C, and the probe 36b is brought into contact with this. A closed loop is constructed by grounding the voltmeter 8b and the aluminum tower C0, respectively.

A closed-loop inspection system E consisting of the DC measuring device 8, the transmission line, and the aluminum flat wafer C8 is connected to the pin terminal 38.
It is configured by the number of a.

The connection confirmation test is sequentially executed for each test system E in accordance with the test program in the control device 2.

That is, first, a current is caused to flow through a certain test system from the constant current source 8a in the DC measuring device 8, and a detected voltage obtained by the voltmeter 8b is sent to the control device 2.

If the detected voltage is zero, the control device 2 detects the inspection system E.
It is determined that there is no open state (poor contact or disconnection*), and the next inspection of inspection system E is performed.

If the detected voltage is greater than a certain value or infinite, it is determined that an open state has occurred in the inspection system E. In this case, the open portion is found and repaired, and once the repair is completed, the next test system E is tested.

After confirming that there are no open states in all inspection systems, a functional test and an electrical characteristic test are performed.

<Problems to be Solved by the Invention> In the conventional semiconductor test system, the connection confirmation test of the transmission line was performed as described above. 1
11), which of the first to fifth contacts P1 to P5 is causing the poor contact, and
The disconnection occurs in the first to fourth line portions 301, 321, 34
1.3111, it is not directly known where the problem is occurring, so it is tedious to have to find each open point of poor contact or disconnection.

In recent years, the number of pin terminals 38a of semiconductor devices C has tended to increase, and some semiconductor devices have more than 500 pins. In connection confirmation inspections before testing such semiconductor devices,
There are more than 500 transmission lines, and as the number of transmission lines that experience poor contact or disconnection increases, there is a problem in that a great deal of effort and time must be spent to find open locations.

This invention was devised to solve the above-mentioned problems, and its purpose is to provide a semiconductor testing system that can easily and accurately find open points in a short time during contact Vt confirmation inspection. do.

<Means for Solving the Problems> A semiconductor testing system according to the present invention connects a semiconductor testing device to a semiconductor testing device via each transmission line of a connection device having a large number of transmission lines and each transmission line having a plurality of contact points. In a semiconductor test system that performs a functional test and an electrical characteristic test of a semiconductor device by individually connecting each of the many test pins in the semiconductor device to each of the many pin terminals in the semiconductor device, the signal input to each transmission line is The present invention is characterized in that an open point detection device is provided for identifying an open point in each transmission line based on the waveform state of each reflected signal that is reflected at an open point and returns through the same transmission line.

<Function> The semiconductor test system according to the present invention utilizes the fact that the degree of distortion of the waveform of the reflected signal changes depending on the distance from the input end of the test input signal to the open point,
The open point detection device automatically identifies the open point based on the degree of distortion of this reflected signal.

<Example> Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 schematically shows a semiconductor test system according to an embodiment of the present invention, which connects a semiconductor test device and a semiconductor device to be tested through a physical and electrical connection device. be.

The semiconductor testing apparatus A1 of this embodiment, like the conventional semiconductor testing apparatus FAa, includes a control device 2 for controlling the entire apparatus A1, and a plurality of waveform generators for controlling the functional test of the semiconductor device C. 4. It is equipped with a waveform detector 6, a large number of signal generation circuits 10, and a plurality of DC measuring instruments 8 for conducting electrical characteristic tests and connection confirmation tests of the semiconductor device C, and as a new component, The present invention includes an open point detection device 12 that detects an open point when an open state (poor contact or disconnection) occurs in a transmission line to be inspected for contact Vt confirmation.

The relationship between the waveform generator 4, waveform detector 6, and DC measuring device 8 and the control device 2 and signal generation circuit 10, as well as the relationship between the signal generation circuit 10 and the connection device B, are the same as in the conventional example. The explanation will be omitted. The specific structure of the connecting device B is also the same as that of the conventional example, so it is simply shown as a block.

The open point detection device 12 is bidirectionally connected to the control device 2 and bidirectionally connected to the connection device B via a relay in the signal generation circuit 10.

When it is determined that an open state (poor contact or disconnection) exists in the transmission line where the control bag W2 is located based on the detection results from the open point detection device 12 in the connection confirmation inspection for all transmission lines, The control device 2 is
The open point detection device 12 is connected to the transmission line in the open state via a relay in the signal generating circuit 10.

FIG. 2 shows the block configuration of the open point detection device 12 and the connection state between the open point detection device 12 and the transmission line in a connection confirmation test.

The transmission line is connected to connection device B as explained in Fig. 6.
The first to third connection boards 30.32.34 in
and first to fourth line portions 301.32L 347! equivalent to the probe card 36! It consists of 361.

P1 to P5 will be explained again with reference to FIG. 5. Pl is the first contact between the test pin 10a of the semiconductor test device A and the land 30a of the first connection board 30, The second contact point (the first
and the second track section 301.321), P3, the pogo pin 32b of the second and third connection board 32.34
and Land 34. P4 is the third contact between the third connection board 34 and the pogo pin 34b of the probe card 36 and the land 36a (between the second and third line portions 32L 341). 3 and the fourth line portion 341.36ji), P5 is the probe 36b
The fifth contact point between the tip of the needle and the aluminum stylus bar C0 is shown.

The open point detection device 12 includes a waveform generation register 14, a variable voltage generation circuit for waveform generation (drive circuit) 16, a waveform detection register 18, and a waveform voltage comparison circuit for waveform detection (comparator circuit) 20. .

The waveform generation register 14 stores input waveform data sent from the control device 2 for generating a step-like input waveform signal SIN as shown in FIG. 3(a). The waveform generation variable voltage ordering circuit 1G generates a corresponding input waveform signal 5i11 based on input waveform data from the waveform generation register 14 and outputs it to the transmission line.

The human-powered waveform signal SIN outputted from the variable voltage generation circuit 16 for waveform generation propagates along the transmission line, and is reflected back at the aluminum bow bar C9 or an open point due to poor contact or disconnection.

When the impedance of the variable voltage generation circuit 16 for waveform generation and the impedance of the transmission line are set equal, the waveform of the reflected signal has a level of 1/2 of the wave height value, as shown in FIG. 3(b) and below. It becomes a staircase waveform with a flat part.

The time width of the flat portion is proportional to the round trip of the signal, that is, twice the distance from the output terminal of the variable voltage generation circuit 16 for waveform generation to the reflection point.

Therefore, through preliminary experiments, we determined the data of the reflected waveform in a normal state with no open state and the data of each reflected waveform when the first to fifth contacts P1 to P5 are individually opened. These waveform data are previously measured and sent to the waveform detection register 1 through the control device 2.
8! Leave the door varnished.

In addition, in FIG. 3 (bT indicates the normal waveform signal S NoM,
FIGS. 3(c) to 3(g) respectively show open waveform signals SAIINI-SAlN5 when the first to fifth contacts PI-P5 are in the open state.

The data of these normal waveform signals S No) I and the data of each open waveform signal 5AIIN+ to SAllN5 are stored in advance in the waveform detection register 18 as reference data.

The waveform voltage comparison circuit 20 for waveform detection compares the waveform of the reflected signal returned during the actual connection confirmation test with the waveform of the reference data stored in the waveform detection register 18, and determines the normal waveform signal 5N (I). If they match, a normal signal is sent to the control device 2, and an open waveform signal SAM is sent to the control device 2.
□~S If it matches any of AllN5, it sends an open point instruction signal indicating which one it matches to the control device 2, and if it differs from any of the above, it sends the reflected signal along with the abnormal signal. It is configured to send waveform data to the control device 2.

Next, the operation of the connection confirmation test by the semiconductor test system according to this embodiment will be explained with reference to the flowchart of FIG.

In step S2, the DC measuring device 8 is controlled to test whether all transmission lines are open or shorted. In step S4, it is determined whether there is an open transmission line, and if all the transmission lines are in a normal state, the connection confirmation inspection operation is finished,
The process proceeds to a functional test and an electrical characteristic test of the semiconductor device C.

When it is determined in step S4 that there is an open transmission line, the process proceeds to step S6, where the open transmission line is extracted, and in step S8, the open transmission line is extracted. An open point detection device 12 is connected to the open point detection device 12 via a relay in the signal generation circuit 10.

Next, in step SIO, the open location detection device 12
to detect open points.

That is, based on the waveform signal data from the waveform generation register 14, the variable voltage generation circuit 16 for waveform generation generates the signal as shown in FIG.
The input waveform signal SIN shown in a) is generated and outputted to the open transmission line, and the reflected signal from the open point is detected by the waveform voltage comparison circuit 20 for waveform detection.

In the next steps 312-320, the open waveform signals S□8-S09. which are stored in the waveform detection register 18 in the waveform voltage comparison circuit 20 for waveform detection. The waveform data of the detected waveform signal is sequentially compared with the waveform data of the detected waveform signal.

In step S12, the detected waveform data and the first contact point P1 are
Compare the open waveform data (SAllN+) with
If they match, the process proceeds to step S22, where a message is output to the effect that the open point is the first contact P1, and if they do not match, the process proceeds to step S14.

In step S14, the detected waveform data and the second contact point P2 are
The open waveform data (S08□) at step S08 are compared, and if they match, the process advances to step S24, where it is determined that the open point is the second contact P2.

If there is no match, the process advances to step 816.

In step S16, the detected waveform data and the third contact point P3 are
Compare with the open waveform data (S AlN5) at
If they match, the process proceeds to step S26, where a message is output to the effect that the open point is the third contact P3, and if they do not match, the process proceeds to step S18.

In step S18, the detected waveform data and the fourth contact point P4 are
Compare the open waveform data (SAllN4) with
If they match, the process proceeds to step 328, where a message is output to the effect that the open point is the fourth contact P4, and if they do not match, the process proceeds to step S20.

In step S20, the detected waveform data and the fifth contact point P5 are
Compare the open waveform data (SAIINS) with
If they match, the process proceeds to step 530, where a message is output to the effect that the open point is the fifth contact P5, and if they do not match, the process proceeds to step S32.

The detected waveform data is open waveform data (SAI111~
S AllN5) does not match any of the contacts P1 to P5 (poor contact), it means that the line portions 301.32E and 341.361 are open (broken), but in this case, In step S32, the distance to the open point is calculated from the difference between the flat portions of the waveform data of the normal waveform signal SNOH and the detected waveform data, and in step S34, the length to the open point is output as a message.

Then, steps 322 to 330 or step S34
Next, the process advances to step S36 and enters an idling state.

In this state, the operator repairs the open area based on the message output, and after the repair is completed, restarts the system.

If it is determined in step 338 that a restart has been commanded, the process returns to step S2 and it is determined whether the open point has been repaired correctly. If the repair is correct, the above-mentioned After identifying the open location in the same way as above, repair is performed, and after confirming that the repair has been performed correctly, the same process is repeated for the next open transmission line.

Then, when all transmission lines are no longer open, all operations are completed and the process moves on to the next process of functional testing and electrical characteristic testing.

As described above, even though there are a large number of transmission lines and each transmission line has multiple or unspecified open locations, it is easy to accurately identify open locations in a short time. You can let them know.

<Effects of the Invention> As described above, according to the present invention, the degree of distortion of the waveform of a reflected signal from an open point changes depending on the distance from the input end of the inspection input signal to the open point. Since we have provided an open point detection device that automatically identifies open points based on the degree of distortion of the reflected signal, we can easily identify each of the many test pins in the semiconductor test equipment and each of the many pin terminals in the semiconductor device. Even if there are a large number of transmission lines that are individually connected, the open points can be easily and accurately identified in a short period of time during a connection confirmation test.

[Brief explanation of the drawing]

Figures 1 to 4 relate to one embodiment of the present invention;
The figure is a schematic configuration diagram of a semiconductor test system in which a semiconductor test device and a semiconductor device are connected via a connection device.
The figure is a circuit diagram showing an open point detection device and a transmission line,
FIG. 3 is a waveform diagram for explaining the operation, and FIG. 4 is a flow chart for explaining the operation. FIG. 5 is a schematic configuration diagram of a semiconductor testing system according to a conventional example, and FIG. 6 is an explanatory diagram of a connection confirmation test in the conventional example. A1 is a semiconductor test device, B is a connection device, C is a semiconductor device, D is a transmission line, 2 is a control device, 4 is a waveform generator, 6 is a waveform detector, 8 is a DC measuring device, 10 is a signal generation circuit, l
oa is a test pin in the semiconductor test equipment, 12 is an open point detection device, 14 is a waveform generation register, 16 is a variable voltage generation circuit for waveform generation, 18 is a waveform detection register, 2
0 is a waveform voltage comparison circuit for waveform detection, 301 to 36n are line parts, P1 to P5 are contacts, 36b is a probe, 38a
is a pin terminal in a semiconductor device. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) Each of the many test pins in the semiconductor test equipment and the many pin terminals in the semiconductor device are connected to each of the many test pins in the semiconductor test equipment through each of the transmission lines of the connection device which has many transmission lines and has a plurality of contact points on each transmission line. In a semiconductor test system that performs functional tests and electrical characteristic tests of semiconductor devices by individually connecting each transmission line, a signal input to each transmission line is reflected at an open point, and each transmission line returns through the same transmission line. A semiconductor testing system characterized by being provided with an open point detection device that identifies open points in each transmission line based on the waveform state of a reflected signal.