JPH0411355A - Floppy disk device - Google Patents

Floppy disk device

Info

Publication number
JPH0411355A
JPH0411355A JP11361490A JP11361490A JPH0411355A JP H0411355 A JPH0411355 A JP H0411355A JP 11361490 A JP11361490 A JP 11361490A JP 11361490 A JP11361490 A JP 11361490A JP H0411355 A JPH0411355 A JP H0411355A
Authority
JP
Japan
Prior art keywords
signal
floppy disk
disk device
mode
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11361490A
Other languages
Japanese (ja)
Other versions
JP2569894B2 (en
Inventor
Yoshiyuki Soejima
副島　義幸
Yoichi Murakami
洋一 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2113614A priority Critical patent/JP2569894B2/en
Publication of JPH0411355A publication Critical patent/JPH0411355A/en
Application granted granted Critical
Publication of JP2569894B2 publication Critical patent/JP2569894B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the burden of the amount of hardware of a host system by detecting mode switching by a signal from the external and generating a reset signal to a CPU by this detection signal. CONSTITUTION:When a 10M medium is inserted to a floppy disk device operated in the 1.6M mode, the device discriminates the 10M mode in accordance with a detection hole 3 of the inserted medium and is switched to the 10M mode. By this mode switching, a signal 10 indicating that the mode is switched is sent to a reset signal output circuit 2 from a mode switching detection circuit 1. This signal 10 is received to send a reset signal 11 to a CPU 3 of the floppy disk device from the reset signal output circuit 2, and the CPU is reset. Thus, the burden of the amount of hardware of the host system is eliminated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、フロッピィディスク装置に関し、特に２つ以
上のモードを持ち、必要に応じてモードを切りかえ、装
置を制御するＣＰＵを有しているフロッピィディスク装
置に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a floppy disk device, and particularly has a CPU that has two or more modes and controls the device by switching the mode as necessary. Related to floppy disk devices.

口従来の技術〕 従来、この種のフロッピィディスク装置は、ＣＰＵが暴
走した場合ＣＰＵをリセットするために、ホストシステ
ム側からフロッピィディスク装置に信号を送ってＣＰＵ
をリセットしていたかまたは、電源監視回路等を具備す
ることにより電源の０Ｎ１０ＦＦを行うことでリセット
信号を発生させていた。[Background Art] Conventionally, in this type of floppy disk device, in order to reset the CPU when the CPU goes out of control, a signal is sent from the host system side to the floppy disk device to reset the CPU.
Or, by providing a power supply monitoring circuit or the like, a reset signal was generated by performing 0N10FF of the power supply.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この従来のフロッピィディスク装置では、ＣＰＵをリセ
ットするために、ホストシステムからフロッピィディス
ク装置に信号を送るためインターフェイスのビン１本を
専有する必要があった。In this conventional floppy disk device, in order to reset the CPU, it was necessary to exclusively use one interface bin in order to send a signal from the host system to the floppy disk device.

あるいは、フロッピィディスク装置のＣＰＵにリセット
をかけるために電源の０Ｎ１０ＦＦを行うためにはホス
トシステムをもリセットしなくてはならず、ホストシス
テムのデータが消えてしまうという問題点があった。Alternatively, in order to perform a 0N10FF operation to reset the CPU of the floppy disk device, the host system must also be reset, resulting in the problem that data in the host system will be erased.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のフロッピィディスク装置は、モード切り替え信
号を受け、２種類以上の媒体に、書き込み補正制御また
は読み出し補正制御またはその他の制御を切り替えられ
、かつＦＤＤの制御なＣＰＵに依り行うフロッピィディ
スク装置において、外部からの信号により、モードが切
り替わったかを検出するモード切り替え検出回路と、前
記モード切り替え検出回路からの信号に依りＣＰＵに対
してリセット信号を発生するリセット信号発生回路とを
具備したことを特徴としている。The floppy disk device of the present invention is a floppy disk device in which write correction control, read correction control, or other control can be switched between two or more types of media in response to a mode switching signal, and the FDD is controlled by a CPU. It is characterized by comprising a mode switching detection circuit that detects whether the mode has been switched based on an external signal, and a reset signal generation circuit that generates a reset signal to the CPU based on the signal from the mode switching detection circuit. There is.

または、前記モード切り替え検出回路を内部からの信号
によりモードが切り替わったかを検出するようにしてい
る。Alternatively, the mode switching detection circuit detects whether the mode has been switched by a signal from inside.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第一図は、本発明の第１の実施例のブロック図である。FIG. 1 is a block diagram of a first embodiment of the present invention.

例えば、１，６Ｍモードで動作していたフロッピィディ
スク装置にＩＯＭの媒体を挿入した場合、装置は挿入さ
れた媒体の検出孔３から判断して１０Ｍモードに切り替
わる。モードが切り替わった事によりモード切り替え検
出回路１よりリセット信号出力回路２にモードが切り替
わった事を示す信号１０が送られる。前記信号１０を受
はリセット信号出力回路２からフロッピィディスク装置
のＣＰＵ３にリセット信号１１が送られて、ＣＰＵがリ
セットされる。次に、第２の実施例について説明する。For example, when an IOM medium is inserted into a floppy disk device operating in 1.6M mode, the device switches to 10M mode based on the detection hole 3 of the inserted medium. When the mode is switched, a signal 10 indicating that the mode has been switched is sent from the mode switch detection circuit 1 to the reset signal output circuit 2. Upon receiving the signal 10, a reset signal 11 is sent from the reset signal output circuit 2 to the CPU 3 of the floppy disk device, and the CPU is reset. Next, a second example will be described.

第二図を参照すると例えばホストシステムが、ＦＤＤが
暴走していると判断した場合、ホストシステム側７はフ
ロッピィディスク装置へ、モードを切り替える信号８を
送出する。Referring to FIG. 2, for example, when the host system determines that the FDD is out of control, the host system side 7 sends a mode switching signal 8 to the floppy disk device.

前記信号を受はモード切り替え検出回路】よりリセット
信号圧力回路２にモードが切り替わった事を示す信号１
０が送られる。前記信号１０を受はリセット信号出力回
路２からフロッピィディスク装置のＣＰＵ３にリセット
信号１１が送れられてＣＰＵがリセットされる。The signal received by the mode switching detection circuit is the reset signal pressure circuit 2, which sends a signal 1 indicating that the mode has been switched.
0 is sent. Upon receiving the signal 10, a reset signal 11 is sent from the reset signal output circuit 2 to the CPU 3 of the floppy disk device, and the CPU is reset.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に、本発明はＣＰＵの暴走に対して、特
にリセット信号線を設けることなく、ＦＤＤのＣＰＵを
リセットできるため、ホストシステムのリードウェア量
に負担を掛けない、また（請求項２項によれば）ホスト
システムよりリセットが行なえない場合でも、ＦＤＤ単
体にてＣＰＵのリセットが行なえるため、ホスト側のソ
フトウェア負担を軽減し、かつ高信頼性を維持したＦＤ
Ｄを提供できる効果がある。As explained above, the present invention can reset the CPU of the FDD in response to a runaway of the CPU without particularly providing a reset signal line. (According to Section 1), even if the host system cannot perform a reset, the CPU can be reset on the FDD alone, reducing the software burden on the host side and maintaining high reliability.
It has the effect of providing D.

１・・・・・・モード切り替え検出回路、２・・・・リ
セット信号発生回路、３・・・・・・ＣＰＵ、４・・・
・・・媒体、５・・・・・・ｔｌＬ　　６・・・・・・
センサー　７・・・・・・ホストシステム、８・・・・
・・モードを切り替える信号、９・・・・・センサーか
らの信号、ｌＯ・・・・・・モードが切り替わった事を
示す信号、１１・・・・・・ＣＰＵをリセットする信号
。1...Mode switching detection circuit, 2...Reset signal generation circuit, 3...CPU, 4...
...medium, 5...tlL 6...
Sensor 7...Host system, 8...
... Signal to switch the mode, 9... Signal from the sensor, lO... Signal indicating that the mode has been switched, 11... Signal to reset the CPU.

代理人　弁理士　　内　原　　　晋Agent: Patent Attorney Susumu Uchihara

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の第１の実施例のブロック図、第２図
は、本発明第２の実施例のブロック図である。FIG. 1 is a block diagram of a first embodiment of the invention, and FIG. 2 is a block diagram of a second embodiment of the invention.

Claims (2)

【特許請求の範囲】[Claims] （１）２種類以上の媒体を外部からのモード切り替え信
号に基づいて制御を切り換えて使用するフロッピィディ
スク装置において、 前記モード切り替え信号を検出するモード切り替え検出
回路と、前記モード切り替え検出回路からの信号に基づ
いてフロッピィディスク装置の制御を行なうＣＰＵに対
してリセット信号を発生するリセット信号発生回路とを
具備したことを特徴とするフロッピィディスク装置。(1) In a floppy disk device that uses two or more types of media by switching control based on an external mode switching signal, a mode switching detection circuit that detects the mode switching signal and a signal from the mode switching detection circuit are provided. A floppy disk device comprising: a reset signal generation circuit that generates a reset signal to a CPU that controls the floppy disk device based on the following. （２）２種類以上の媒体を、セットされた媒体から判断
するモード判別手段から出力するモード切り替え信号に
基づいて制御を切り換えて使用するフロッピィディスク
装置において、 前記モード切り替え信号に応答してフロッピィディスク
装置の制御を行なうＣＰＵをリセットするリセット信号
発生回路を有することを特徴とするフロッピィディスク
装置。(2) In a floppy disk device that uses two or more types of media by switching control based on a mode switching signal output from a mode determining means that determines based on the set medium, the floppy disk is switched in response to the mode switching signal. A floppy disk device characterized by having a reset signal generation circuit for resetting a CPU that controls the device.
JP2113614A 1990-04-27 1990-04-27 Floppy disk device Expired - Fee Related JP2569894B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2113614A JP2569894B2 (en) 1990-04-27 1990-04-27 Floppy disk device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2113614A JP2569894B2 (en) 1990-04-27 1990-04-27 Floppy disk device

Publications (2)

Publication Number Publication Date
JPH0411355A true JPH0411355A (en) 1992-01-16
JP2569894B2 JP2569894B2 (en) 1997-01-08

Family

ID=14616681

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2113614A Expired - Fee Related JP2569894B2 (en) 1990-04-27 1990-04-27 Floppy disk device

Country Status (1)

Country Link
JP (1) JP2569894B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59185069A (en) * 1983-04-04 1984-10-20 Mitsubishi Electric Corp Recording medium read control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59185069A (en) * 1983-04-04 1984-10-20 Mitsubishi Electric Corp Recording medium read control system

Also Published As

Publication number Publication date
JP2569894B2 (en) 1997-01-08

Similar Documents

Publication Publication Date Title
KR960009756A (en) Automatic turn off / on device for error correction
KR880011652A (en) Computer systems
KR970016972A (en) Information processing system
JPH0411355A (en) Floppy disk device
JP2000039935A (en) Computer system
WO2004100003A3 (en) Method and apparatus for controlling an external device by remapping keys on a user input device
JP3288114B2 (en) Microcomputer
JP2658911B2 (en) Floppy disk unit
KR100240110B1 (en) Operating method and apparatus for floppy disk driver
JPH05204497A (en) Peripheral device remote-controlled on/off of power source
JPS5827219A (en) Feeding device
JPH11112721A (en) Device and method for controlling switch in scanner device
JPH02157952A (en) Storage device
KR970064288A (en) An error detection method of an auxiliary memory device in an electronic switching system
JPS63113996A (en) Holder device for magnetic bubble memory cassette
JP2000090043A (en) Peripheral equipment detecting method of computer
JPH07334279A (en) Scsi device
JPH1124805A (en) Scsi adapter
JPH0566907A (en) Device number display system for external storage device
JPH01280817A (en) Controller for external power supply state detecting i/o equipment
JPH0368017A (en) Error processor
JPH0690184B2 (en) Input state memory circuit using relay
JPH0214461A (en) Magnetic disk protection system
JPH0451308A (en) Keyboard
JPS6129922A (en) Power control system

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071024

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081024

Year of fee payment: 12

LAPS Cancellation because of no payment of annual fees