JPH04108237A - Count control type multiplex communication system - Google Patents

Abstract

PURPOSE:To reduce an access delay time and to set its maximum value by identifying its own transmission time slot and sending an idle pulse through a transmission time slot. CONSTITUTION:A synchronizing pulse Fx from a control node X is always acquired and an internal clock is established based thereon. Then a packet P or an idle pulse I in succession to the synchronizing pulse Fx is detected and the sum Cs is counted. Then a standby time slot number is obtained by using a sequence number (n) of its own terminal equipment and the sum Cs to obtain a standby time slot number, and when its own terminal equipment node is a terminal equipment node in the standby state having a transmission request, a data packet P is sent through the time slot and when the node is in an idle state not having a transmission request, the idle pulse I is sent. Thus, the access delay time is reduced, the setting of the maximum value is attained and an impartial access characteristic independently of the position of the terminal equipment node is realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is used in a local area network (hereinafter referred to as LAN) for mutual communication between computers and terminals. It relates to technology that improves communication control between the nodes (interfaces between computers/terminals and transmission paths) that are its constituent elements.

LAN topologies include ring type (no control node), loop type (with control node), and bus type. As connection methods between transmission lines and nodes constituting a LAN, there are two methods: an insertion method in which a node is inserted into a transmission path, and a branching method in which a node is branched from a transmission path. Please refer to FIG. 9 for an example of the interrupt method and the branch method. There are also an asynchronous method in which burst pulses are transmitted on a transmission path, and a synchronous method in which periodic frame pulses are transmitted and the pulses are transmitted in a specific time slot (time slot) on a frame determined by the frame pulses.

In the present invention, when periodic frame pulses are used, it is a synchronous method because it is essentially suitable for transmitting synchronous information (circuit-switched information such as voice), but it is a synchronous method when using periodic frame pulses. Since it has a flexible access function, it is also suitable for transmitting asynchronous information (packet-type information such as data). In other words, the integration of synchronous information (V: Voice) and asynchronous information (D: Data)
ation) transmission (IVD function:
This is a method that can be used for on-of-voice andlor [1ata]. Further, in the present invention, even when using non-periodic frame pulses, the maximum value of the access waiting time can be kept constant, so this characteristic can be used to transmit synchronous information. Furthermore, the present invention can be applied to either a bus type or a loop type, and can also be applied to either a branch type or an interrupt node type.

Among the bus types and branch types, there are a collision type that allows data packets to collide and a control type that controls to prevent collisions.The present invention belongs to the latter control type, so it is possible to achieve high communication efficiency. It is something.

[Conventional technology]

Two types, the branch node type and the interrupt node type, will be taken up, and an example of the branch node type will be explained first.

FIG. 10 is a general configuration diagram of a bus type/branch type synchronous LAN. In FIG. 10, symbol X is a control node;
L is a transmission path (in this example, a conductor cable), R is a terminating resistor, and 1.2.3.4 is a terminal node for connecting to a computer or the like.

FIG. 2 is a time chart for explaining the operation of the LAN. eX is a pulse waveform at the transmission point of control node χ, eAxen is a pulse waveform at branch points a to d,
λ1 and λI2 are frame synchronization pulses sent out by the control node X, and D1-D are packets (signals) sent out by the terminal nodes 1-4. However, the description of ec is omitted in FIG.

Terminal node 1.2.3.4 has sequence numbers (1, 2, 3,
4) is given in advance. In this example, the nodes are attached in order from the one closest to the control node X. That is, the distance from the control node X to each terminal node is measured using a pulse reflection technique or the like, and the sequence number is determined from the distance and notified to each terminal. Each terminal node performs frame synchronization by detecting the frame synchronization pulse sent by the control node X, and knows the position of the time slot that it can transmit from this synchronization position based on the above-mentioned sequence number. However, time slots are not assigned to terminal nodes in an empty state that do not have packets to be transmitted, and time slots are assigned only to terminal nodes in a waiting state that have packets to be transmitted. Each terminal node communicates control information described below with the control node X in advance using a specific time slot on the frame. The terminal node in the waiting state sends a time slot allocation request to the control node X in a procedure not shown, and the control node and the number of allocated time slots are determined and notified to each terminal node in advance.

In FIG. 11, all terminal nodes ~4 are in the waiting state,
The case is shown in which one time slot is assigned to each of them. However, ee is omitted in the drawing.

The packet immediately after being sent from the terminal node 1.2.4 is shown in outline and is indicated as ,D,,D4 (D
3 is omitted). These packets propagate bidirectionally on the transmission path as shown by the arrows in FIG. 10, and in FIG.
It propagates as shown as D4. control node
Viewed from the output point, these pulses are transmitted in the opposite direction to the frame synchronization pulses (λ14, λ1□), so there is a time gap between the pulses that is equivalent to twice the propagation delay between adjacent terminals, resulting in tooth extraction. It looks like If terminal node 2 is an idle terminal, time slot D2 can be assigned to terminal node 1 or 3. That is, terminal node 1 or 3 can transmit two packets.

This method is suitable for transmitting synchronous information, there is no signal collision on the transmission path, and almost the entire transmission capacity (capacity for transmitting control information between control node X and each terminal node, frame synchronization pulse However, it is not suitable for transmitting asynchronous information with a short waiting time.

After all, when a queue of data to be transmitted occurs to a certain terminal node, this terminal node requests the control node to allocate a time slot.

Here, since request allocation of time slots generally requires a long time, even if there is little traffic added to the transmission path, the access delay time until this terminal starts transmitting data will be long. When transmitting data that is bursty and has frequent occurrence characteristics, the delay time based on such request allocation is a major factor in reducing throughput.

Note that in the bus-type LAN shown in FIG. 10, if the terminal end of the transmission line is connected to the other end of the control node X, it becomes a loop LAN, but the above-mentioned principle can also be applied to such a loop LAN.

Next, an example of a conventional technique using an interrupt node will be described.

FIG. 12 is a configuration diagram of a bus type/interrupt node type synchronous LAN. In FIG. 12, X and Y are control nodes, 1
．． 2. N is an interrupt type terminal node, REP and AU are a signal relay unit and adapter of the interrupt type terminal node, and LA and LB are transmission lines. Furthermore, F is a frame synchronization pulse, HA is a header section, D is a transmission data section, and S is one time slot.

FIG. 13 is a partially detailed diagram showing the first terminal node. In Figure 13, AMP is an amplifier, SR is a register, OR is an OR gate, ALJ is an adapter unit, RQ is a request counter, CD is a countdown counter, G1 and G3 are input terminals, and G2 and G4 are output terminals. .

In FIG. 12, the control node X periodically sends F frame synchronization pulses in the direction of the dotted arrow. Data packets (or messages) generally sent from terminal nodes
are too long to be transmitted in one time slot, so they are divided and transmitted as unit length data (also called segments) using the transmission data portion. Such time slots are created one after another, and the signal relay unit RFP of each terminal node moves along the transmission line LA in the direction of the double line arrow.
transmitted via.

The data portion in the time slot S departing from the control node X is initially an empty time slot that does not contain any information. If node 1 now has a queue, it can load its own data into the data section of an empty time slot and transmit it to the right in the diagram. However, if access to empty time slots is allowed without permission, terminal nodes close to the control node X will have easier access.

To solve this problem, a method has conventionally been used in which the access rights of each terminal node are controlled using an algorithm called the DQ protocol.

Now, consider the case where data is transmitted from the first terminal node I in the right direction using the transmission path LA. A node waiting for a data transmission request in the right direction uses a part of the header HA to transmit the request signal in the left direction via the reverse transmission path LB. These request signals are stored in advance in a request counter (RQ) shown in FIG. Let tl be the time when node I intends to transmit. Time t
1, terminal node I transmits a request signal to the left via transmission path LB. On the other hand, the total value V (RQ) of request signals sent by nodes on the right side of the terminal node I via the transmission path LB by time t1 is stored in the request counter RQ in FIG. 13 (first node). This value corresponds to the number of waiting nodes that already exist on the right side of the terminal node ■. The adapter unit AU of the terminal node ■ transfers this value V (RQ) from the request counter RQ to the countdown counter CD at time t1,
Reset request counter RQ.

Next, when the header part of time slot S flowing on the transmission line LA arrives at the shift register SR of its own node,
The adapter unit AU of terminal node I decodes its contents and determines whether the time slot is free (idle) or not.
Identifies whether it is already being used (busy) by a terminal node to the left of terminal node I. Each time an empty time slot is transmitted to the right, the count value V (RQ) of the countdown counter CD is subtracted by one. That is, since this empty time slot is used by any of the waiting nodes on the right side of the terminal node I, the number of waiting nodes on the right side that had queues before time t1 should decrease accordingly. Let t2 be the time when this value V (RQ)=O.

This means that all the waiting nodes on the right side of the terminal node existing at time t1 successfully access at time t2, and strictly speaking, the transmission ends after some signal propagation time. Terminal node I is then allowed access to the next free time slot.

Let t3 be the time when an empty time slot arrives at Hatsushima after time t2. At time t3, the terminal node I accesses the transmission path, changes the empty time slot header section (HA) output from the shift register SR in FIG. 13 from idle to busy, and sends the transmission data to the data section. Successfully send data.

These operations are performed by the OR game shown in FIG.

On the other hand, during the period from time t2 to time t3, the request signal from the waiting node newly generated at the node on the right side of the terminal node E is transmitted to the adapter unit (AU) of the terminal node L.
It is counted by counter RQ.

In other words, the transmission requests from these waiting nodes are sent to the terminal node I.
will not be fulfilled before it is sent.

Next, assume that the terminal node does not receive a transmission request for a while after time t3, remains an idle node, and becomes a waiting node again at time t4. Also during the period t1 to t3, the terminal node I counts the request signals from the waiting nodes generated on the right side of the terminal node I in the request counter RQ. Moreover, each time the terminal node I detects an empty time slot propagating rightward during the period t2 to t4, the number of waiting nodes on the right side of the terminal node I decreases by one, so the count value of the request counter RQ decreases by one. Subtract.

As a result, the request counter RQ at time t4
The count value V (RQ) indicates the exact number of waiting nodes on the right side of the terminal node I at that time. By repeating this process, access right allocation control is performed.

Problems with this conventional method are (1) since a reverse transmission path LB is required to determine access rights, the system will go down in the event of a failure in the transmission path LB, and reliability cannot be improved.

(2) The delay time until the final node terminal N obtains the access right is the signal propagation time on the transmission path as τ1 and the time length of the data D as τ during high traffic.

When , it becomes [2τ, +(N-1)　τD].

The reason is that it takes τ6 to transmit the request signal to the first terminal node, τ1, and (N− 1) Until (N-1) nodes finish transmitting the queues they already have
τ, is required.

In a long-distance system with a long signal propagation time τ6, this delay becomes a factor that cannot be ignored.

(3) The transmission delay time and throughput of packets, including the access delay time described above, vary significantly depending on the location of the terminal. As a result, fair allocation of access rights is seriously impaired.

(4) The terminal node is expensive because the control by the counter is extremely complicated.

The above-mentioned principle can also be applied to a loop topology in which the control nodes X and Y are placed at the same location and connected together in FIG. 12, but the same problems arise.

FIG. 14 is an explanatory diagram of another conventional technique using an interrupt node. X is a control node, A, B, and C are interrupt type terminal nodes, L is a ring-shaped transmission line, F is a frame synchronization pulse, and S
Yl and SY2 are synchronization time slots, BT is a busy token, D is transmission data, and FT is a free token.

The terminal node in this case has almost the same circuit configuration as in FIG. 13, but since there is no reverse transmission path, it consists of the four relay sections RE P and the adapter unit (AtJ) in FIG. 13. Also, the shift register SR has a gate on the output side,
There are cases where the incoming signal at the terminal G1 is output as is to the terminal G2, and cases where it is absorbed by the adapter unit (AU).

In the system of FIG. 14, a control node X generates a periodic frame synchronization pulse F and transmits it in a counterclockwise direction. F
This method creates synchronous time slots on the loop transmission path, so it is called a time division synchronous loop method. Therefore, in order to carry synchronized shadow signals such as voice, synchronized time slots (SYI, SY) are required from the terminal node under the allocation control of the control node
2, and a signal can be periodically placed there. When a burst data signal is placed in the synchronized time slots SYI and SY2, a waiting time for request allocation is generally required, similar to the bus type synchronous LAN described in FIG. 1θ.

To avoid this, the remainder of the synchronization time slot (
(from the trailing edge of SY2 to the leading edge of F) is used in this example for asynchronous transmission of data signals.

When a data signal accesses this remaining time slot, for such an interrupt node type LAN, a token passing method (
An interrupt node type asynchronous LAN) is used. That is, this method is a mixed method of a time division synchronous loop method and a token passing method. Therefore, I V D(
Integrated Voiceandlor Da
ta) It has the advantage of having multiple functions.

In the token passing method, one free token FT is transmitted on the transmission path when access from the terminal node is permitted. Now suppose, for example, that terminal node A identifies that an FT has arrived in its shift register SR. If the terminal node A is in the waiting state, this free token FT is changed to a busy token BT and sent to the transmission path, and then the transmission data D is sent, and after the transmission of the transmission data D is finished, the other terminal node A free token FT is sent to allow access.

This situation is shown in FIG.

This free token FT is transmitted to the next terminal Node B. If the terminal node B is a waiting node, it can send the transmission data in the same manner as described above.

Note that when the packet sent from terminal node A completes the loop and returns to terminal node A, terminal node A
absorbs this packet.

The problem with this conventional method is that the waiting time T for accessing a free token becomes significantly longer as the propagation delay time τ around the transmission line and the throughput ρ increase. Its value is T, a, , τd/2(1-ρ)(
1). In the long-distance method, since τ is long, this method becomes less advantageous, especially in the case of high traffic (ρ″=,1).

In addition, due to the complexity of token processing, errors in token processing may result in the generation of multiple free tokens or the generation of busy tokens that circulate forever. In order to recover the system from such a failure state, the control node X needs to monitor and control the token. However, the above recovery process is generally complicated and requires a long time.

[Problem that the invention attempts to solve]

A branch node type asynchronous LAN without an interrupt node cannot increase throughput due to collisions. Moreover, since the access waiting time is undefined and can be as long as 2, it is essentially impossible to transmit synchronous information. Although the branch node type synchronous LAN shown in FIG. 10 has a high throughput, as mentioned above, there is a problem in that the access delay time increases and the throughput decreases due to burst data transmission.

However, because the branch node type LAN is a branch type, the mobility of terminals is extremely high, and it is advantageous as a short-distance system. Therefore, it is desirable to use this topology to solve the above problems.

On the other hand, the interrupt node type using the DQ protocol described above
Although the synchronous LAN has an IVD function, there is a problem in that the delay time and throughput vary depending on the location (order) of the terminals. Furthermore, since the access delay time during high traffic includes the propagation delay time factor of the transmission line, the performance cannot be fully demonstrated in long-distance systems, which this system is good at. Furthermore, there are major problems in terms of reliability and complexity of the control mechanism.

Furthermore, the above-mentioned interrupt node type asynchronous LAN (token passing method) has an IVD function if configured in a mixed manner with a time division synchronous LAN, but the access delay during high traffic is due to the propagation of the transmission path. Since the delay increases in proportion to the delay, it is not suitable for long-distance systems. Furthermore, failures may occur due to incorrect processing of tokens, and recovery from such failures is not easy, which poses problems in terms of reliability and safety.

The present invention has the following advantages: (1) access delay time is small and its maximum value can be set; (2) access time is fair regardless of the location of the terminal node; (2) throughput is increased by reducing loss time; Adding control information to the frame synchronization pulse improves system controllability; ■ The circuit configuration of the terminal node is simple; ■ It has an IVD function with synchronous or asynchronous access; ■ It supports branch-connected and bus-type LANs. It is an object of the present invention to provide a method that can be applied to a LAN of a split node type as well.

[Means for solving problems]

The present invention includes a transmission path, a control node connected to the transmission path, and a plurality of branch terminal nodes branched from the transmission path or an interrupt terminal node inserted into the transmission path, In the multiplex communication system, the control node includes means for transmitting a periodic synchronization signal to the transmission path,
The terminal node includes means for counting the number of time slots having a plurality of different lengths transmitted on the transmission path by all the terminal nodes in positions to receive the synchronization signal first, using the synchronization signal as a reference. A sequence number is set in advance in each of the terminal nodes corresponding to a physical position of a branch point on the transmission path or an insertion point of the terminal node, and further, each of the terminal nodes has the counting means. means for identifying its own transmission time slot position by comparing the number of time slots counted by the terminal node with the sequence number set for the terminal node;
When the arrival of its own transmission time slot is identified by this identification means, if there is a packet to be transmitted, the packet is transmitted to that transmission time slot, and if there is no packet to be transmitted, it is idle in that transmission time slot. The apparatus is characterized by comprising a means for transmitting a pulse.

〔Example〕

Examples will be described separately regarding the branch node type and the interrupt node type.

FIG. 1 shows a branch type, bus type, and synchronous LA according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram of the system configuration of N. This is a configuration in which a control node Y1 and a reverse transmission line LB are added to the conventional system described in FIG. Further, this may also be said to be a configuration in which the conventional interrupt type node explained in FIG. 12 is changed to a branch type node. 1.2.3, , h, j in Figure 1
, in , ,N is the terminal node, is the branched form, and X
1Y is a control node, LA and LB are transmission lines F, and Fr are frame synchronization pulses.

FIG. 2 is an explanatory diagram of the operation of this embodiment, and is a diagram showing the arrangement of time slots on a frame. F is a frame synchronization pulse, P-■, P-■ are packets sent from the terminal node 1.2 (to be exact, they are segments into which a packet is divided, but here they are considered as data transmission units and are called packets) ), P, is the preamble (part of the header), ED is the bucket completion signal (p, , E, is part of P), U is the waiting packet that was not successfully transmitted, τ1 is loss time, ■ is idle pulse, E81~
E, 3 is an example of a combination of standby terminals, and Sq: ■, ■, . indicates that the series of standby terminal nodes is ■, ■, .

FIG. 3 is an explanatory diagram of the operation of the embodiment shown in FIG. 1. FIG. 3 is a spatio-temporal relationship diagram showing the relationship between the arrangement of time slots over a plurality of frames and their positions on the bus. F, (S
) (m = 1.2.3.4; S = 1.2, N) is the mth frame synchronization pulse, which indicates not only the frame synchronization position but also that the access initiating terminal node is the Sth terminal node. It also includes information to F□ is the auxiliary frame pulse in the second frame, and D(n) is the signal transmitted by the n-th terminal node that propagates in the opposite direction and reaches the control node CF, ) indicates the entire m-th frame. The horizontal axis shows time, Tf is the frame period, τ is the signal propagation time of the entire transmission path between X and Y, Tf is the frame pulse time width, τ is the bucket shown in Figure 2) P and idle Average time slot length considering the frequency of occurrence of pulse I (Actually, it is either the time width τ of packet P or the time width τ of idle pulse ■, but here, for simulation, the average value of both τ, (indicates the existence of a time slot), 2τ
6 is the round trip propagation time of the transmission path (in this figure, it shows the propagation margin time for signals propagating in the opposite direction), T is the time width from the trailing edge of D (n) to the leading edge of the next frame synchronization pulse is the residual frame time.

The vertical axis in FIG. 3 indicates the spatial position of a branch point on the transmission path between the two control nodes X and Y, and the numbers ■ and N of terminal nodes branching from the branch point are displayed. Terminal numbers ■, k, etc. in the figure indicate that signals (P or ■) have been sent from branch terminal nodes ■, . . . k, etc. to the respective temporal and spatial positions.

FIG. 4 shows an example of the configuration of a branched terminal node. AU is an adapter unit, and SR is a shift register.

FIG. 5 is a detailed circuit diagram of the adapter unit (AU) shown in FIG. 4. In the figure, P is a packet, ■ is an idle pulse, and P
r is a preamplifier node E, is a child signal for a packet, and F is a frame synchronization pulse, which are the same as those explained in FIG. PD is a pattern detection circuit, SC is a terminal counter, B
C is a bit counter, N, , N are the number of bits that can be transmitted in one frame and remaining frames, PR is a register for packets to be transmitted, IR is a register for idle pulses, and Q is a queue for data to be transmitted. (actual transmission data is stored in the packet register PR).

Returning to FIG. 1, the operation will be explained using FIG. 2. FIG. 1 shows an example of access to a time slot on a right (forward) direction synchronization frame based on the synchronization frame period F transmitted from the control node X. Each terminal node operates according to the following algorithm.

(1) The synchronization pulse F from the control node X is always captured and an internal clock is established based on this.

(2) Synchronization pulse F. (bucket) P or idle pulse (2) following 2 is detected, and the total value C1 of the number is counted.

(3) Use the sequence number n of the own terminal and the total value C1 to find the number of waiting time slots W = n - C, (2), and if W = 1 (3), use the next time slot for own transmission. It is assumed that the time slot is available.

(4) If the own terminal node is a terminal node in a waiting state with a transmission request, data is sent to this time slot.
If it is a registered active terminal node but is in an empty state with no transmission request at this point, it sends out an idle pulse I.

E and l in FIG. 2 are examples in which all terminal nodes are in a waiting state. Since the leading terminal node 1 closest to the control node X has the right to transmit in the time slot immediately after the synchronization pulse F, it transmits the bucket) P-0. When the second terminal node identifies the arrival of the bucket) P-■, it calculates W = 2 - 1 = 1, learns that it has been given the right to transmit the next time slot, and transmits the bucket. ) P-■ is sent.

Each bucket) P consists of a preamble, a data part, and an end signal, and the data part includes a destination address and the like. Each terminal node learns of the arrival of a packet by identifying the preamble P.

FIG. 2E, 2 shows a case where the transmission request starts from the terminal node 2 and is scattered. In this case terminal node 1
Since there is no transmission request, the address pulse message is transmitted instead of the packet P. The terminal node 2 detects ■-■ from the preceding idle pulse I, sets C3=1, and confirms that the time slot in which it can transmit has arrived.

Considering the terminal node 5, n=5, and detects the preceding idle pulse I-■, packet P-■, idle pulse I-■, and idle pulse I-■, and outputs C3.
=4, and when it obtains W=1 from equation (2), it knows that the transmission right has been granted and transmits the bucket) P-■. 211th! Packet U of l is a service incomplete packet whose transmission request could not be fulfilled, and τ1 is packet P
Alternatively, it is a lost time that cannot be used for communication because it is shorter than the time length of the idle pulse I.

E and 3 in FIG. 2 are an example of a case where there are many idle terminals, and show a situation where address pulses I are continuously transmitted.

Here, the following algorithm is added in order to deal with the case where the frame matching boundary approaches.

(5) When a frame pulse F is received, the bit counter BC is set to Nf [1 frame time available for transmission Cr]
t-τt2τd)], subtracts the incoming number of bits, and always advances C5 of the resulting count.

(6) Bucket) A terminal that wants to send an idle pulse I checks in advance whether or not the following equation is satisfied with respect to this count value C1, and does not transmit the above (4) for pulses that do not satisfy the following equation.

Pulse of terminal in standby state ;(:, >p (4) For idle terminal: Cb > 1 (5) Here, p
, l are the bit lengths of the signals P and I.

Usually about 1 byte is used for the preamble P and end signal E. If the preamble Pr1 end signal E is reliably detected at each terminal, one bit is theoretically sufficient for the idle pulse I, but if we consider the error rate of the transmission path and use majority voting, for example, three bits are required. become.

In this embodiment, by notifying each terminal of the sequence number of the terminal in advance, orderly operation can be realized using the simple algorithm described above.

By the way, when the access method shown in FIG. 2 is used, the opportunity for terminals with large sequence numbers to access the terminals decreases, so fair access cannot be guaranteed. Considering this point, if the last terminal that accessed the last frame (including the terminal that sent I) is numbered, and the first terminal that can access the next frame is set to +1, then Access opportunities can be circulated.

FIG. 3 shows a cyclic access pattern to such a synchronization slot. The frame synchronization pulse F1(S) includes information that the leading terminal node that indicates the frame (F,i (m=1.2.3,) is the Sth. Therefore, the frame synchronization pulse F+ According to the instruction in (1), the first terminal node of the first frame [F1] becomes ■.The last terminal of this frame is k, and as shown in Figure 3, the packet sent by k is sent in the opposite direction. is also propagated and is detected by control node X as signal D (k).In other words, control node
2 (k+1).

In the second frame [F2], packets are transmitted sequentially starting from the terminal number +1 until ending at the final terminal node N, but the packet sent by the terminal node N is sent to the control node X as packet D (N). Detected. The control node X thereby knows that the access right has passed through all terminal nodes. The time from the trailing edge of this bucket)D(N) to the beginning of the next frame is the remaining frame time Tr, and if T, > (2τ6+τt) (6), then the control node By referring to frame [F2a], it is determined that further packets can be sent, and the auxiliary frame pulse F2m is sent out at the timing shown in FIG.

The right side of equation (6) is the time (2τ,) required for inserting F2a (τ,) and transferring the access right to the leading terminal node 1. As shown, starting from F+ (1), F2a
1 in which the period ending immediately before visits all terminal nodes.
The period becomes Tcg. In the second half of frame [F,], the third
In the case of the figure, terminal nodes 1 to j access the frame [
In F3a, terminal nodes j+1 to h access the terminal node using a similar method. Furthermore, in frame F4, terminal node h+
1 accesses and repeats this process.

In this way, each terminal node is given one access opportunity for each cycle period Tsc, so it is possible to achieve extremely fair access characteristics that are independent of the ordinal position of the terminal nodes.

Note that packets D (k), D (N), etc. are transmitted not in the frame pulse transmission direction (in the opposite direction), so when control node X receives these packets, the delay time between adjacent terminal nodes is This results in a pulse train with twice as much empty time inserted.The control node X is provided with the ability to receive and detect such a quasi-asynchronous signal.

Let us now consider the packet length p bits of bucket) P as constant. The cyclic frame period Tcm naturally changes depending on the number N of terminal nodes having transmission requests.

When the number N of terminal nodes is small, the cyclic period Tcs
becomes shorter and the frequency of inserting auxiliary frames increases, resulting in a loss time of (2τ, +τr) each time. However, when the number of terminal nodes N is large, the frequency of inserting auxiliary frame pulses decreases and the transmission efficiency improves accordingly, so this system essentially has the property of adapting to transmission demands.

By the way, when a small number of terminal nodes have a large amount of transmission requests such as file transfers, if the packet length p is constant, the frequency of inserting auxiliary frames increases, which somewhat impedes transmission efficiency. Therefore, when the number Nq of terminal nodes is small, the control node X uses frame pulses to notify each terminal of the relaxation of the allowable value of the packet length p.
It will be possible to adapt to such uneven demand.

The unused time slot τ1 shown in FIG. 2 serves as wasted time and causes a decrease in transmission efficiency. In order to avoid this, it is necessary to control so that the rear part of the bucket) P-■ can be transmitted in the next frame, as shown in the second row of FIG. 2. Let us now assume that the dead time τ1 occurs at the boundary between frames [F1a and [F,]] in FIG. That is, after terminal node k sends the front part of the packet, control node
(kf). The control node X instructs the terminal node k to first transmit the rear part of the packet using the next frame pulse F2(kl). By using such a terminal order relaying method, it is possible to perform continuous transmission according to the geographical order of the terminals and spanning synchronization frames. Note that the sub-indexes f and f indicate the first half and the second half of the packet transmitted by the terminal node k. Specifically, information indicating that it is the first half is included in E of D(kf). Furthermore, information about a second half transmission instruction is included in Fq(kt).

When such a counting type access method is used, a terminal node in a waiting state has two or more queues, and the access waiting time (cyclic frame If the throughput is ρ and Nq nodes out of N nodes are always terminal nodes in a waiting state, then Ta=Tcs=””′ρ, which means that access is always possible within Nr seconds. Therefore, if a method is adopted in which the packet time width τ is controlled by traffic according to instructions from the control node X, each terminal node can always access the terminal node within a certain predetermined waiting time limit.

The circuit configuration of the terminal node required to implement this method will be explained with reference to FIG. The signal transmitted on the transmission line LA in FIG. 1 passes through the input G1 and the input side amplifier AMP in FIG. 4, and is always stored once in the shift register SR. If the bit length of the shift register SR is set to the longest pulse among the preamble Pr and the end signal EP% idle pulse I, in this shift register SR, these signals are detected by the pattern detection circuit (
FD) and is decoded and identified. Based on this identification result, if it is time for the own terminal node to access, the adapter unit AU sends the transmission signal (transmission bucket) P or idle pulse (■) to the output side amplifier AMP.
The signal is sent to the transmission line via the output terminal G2.

This function will be explained in more detail using FIG.

FIG. 5 is an explanatory diagram regarding the n-th interrupt node, and is a partial circuit configuration diagram for the double bus type transmission line LA line of FIG. 1. In FIG. 5, the input pulse train coming from the transmission line LA is stored in the shift register SR, and then the pattern detection circuit PD determines whether the input pulse train is a frame synchronization pulse F, an auxiliary frame pulse F a, a packet P or an idle pulse I. Identification is made as to whether When the frame synchronization pulse F (s) arrives, the value of station counter SC in FIG. 5 is set to S and the value of bit counter BC is set to Nt.

When the auxiliary frame pulse F arrives, the terminal counter S
The value of C is set to 1, and the value of the bit counter BC is set to the number of bits, N, of the residual frame time contained in the auxiliary frame pulse, F,. Each time P (bucket) or idle pulse I is detected, 1 is added to terminal counter SC, and p or i is subtracted from bit counter BC in response to packet P or idle pulse I, respectively. .

If this terminal node has a queue (Q=1), its packet P is stored in advance in the packet register PR,
If there is no queue (Q=O), the idle pulse ■ is stored in the idle pulse register ■R. From the count value of the terminal counter SC and the number n of this terminal node, formula (2)
is calculated, and if equation (3) is satisfied, this terminal node will have access rights to the next time slot.

On the other hand, the number of pits remaining in the current frame time can be known from the value of the bit counter BC. It judges whether the value is sufficient for the information to be transmitted or not using the logical values Ap and A+ of the following equation, and determines whether transmission is possible (transmission is permitted when A, = 1, A+ = 1) .

A,= (C,≧p)Q (8)AI= (
C,≧p)Q (9) These logic functions are performed in logic circuits DLI and DL2. Logical value A, ,A
, the information in the packet register PR or idle register IR is sent to the transmission path LA via OR.

Note that when the auxiliary frame pulse comes in, s=l and 5C=1 is set, but the bit counter BC
is not set again, its value is kept as is, and the expression (
Control continues according to logics 8) and (9).

Although the packet division relay transmission function was not mentioned here, this function can be easily realized by adding some logical functions.

FIG. 6 is an explanatory diagram of the operation of an embodiment in which the present invention is applied to a topology including an interrupt node (see FIG. 12). The vertical and horizontal axes are the same as in FIG. 3. In Figure 6, F* (Sm, θ, ,) (m=1.2, ・) is m
The frame synchronization position and the access starting terminal node number S are included in this pulse train at the th frame synchronization pulse. θ, is the (packet) P circulating in this frame
This is the expected value of the number of terminal nodes (which can send an idle pulse l), and is shown here for convenience of explanation. Also Fl,
Sl, θ2. The subscript m is used for convenience of explanation. τ6, τ1, τ1, T2, [F,] are the same as the symbols in FIG. τd2~. represents the propagation delay time between terminal nodes 2 and 3. τu (is the loss time as in Figure 2,
θ0 is the total number of terminal nodes actually visited in this frame,
DS is a duplicate (access) terminal node, SS is a skip terminal node, and Δ is a circulation margin (number of nodes). Note that τ in this case.

is the true line propagation time and the delay time at each terminal node (
(latency time) τ, which consists of N times a. As explained in FIG. 18, the terminal node includes a shift register SR whose delay is approximately τ. I miss you.

FIG. 7 is a long-term operation explanatory diagram based on FIG. 6. Most of the symbols in FIG. 7 are the same as in FIG. T1 is the last frame of the cyclic period T'cs, Ts is the next period T'
The first frame of cs, τU, is the loss time.

FIG. 8 is a block diagram of an embodiment of a terminal node when the present invention is applied to the conventional topology explained in FIG. 12. Here, functions for the rightward transmission path LA are shown. The function for the reverse direction transmission path LB can also be realized by the same circuit. The basic configuration is the same as that in FIG. 13, and only the adapter unit (AU) in FIG. 13 is different.

Also, most of the symbols in Figure 8 are used in Figures 13, 5, and 6.
It is similar to FIG. 7. For symbols not shown in Figure 5, N
1 is for the case where when the frame synchronization pulse comes in, it circulates to node N in the last frame of the cycle period,
This is the value set as the initial value of the bit counter BC,
This corresponds to the bit length of frame length T, which will be described later.

FIG. 6 will first be described with reference to the interrupt node type LAN and FIG. 12.

Since this type of interrupt node method is for a one-way long-distance system, reverse transmission pulses cannot be used like in the bus method, so the important issue is how to relay the access order of terminal nodes between frames. It is. When control node X generates a new frame pulse, if control node Since the terminal nodes can be specified, access rights can be smoothly relayed according to the geographical order of the terminal nodes. To achieve this, the final terminal node n needs to transfer its own number to the control node X using the transmission path LB in the opposite direction.
For this purpose, a margin time Trb=2τ, αO must be provided at the end of the frame period as the maximum value of the line round-trip transfer time.

Now, by making the transmission path into a loop and aligning the positions of the two control nodes X and Y, this signal is changed from n1 to Y-+
Even if the signal is transmitted within a short period of time, at least a frame pulse propagation time (τ,) is required. However, in long-distance transmission, the propagation time r is generally long, and the time Trb in equation αQ is wasted time, so a method that generally uses this information n is not necessarily advantageous in terms of transmission efficiency. .

An embodiment that solves this problem will be described here.

Now, the number of terminal nodes that circulate every frame period Tt is assumed to be θ, predicted based on past traffic volume, and adaptively designated based on that value. The total number of terminals is N
When the number of waiting terminal nodes that have packets to be sent in their buffer memory is Nq, since NQ<N,
Average value θ of the effective number of visiting terminals. In the above equation, τ is the average service time occupied on a frame when each terminal node accesses it.

The control node X can calculate T1 and θ in the above equation by collecting past traffic information. On the other hand, since the number θ of terminal nodes is a value that gradually changes depending on the traffic, a predicted value θ of the number of cyclic access terminal nodes in one frame in the future is set based on the average value θ.

Here, m-th frame pulse Fa (s, θ,)
is used to transmit the sequence number s1 of the access starting terminal node and the predicted value θ of the number of access terminal nodes in the frame to each terminal node. In order to clearly indicate the frame order, a subscript m is attached to S and θ, if necessary for explanation. Now m=l, s=1, θ=θ7. FIG. 6 shows an example of an access pattern assuming that.

In FIG. 6, access starts from terminal node 1 and terminal node θ. We have shown the case where it ends with . If the predicted margin Δ shown in the figure is chosen to be sufficiently large, θ. terminal nodes can almost certainly be accessed within this frame. That is, it can generally be expressed as θ2=θ, −Δ=ξθ, α■ ξ=1−(Δ/θ, ). However, as shown in Fig. 6, the actual number of traveling terminal mates is θ0, and the number of terminal nodes θ0 is θ,
It is considered to be a random variable that fluctuates with the average value.

Further, ξ(<1) of the expression α is the cyclic margin rate.

The frame CF+) in FIG. 6 is the frame pulse F1(1
, θP1) are transmitted, and θP+<θ. This is the case. In other words, even if θ, one terminal node is visited, 1
The frame time usually does not end θ. The access right is circulated up to the th terminal node, and FIG. 6 shows this situation. Second frame pulse F2 (S2, θ
, 2) is the predicted value θ of the number of visiting terminal nodes in the preceding frame.
, an instruction is given to start access from the S2nd terminal node. Generally, S, 1=S, +θ1.0 is set. Therefore, from (θpt+'l) 00
All terminal nodes at the 0th
Access rights will be granted again at the beginning of section a. These terminal nodes DS are duplicate access terminal nodes.

The difference between the actual number of visiting terminal nodes θ and the predicted value θ2 is a predicted deviation, and if the control node X collects this value over a certain period in the past, a new average value θ6 can be determined.

On the other hand, if we consider the case where θ, 1>θ0 in frame [F1a], at the end of one frame, the terminals from (θo+1) to θF1 are not given the opportunity to access, which is indicated by the dotted line in FIG. Thus, at the beginning of frame [F2a, these terminals are skipped and access is started from the (θ, , +1)th terminal node. The probability of occurrence of such a skip terminal node SS (skip rate) is preserved in the amount of fluctuation of incoming traffic, but if the cycle margin △ of the formula α is chosen large and the cycle margin rate ξ is selected sufficiently small, the probability of occurrence can be made sufficiently small. sell. The control node X uses the information up to 2τd seconds ago (the value of θ of the past frame) to obtain the average value θ, and this average value θ.

Based on this, the next frame pulse predicted value θ is determined. If the transmission line is made into a loop and control nodes X and Y are combined, information up to 77 seconds ago can be utilized.

FIG. 7 shows how the access operation of FIG. 6 progresses in sequence. Frame [F1a] in FIG. 7 has almost the same operation as in FIG. 6, but suppose that the frames advance one after another and the i1th frame pulse is Fl (31% θ, I). In this case, the number of remaining terminals N, is N, = N (s+ 1) <θ,, Q5
), it should be possible to complete a tour of all terminals in this frame with a high probability. FIG. 7 shows the case of 1=2. That is, the process in which the access right goes around once in frame [F,) and returns to the first terminal is shown. Frame [F3a has the same operation as in FIG. 6, but the terminal node that starts access uses frame pulse F3 (
According to the instruction of S3, θp3), it is S5th.

In addition, when looking at the front and back of frame pulse F, terminal θo3
is ahead of the next access initiating terminal S. In this case, terminals in the section from (θ.3+1) to (s3-1) will lose access opportunities.

However, the occurrence of such a case can be designed to be sufficiently small by reducing the cyclic margin rate ξ.

The illustrated frame [F,] is the final frame, in which the access order returns to the first terminal node. Such a final frame is generally divided into <TL and T5 as shown. T, is the average packet length τ.

It is the value obtained by dividing the average time required for Nr terminals to transmit a packet of by the cyclic margin rate ξ, and is given by the following equation.

T L = N r r a /ξ a
oT, =T, -τ, -TL, Q'l) Now, let T be a partial frame time that can be calculated in advance using the above equation, and let its bit length be N. The control node
(Sl, θ, 1, N,) can be transmitted as bit number information. The first node terminal 1 that detected this recognizes that it can start circular access after 13 seconds, and
We know that the period of T on the large side can be utilized for signal transmission.

That is, the node terminal 1 has Fl(Si, θP1, NL
), access can be started when T1 seconds have elapsed, but in order to more accurately indicate this point, the control node X transmits the auxiliary frame F+-(1, θ, N,) anew. Here, θ, 6 is the number of cyclic terminal nodes in the first frame, and N1 is the bit length of T. Since N is determined from the equation α force, it does not need to be transmitted.

In this way, in each circulation period, twice for a small number of duplicate terminal nodes DS, and once for other terminal nodes.
You will be given the opportunity to access the site once.

Furthermore, since this duplicate terminal node DS generally changes randomly every cycle, fair access characteristics can be achieved.

Next, immediately before each frame pulse E, , F, a, the second
The loss time τuf shown in the figure occurs, and its average value is given by the following equation.

τuf=τ, hit loss time ru
f is the increment of the cycle period, but if the end of the frame period approaches, the terminal node in the waiting state accessing the time slot may use a different packet size, for example, τ, = 1 byte. If it is accepted, it can be reduced from τuf to τa, and a significant drop in transmission efficiency can be avoided.

By the way, in the final frame [F,], the access right cannot be advanced beyond the final terminal, and a prediction error occurs in the time slot immediately before the auxiliary frame pulse Fia. In the case of insufficient frame time, the final terminal is not given an opportunity to access, which is undesirable in terms of system operation, but there is almost no lost time. On the other hand, if the frame time is too long, a loss time τu6 occurs. In general, the cyclic margin ξ
Choosing a small value will surely provide an access opportunity, but the loss time τu6 will increase. In that case, if the final terminal N has long queue data, it should be possible to reduce the loss time τ by allowing a long packet length.

However, if the #most terminal happens to become an idle terminal, the remaining allocated terminal time (τ, /ξ) becomes lost time. As a method to keep this loss time τ, small and to allow access by all terminal nodes up to terminal node N with high probability, the terminal node in the n-th waiting state uses the following algorithm to transmit the packet time τ, ( n) adaptively.

That is, the time T left for the last frame pulse before the nth waiting terminal node transmits.

The value obtained by subtracting the allocated time for the remaining number of terminal nodes h=N−n from (n) is 1p(n>=TL (n) h ra/ξ 0
Then, towards the end of the final frame [F,],
The residence time is adjusted each time each terminal node accesses. When this is calculated using the probability (N, /N) of occurrence of a terminal node in a waiting state, the following relationship is obtained as the expected value of the loss time τ5a.

E(τ5.)〈τ, (2) Therefore, this can prevent the transmission efficiency from decreasing due to τ.

By using the various techniques described above, the loss time τ5 and τuf can be made sufficiently small, so that the throughput can be sufficiently increased.Furthermore, the access waiting time can be reduced to Nr or less, so that the time slot for the frame synchronization pulse can be By allocating a portion for control signals, the packet size can be easily changed as appropriate, and if the packet length τ2 is kept below a certain value during high traffic, the maximum value of the access waiting time can be set as the system target.

Further, if priority control information is placed on the frame synchronization pulse to preferentially permit access from a specific terminal node, transmission of priority packets can be easily realized. In this case, a priority packet transmission request is sent to the control node X or Y through either the forward or reverse transmission line LA.

If the packet is transmitted in advance via the LB, the control node X or Y can specify a frame exclusively for priority packets based on the request.

Next, in the embodiment of the interrupt node type synchronous LAN, the terminal node is almost the same as in FIG. 13, but the inside of the adapter unit (AU) is different. FIG. 8 is a detailed diagram of an adapter 22) AU for this purpose.

This figure 8 is similar to the above-mentioned figure 5 and performs the same operation. The only difference is that when the incoming frame synchronization pulse arrives, if the last node is expected to access within the following frame time, this frame will be the last frame of the cycle.

Therefore, the frame length is N based on the predicted value described above.

(TL pit number display). This value NL is determined by the control node X and this information is included in the frame synchronization pulse mentioned above. Therefore bit counter BC
The initial value of is set to N1 (in a normal frame, Nt
). The other operations are the same as those explained in FIG. 5, and the explanation will be omitted.

In the embodiment described above, the synchronization frame period T.

As far as we focus on, it is a completely synchronous type, but the above communication operation can be realized even if the frame synchronization pulse is removed. In this case, it is an asynchronous type.

In the bus-type LAN of FIG. 3, the hatched frame synchronization pulse F7 is removed, leaving Fl (1) (because it is also an auxiliary frame pulse) and the auxiliary frame pulse F□. Then, the control node
Suppose that D (N) is detected in 4a. Then, X sends out the next auxiliary frame pulse, F 4m. By repeating this operation, a sequence of F□ is generally created, so for convenience we will give a new sequence number m=1.2.3.

At this time, a series of auxiliary frame pulses F1, F2a, F3a, whose frame period is the cyclic frame period Tcs, is generated.

In this case, the cyclic frame period Tcs is not constant but changes depending on the traffic, so it is no longer a synchronous type. However, its maximum value is constant, Tc, , = Nt
, +'2τd+τ, G! l) is given.

In this case, since it is a branch type, the propagation time τ, and the latency time τ3. is not included. Therefore, if the information rate of synchronous information is g bits/second, the shortest time for cyclic frame synchronization is '
If the length of the packet to be sent during rciF is h bits, then Therefore, generally T e %≦Teas
Therefore, all predetermined information can be transmitted. In general, h bits are transmitted every cyclic frame synchronization T0, and if no information is stored in the transmission buffer, an idle signal is sent instead of pausing the transmission of the packet area P on the time slot given to this terminal node in that frame. The transmission speed to the LAN and the information source speed can be matched by thinning transmission such as sending I. In order to concretely realize this, it is sufficient to prepare a buffer memory with a capacity of about 2h bits in the transmitting/receiving terminal. In this way, an IVD function can be provided.

In this asynchronous form, the loss times τuf and τ occur in the period of the frame. , are eliminated, frame synchronization pulse control becomes simple, and there are advantages in that throughput and delay time characteristics are also improved.

Next, in the interrupt node type LAN shown in FIG. 7, in the same way, by removing the shaded frame pulses and leaving auxiliary frame pulses such as F and F2a, Tc is a series of auxiliary frame pulses F that is tossed once. am (m =
1.2, ) should be possible. By the way, in this case, the control node X is D (N) in FIG.
Since such a signal is not given, the control node X cannot determine the transmission position of the next auxiliary frame. This problem is solved by the following method.

FIG. 15 shows a configuration example of the present invention, which is an extension of the example shown in FIG. 12, and its time chart. FIG. 15(a) is a loop version of FIG. 12, showing only the transmission path A, but a relatively reverse transmission path B is also generally prepared. In this loop, there are two (or more) control nodes X1
Y and general interrupt type terminal nodes 1.2, N', and N are included.

The control node X first sends out a cyclic frame pulse Fl11, and then the terminal nodes 1 to N° sequentially send out a signal (packet) P or idle I). Since the control node Y can accurately detect the trailing edge of the signal sent by the terminal node N°, it sends the cyclic frame synchronization pulse F□ to this position. In the time slot following FYI, terminal nodes (N'+1) to N sequentially send out signals. control node
detects the trailing edge of the signal sent by terminal N and sends out the next cyclic frame synchronization pulse F, 12 in this time slot. In the time slot following this pulse F112, the terminal nodes 1 to N° sequentially send out signals and repeat this operation.

FIG. 15(b) shows the interrelationship of these pulses. Each signal (packet P or idle ■) sent from each terminal node is indicated by the length of the average value τ1. Further, the maximum value of the cyclic frame period in this case is Tc5a = N r p + 2τf1221, which is approximately 2τ smaller than the formula QI). 2τ.

is the time length of frame synchronization pulses F and F sent out from control nodes X and Y.

In this case, the receiving side of control node There is a need to.

This is indicated by the thick black line in FIG. 15(b). Furthermore, the control node X must always send out a new frame synchronization pulse F at an appropriate timing.

FIG. 16 is a block diagram of an embodiment of the control node X that implements the above-mentioned functions. In Fig. 16, 1, N are the same symbols as in Fig. 12; AMP, SR,, PD, O
R is the same symbol as in FIG. FF is a flip-flop, FG is a frame pulse generator, AND is an AND gate 1, and Dl, D2, and Dl are outputs of a packet decoder PD. When the control node shown in FIG. 16 is used as the control node X, it is inserted into the transmission path between the terminal node N and the control node X. here,
Dl: Leading edge of the same frame pulse F, D2: Trailing edge of the end signal E of bucket) P sent by the terminal node N' or idle signal ■, D: End of P of the packet sent by the terminal node N If the detected output is the signal E, or the trailing edge of the idle signal The output side of becomes "1", and all outputs of the terminal node N during this period are blocked here. Furthermore, since the trailing edge D3 triggers the frame signal generation circuit FG, the frame synchronization signal F is sent out at the trailing edge of the output of the terminal node N. A similar circuit can be used for control node Y as well. Note that the above signals RI, Dl, and Dl are outputs of the trailing edge of the detection signal, so they can be easily generated by installing a delay circuit having the bit length of the end signal E and the idle I in the packet decoder PD shown in the figure.

Furthermore, in FIG. 15, the inserted terminal node 1.
2. Let's consider the case where all N are branch nodes. Although the signal sent from the terminal on the transmission line LA propagates in both directions, the system is similar to that in FIG. 1 in which only the signal propagating in the direction of the arrow is detected by each terminal node. In this case, the operation will be based on the same principle as in FIG. 15(b), and the maximum value of the cyclic frame period is Tc1s = N r p + 2 τt
e21, the influence of the cable propagation delay time τ disappears, and the throughput/delay time characteristics improve accordingly. An asynchronous count-controlled multiplex communication system can be realized using the circuit and system described above.

〔Effect of the invention〕

As explained above, since the present invention uses a synchronization frame, a part of the time slot of the frame is used as a time slot for synchronization information, which is extremely effective when used for transmitting synchronization source information such as voice. , and other time slots can be used for transmitting data with burst characteristics.

Moreover, when this data is transmitted asynchronously, not only can extremely short access latency characteristics be realized, but also the upper limit of the latency can be determined. The asynchronous method of the present invention uses this principle and shows that synchronization source information can be transmitted using burst data time slots. That is,
Since a packet can be transmitted from at least one terminal node every maximum waiting time Nτ, for example, Nτ
, = 125 .mu.s 1.tau., -k.times.8 bits, the channel can be reliably transmitted even though the normal PCM audio signal (8k)lz sampling, 8 bits/sample) is selected. In this case, the transmission packet interval of this terminal node is the maximum value Nτ
.

However, if this fluctuation is absorbed by the buffer memory on the receiving side, 7 samples will be generated at 8 kHz intervals.
It can restore second analog signals. In this case, 1
A delay time of about one frame is required, but there are no other deteriorated bones. The deterioration in voice quality due to this delay time is negligible.

Therefore, there is an advantage that synchronization source information can be transmitted without providing a synchronous time slot.

In addition, control is extremely simple compared to the DQ protocol and token passing method, and
Fair access opportunities can be provided.

By using the control information transmission distribution function of the frame synchronization pulse, it is possible to transmit, for example, a priority packet transmission permission signal or a recovery control signal necessary in the event of a system failure, so that adaptive system control can be realized.

Furthermore, when the traffic becomes high, the number of idle pulses sent decreases, and the throughput approaches 100%. However, in special cases, when a small number of terminal nodes have large traffic demands such as file transfers, Depending on the situation (while monitoring the status to ensure that the access wait time of other terminal nodes does not become abnormally large), if the frame synchronization pulse control information allows the packet size to increase, the density of idle pulses will become relatively This reduces the amount of time required, making it possible to achieve highly efficient communication and increase throughput.

As described above, the present invention enables - Reduction of access delay time and setting of maximum value - Realization of fair access characteristics independent of the position of the terminal node - Increased throughput by reducing loss time - Control based on frame synchronization pulses Enhancement of system control functions by adding information (special services such as priority packet transmission,
(advantageous in terms of troubleshooting), ・The circuit function of the terminal node is simple,
Can be realized with a simple control@mechanism - IV with synchronous access or asynchronous access
It is possible to realize a method having various features such as being applicable to D function, branch connection type, bus type LAN, and interrupt/do type LAN. There is no conventional LAN system that has both of these performances, and the effectiveness of the present invention is remarkable.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a bus type/branch type LAN according to an embodiment of the present invention. FIG. 2 is a time chart for explaining the principle of this embodiment. FIG. 3 is a time-space relationship diagram explaining the operation of the above embodiment. FIG. 4 is a block diagram of the terminal node of the above embodiment. FIG. 5 is a partial detailed circuit diagram and frame configuration diagram of the terminal node. FIG. 6 is a time-space relationship diagram illustrating the operation when the present invention is implemented in the configuration shown in FIG. 12. Figure 7 is a long-term relationship diagram. FIG. 8 is a circuit diagram and a frame configuration diagram of a terminal node when the present invention is applied to the configuration explained in FIG. 12. FIG. 9 is an explanatory diagram of insertion and branching. FIG. 10 is a general configuration diagram of a bus type, branch type, synchronous type LAN to which the present invention is applied. FIG. 11 is a diagram explaining the principle of the prior art. Figure 12 shows the bus type/interrupt node type L to which the present invention is applied.
A general configuration diagram and a frame configuration diagram of an AN. FIG. 13 is a partial detailed circuit diagram showing the terminal node of FIG. 12. FIG. 14 is a block diagram illustrating the conventional technology of an interrupt node type/ring type LAN. FIG. 15 is a block diagram and a frame block diagram of an embodiment of the present invention in which the transmission path shown in FIG. 12 is looped. FIG. 16 is a block diagram of an embodiment of the control node. Patent Applicant Nippon Telegraph and Telephone Corporation Agent Patent Attorney Takasuke Ide

Claims (1)

[Claims] 1. A transmission line, a control node connected to this transmission line,
A multiplex communication system comprising a plurality of branch type terminal nodes branch-connected from this transmission line or an interrupt type terminal node inserted into this transmission line, and the control node is equipped with means for transmitting a frame signal to the transmission line. In this method, the terminal node counts the number of time slots having multiple types of lengths transmitted on the transmission path by all the terminal nodes that are in a position to receive this synchronization signal first, using this frame signal as a reference. A sequence number is set in advance in each of the terminal nodes corresponding to a physical position of a branch point on the transmission path or an insertion point of the terminal node, and further, each of the terminal nodes has a means for: means for identifying its own transmission time slot position by comparing the number of time slots counted by the counting means with the sequence number set in the terminal node; At the time when the arrival of a slot is identified, if there is a packet to be transmitted, the packet is transmitted to the transmission time slot, and if there is no packet to be transmitted, the idle pulse is transmitted to the transmission time slot. A counting control type multiplex communication system characterized by the following.