JPH04105725U - Multiplier circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To keep the duty ratio of the multiplied clock signal constant even if the frequency of the input clock signal fluctuates. [Configuration] Switched clock signal that delays the input clock signal.
It has a delay circuit consisting of a register circuit 1 and a capacitor 2, and an exclusive NOR circuit 3 that compares the output signal of this delay circuit with an input clock signal and outputs a clock signal having twice the frequency of the input clock signal, Switched
The input clock signal and the output signal of the exclusive NOR circuit 3 are used as the sampling clock of the register circuit 1.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

The present invention relates to a multiplier circuit that multiplies a clock signal, and in particular to a multiplier circuit that multiplies a clock signal. This relates to a multiplier circuit that has excellent followability.

0002

[Conventional technology]

An example of a conventional multiplier circuit is shown in FIG. 4 and will be described. As shown in Figure 4, conventional multiplier circuits are connected in cascade to delay the input clock signal. an inverter 14 that extends and a delayed clock signal that is the output of this inverter 14; and the input clock signal, and select a clock with twice the frequency of the input clock signal. It has an exclusive NOR circuit 15 that outputs a lock signal. And IN indicates input, and OUT indicates output.

0003

[Problem that the idea aims to solve]

In this conventional multiplier circuit, the delay time of the delay circuit consisting of an inverter is constant. Therefore, when the frequency of the input clock signal changes, the duty of the multiplied clock signal increases. There was a problem that the tee ratio fluctuated. Also, the delay gate of the delay circuit must be changed to match the clock frequency. The problem was that there was no.

0004

[Means to solve the problem]

The multiplier circuit of the present invention is a multiplier circuit that multiplies a clock signal. Switched resistor circuit that delays the clock signal and this switched resistor The capacitor connected to the output side of the circuit and the output of the above switched resistor circuit Compare the signal with the above clock signal and find a clock with twice the frequency of this clock signal. Equipped with an exclusive NOR circuit that outputs a clock signal, and the switched register circuit described above. The above clock signal and the above exclusive NOR circuit are used as the sampling clock of the circuit. The output signal is used.

[0005]

[Effect]

In this invention, the delay circuit includes a switched resistor circuit and a capacitor. , the resistance value of this switched resistor circuit is inversely proportional to the frequency of the input clock signal. However, the delay time of the delay circuit is inversely proportional to the frequency of the input clock signal.

[0006]

【Example】

FIG. 1 is a block diagram showing the basic configuration of an embodiment of a multiplier circuit according to the present invention. . In this figure, 1 is a switched register circuit that delays clock signal a. 2 is a capacitor connected to the output side of this switched resistor circuit 1, These constitute a delay circuit. 3 is the output signal of switched register circuit 1 Compare clock signal b with the above clock signal a and find a clock signal with twice the frequency of clock signal a. Exclusive NOR circuit outputs clock signal c, 4a and 4b are inverters . IN indicates input, and OUT indicates output. Then, the above clock is set as the sampling clock of the switched register circuit 1. It is configured to use the signal a and the output signal of the exclusive NOR circuit 3. .

FIG. 2 is a circuit diagram showing a specific configuration of an embodiment of a multiplier circuit according to the present invention. In FIG. 2, the same symbols as those in FIG. 2 is a field effect transistor, and 13 is a constant voltage source (V _dc ).

FIG. 3 is a waveform diagram showing clock waveforms in each part of the embodiment shown in FIGS. 1 and 2, in which (a) shows an input clock signal a, and (b) shows a switched signal. Output signal b of register circuit 1, (c) is output signal c of exclusive NOR circuit 3, (d) is input clock signal φ _e , (e) is clock signal φ ₀ , (f) is clock signal φ ₁ , (g) shows the clock signal _φ2 .

[0009] Next, the operation of the embodiment shown in FIGS. 1 and 2 will be explained with reference to FIG. First, set the frequency of input clock signal a to f₁ Then, switched register The input clock circuit 1 receives the input clock signal φ shown in FIG. 3(d)._e and this input clock signal φ _e The clock signal φ shown in FIG. 3(e) is inverted by the inverter 4a.₀ support The analog switches 5 and 6 are driven as a sampling clock. Also, in Figure 3 ( Input clock signal φ shown in d)_e The clock signal shown in (f) of FIG. 3 is multiplied by φ₁ and this multiplied clock signal φ₁Figure 3 shows the inverter 4b inverting the The clock signal φ shown in (g) of₂ as the sampling clock, the analog switch switches 7 and 8. By driving the analog switches 5, 6 and 7, 8 in this way, , the resistance value R between the drain and source of the field effect transistors 12-1 and 12-2_{FE T} is determined, and its resistance value R_FET is expressed by the following formula. R_FET = 1/(2C₂・f₁)・・・・・・(1)

[0010]The time constant τ of the delay circuit including this resistance value R _FET and the capacitor 2 is given by the following equation. τ=R _FET・C ₁ =(1/2f ₁ )・(C ₁ /C ₂ ) However, C ₁ is the capacitance of the capacitor 2, and C ₂ is the capacitance of the capacitor 10. Therefore, the time constant τ of the delay circuit is inversely proportional to the frequency f ₁ of the input clock signal.

Next, the exclusive NOR circuit 3 that compares the input clock signal and the input clock signal that has passed through the delay circuit has a constant duty ratio even if the frequency f ₁ of the input clock signal changes, as shown in (c) in FIG. Outputs a multiplied clock signal as shown in .

0012

[Effect of the idea]

As explained above, the multiplier circuit of the present invention has a switched register circuit in the delay circuit. The resistance value of this switched resistor circuit is the input clock. The delay time of the delay circuit is inversely proportional to the frequency of the input clock signal. Since the frequency of the multiplied output clock signal is proportional, the frequency of the input clock signal varies. However, the duty ratio does not change even if the delay circuit is delayed by the input clock signal. This has the effect of eliminating the need to change the gate.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of an embodiment of a multiplier circuit according to the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of an embodiment of a multiplier circuit according to the present invention.

FIG. 3 is a waveform diagram showing clock waveforms at each part of the embodiment shown in FIGS. 1 and 2;

FIG. 4 is a circuit diagram showing an example of a conventional multiplier circuit.

[Explanation of symbols]

1 Switched register circuit 2 Capacitor 3 Exclusive Noah circuit 4a, 4b inverter

Claims (1)

[Scope of utility model registration request] 1. A multiplier circuit that multiplies a clock signal, comprising: a switched register circuit that delays the clock signal; a capacitor connected to the output side of the switched register circuit; and an output of the switched resistor circuit. an exclusive NOR circuit that compares the clock signal with the clock signal and outputs a clock signal having twice the frequency of the clock signal; A multiplier circuit characterized by using an output signal.