JPH04105126A - Pipeline processing system - Google Patents

Abstract

PURPOSE:To evade the interlock and to prevent the deterioration of the processing speed by moving back and forth the position of a prescribed stage including the operand processing. CONSTITUTION:A dummy stage 2 that only functions to transmit the data is added to a pipeline stage 1 including plural stages and can be replaced with a prescribed stage 3 which carries out the operand read processing. So that the position of the replaced stage 3 is set the rear side of a stage executing sequence. Then the position of the stage 3 including the operand read processing can be moved back and forth. Therefore the stage 3 is usually set at the front side and then moved to the rear side at estimation of the interlock so that the interlock can be evaded. Thus it is possible to evade the occurrence of the interlock and to prevent the deterioration of the processing speed in a pipeline processing system.

Description

[Detailed Description of the Invention] [Summary] Regarding the pipeline processing method used at the instruction processing level of computers, etc., the position of a predetermined stage including operand read processing can be moved back and forth, thereby avoiding interlocks and increasing processing speed. In order to prevent the deterioration of performance, a dummy stage that only passes data is added to the multiple pipeline stages constituting one instruction, and at least a predetermined stage that executes operand read processing and the dummy stage are connected to each other. In addition to making it possible to replace
The predetermined stage position after replacement is located at the rear of the stage execution order, and preferably, when executing a subsequent instruction that depends on the execution result of the preceding instruction or the preceding instruction itself, the predetermined stage and the dummy stage are Preferably, the predetermined stage after the replacement is returned to the position before the replacement upon execution of a subsequent instruction that does not depend on the execution result of the preceding instruction or the preceding instruction itself.

[Industrial application field]

The present invention relates to a pipeline processing method used at the instruction processing level of computers and the like.

-g, as a representative method for speeding up computers,
There is a pipeline processing method in which one instruction is divided into several processing units (pipeline stages) and multiple consecutive instructions are executed in parallel.

[Conventional technology]

FIG. 15 is a conceptual diagram of a conventional pipeline processing method, and in this example, one instruction is divided into four stages for each processing unit.

After executing the ■stage of instruction n in the first processing cycle, the ■stage of instruction n and the ■stage of instruction n+1 are executed in the following j+1th processing cycle, and thereafter, the ■stage of instruction n+1 is executed.
■stage of instruction n in the th processing cycle, instruction n+1
Execute ■ stage of and 1 stage of instruction n+2,
■stage of instruction n in the following i+3rd processing cycle,
The ■stage of instruction n+1, the ■stage of instruction n+2, and the 1st stage of instruction n+3 are executed.

Multiple instructions can be executed in parallel, allowing the computer to operate at high speed.

[Problem to be solved by the invention]

However, in such conventional pipeline processing methods, each stage of the pipeline is an instruction processing unit,
For example, "instruction processing", "decoding processing", "
"Execution processing" is fixed depending on the execution process, so a so-called pipeline interlock (hereinafter simply referred to as "interlock") occurs when a specific instruction is executed, which consumes extra processing cycles. There was a problem that the processing speed decreased.

Here, interlock is a phenomenon specific to pipeline processing, and can be explained as follows.

In other words, when an instruction refers to the execution result of a preceding instruction, if the execution result is not yet finalized, the instruction will refer to old (in other words, incorrect) data that has not yet been finalized. In order to avoid this, the execution of a certain instruction is made to wait until the execution result of the preceding instruction is determined.

For example, when a certain instruction depends on the execution result (load data) of a preceding instruction, execution of the next instruction is made to wait until the load data is finalized. This is generally referred to as a "load data dependent interlock."

Also, in the case of a special instruction that occupies an arithmetic unit for multiple processing cycles (a so-called multi-cycle instruction), execution of the next instruction is made to wait until the instruction releases the arithmetic unit. This is done as follows:
This is called "interlock using multi-cycle instructions."

Note that interlocks vary depending on the implementation (method of realizing the circuit), and are not limited to the above two interlocks.

A specific example of such an interlock will be explained in detail with reference to the drawings. In FIG. 16, I-F is an instruction fetch stage, D is a decode stage, E is an execution stage including operand read processing, and D- F is a data fetch stage, and W is a data write stage.

The n-th instruction is an addition instruction (add), the n+1-th instruction is a load instruction (Load), the n+2-th instruction is an addition instruction (add), and the n+3-th instruction is a subtraction instruction (sub).

Now, assuming that the n+2nd addition instruction is an instruction that uses the execution result (data) of the preceding instruction (n+1), in this case, the data of 71 + l must be near the end of the I>F stage. Since it is not finalized, it is necessary to delay the n-thousand-second instruction in accordance with this finalization timing. For this reason, the instructions from the n+1st onwards are delayed (interlocked) by several cycles (one cycle in the figure).
What is done is done. By doing this, n±2
Correct operand data can be given to the second instruction, resulting in accurate execution results.

However, on the other hand, there is a problem in that the delay cycles are accumulated in proportion to the number of times the interlock occurs, and as a result, the processing speed decreases as a result of extra pipeline processing cycles.

Incidentally, it is also possible to prevent interlocks from occurring in software at the stage of compiler development, but such a method is not preferable in terms of the burden of software development, the occurrence of bugs, and cost.

The present invention was made in view of these problems, and
The purpose of this method is to enable the position of a predetermined stage that includes operand read processing to be moved back and forth, thereby avoiding interlocks and preventing a decrease in processing speed.

[Means for Solving the Problems] In order to achieve the above object, the present invention passes data through a plurality of pipeline stages 1 constituting one instruction, as shown in FIG. dummy stage 2 is added, and at least a predetermined stage 3 that executes operand read processing and the dummy stage 2 are added.
and the predetermined stage position after the replacement is located at the rear of the stage execution order. Preferably, when executing a subsequent instruction that depends on the execution result of the preceding instruction or the preceding instruction itself, The method is characterized in that the predetermined stage and the dummy stage are replaced, and preferably the predetermined stage after the replacement is returned to the position before the replacement upon execution of a subsequent instruction that does not depend on the execution result of the preceding instruction or the preceding instruction itself. It is characterized by

[Operation] In the present invention, a predetermined stage that executes operand read processing is replaced with a dummy stage that is located behind the stage and only allows data to pass through.

Such replacement is performed, for example, when the execution result of a preceding instruction is required at a predetermined stage, or when an instruction including a predetermined stage is dependent on a preceding instruction.

Further, the return of the predetermined stage to its original position is performed when the execution result of the preceding instruction is no longer needed at the predetermined stage, or when the instruction including the predetermined stage no longer depends on the preceding instruction.

Therefore, the arrangement of the pipeline stages can be freely changed according to the interrelationship between the preceding instruction and the following instruction, thereby avoiding the occurrence of intercocks and preventing a decrease in processing speed.

(Example) Hereinafter, the present invention will be explained based on the drawings.

2 to 14 are diagrams showing an embodiment of the pipeline processing method according to the present invention.

First, the principle will be explained with reference to FIGS. 2 to 10. FIG. 2 is a diagram showing a five-stage Guinamink pipeline as a simple example.

The basic format of this pipeline is that after the IF (instruction fetch) stage and the D (decode) stage,
Two execution candidate stages (A, B) are provided, and finally W (
Light) Place and configure the stage.

The two execution candidate stages (A, B) can be changed into several combinations, as shown by format 1 and format 2 in the figure.

This format 1] This formant is the instruction processing format in the normal case, and 3
Divided into two subdivisions. One is to place the E (execution) stage at the front and a dummy stage (a stage where data only passes) at the rear (Formant 1-
1), the other one places the EL/S (load/store address calculation) stage on the front side and the D-F (data fetch) stage on the back side (formant 1-2), and the last One is the one (format 1-3) in which the El, 2 (two-cycle instruction execution) stage is placed in both of the two execution candidate stages, and in both cases, the operand read processing is placed before the two execution candidate stages. The execution stage containing is located.

[Format 2] -4, This format is an instruction processing format when interdependent instructions that cause an interlock appear, or when executing an instruction following a 2-cycle instruction.
Place a dummy stage in front of the two execution candidate stages,
An execution stage including operand read processing is placed at the rear.

That is, there is a plurality of execution candidate stages, and at least a predetermined stage (E
There are two types of instruction processing formats: format 1 in which a dummy stage is placed in front of multiple execution candidate stages and a predetermined stage is placed in the rear. Set.

Simply put, these two types of instruction processing formats are characterized by two points: the addition of a dummy stage, and the ability to replace the dummy stage with a predetermined stage as necessary.

To specifically explain the instruction processing sequence of a pipeline having several types of formats, for example, in FIG.
In the case of a series of instruction processing sequences that are completed with the 11th add instruction, the optimal format according to the instruction is selected as shown in the following table. In addition, add (d
ep) is an addition instruction that uses the execution result of the preceding instruction or load data, 2cycInst is a 2-cycle instruction, and the arrows connecting each instruction represent data bypass.

In the table, that is, in FIG. 3, format 1 as a normal instruction processing format is used in (1).

Case (2) is a case in which load data of the preceding instruction (n + 2) is required, and the format is switched to format 2.

Therefore, the E stage including the data read processing of the preceding instruction is moved to the rear side, and the load data of the preceding instruction can be taken in without any problem. In (2), the same resources (addition/logical operation unit) as the previous instruction are used, so format 2 is used continuously. In (2), format 2 is restored to format 1. That is, in the case where the n+5th instruction does not depend on the preceding instruction, and the resources used in the E stage of the instruction (n+4),
If there is no conflict with the resources used in the E L/S stage of instruction (n+5), format 1 is restored. As a result, by adopting format 2, 1
A given stage that has been shifted back by a processing cycle can be returned to its original position. Since a 2-cycle instruction is processed in step 2, format 2 is adopted again in step 2 that follows.

Therefore, each pipeline stage is arranged with a one-cycle shift for each instruction, and it is possible to avoid the interlock that occurs in the conventional pipeline processing method, for example, in the processing cycles indicated by ■■ in the figure. Moreover, ■ [phase] in the figure
When the processing cycle of H is reached, the adjacent instructions E and E
Since the L/S stages are executed in parallel, it is possible to compensate for the lack of execution stages in the processing cycles of ■■.

As a result, it is as if one instruction was executed per cycle in the entire instruction processing sequence, and pipeline processing can be performed with zero penalty.

Implementation Next, as a specific example, a dynamic pipeline with a basic configuration of six stages and two types of pipeline formats will be disclosed and explained.

FIG. 4 is a block diagram of the main parts of a six-stage dynamic pipeline circuit. In this figure, 10 is an address queue;
11 is an instruction queue, and the instruction queue 11 has five registers, one less than the number of pipeline stages, namely a decode register (DR) and an A register (A-R).
, B register (B-R), and write register (W-R), which are connected in series and connected to the output line tercock detection & multiplexer control circuit (hereinafter referred to as control circuit) 12 of each register. It consists of

The control circuit 12 determines the presence or absence of an instruction that has a data dependency with a preceding instruction or an instruction following a multicycle instruction (that is, predicts the presence or absence of an interface/link) based on the fetch instruction from memory and the contents of each register. ), and outputs a switching operation signal corresponding to the determination result to various multiplexers to be described later.

In addition, Align, WDI, WD2, Wl, W2, W3
, EEL, EE2, EOI and EO2 are registers, M
UX1 is the first multiplexer, MUX2 is the second multiplexer, MUX3 is the third multiplexer, MUX4 is the fourth multiplexer, ALU is the arithmetic logic unit, LD/
ST Adder is a load/store address calculation unit, and LL-L7 is a bypass path.

FIG. 5 is a configuration diagram of the address queue 10. The address queue 10 includes an address generator 13, an F stage address counter (FPC), a D stage address counter (DPC), and an A stage address counter (
APC), B stage address counter (BPC),
C stage address counter (CPC), W stage address counter (wpc), branch destination address calculation unit 14, branch failure return address counter (REPC)
), and a multiplexer 15.

Figures 6(a) to (d) divide the stage arrangement in one processing cycle (see Figure 7) into four cases 1 to 4, and define the control rules for MUX1 to MUX4 determined for each case. FIG. Note that the symbol * in the figure indicates that control is performed on a case-by-case basis depending on the presence or absence of register interdependence (in the case of D stage) or the presence or absence of writing of calculation results or load data (in the case of W stage). , the symbol - indicates that switching is not necessary.

This is a case where two dummy stages and an E stage are lined up in one processing cycle.
The output of L and EOI (b) is selected.

[Case 2] Two dummy stages and E L/ in one processing cycle
This is a case where the S stages are lined up, and the same <EEL and EOI outputs (b) are selected by MUX3.

That is, in case 1 and case 2, data with a passing delay (1 clock) of one register stage (EEL or Eol) is transmitted to the ALU or LD/ST Adder.

[Case 3] This is a case where one dummy stage, E stage and E L/S stage are lined up in one processing cycle, and the output of EEL and EOl (B) is output by MUX2.
is selected, while EE2 and EO are selected by MUX3.
Output 2 (c) is selected.

[Case 41 This is a case in which the E stage and the E L/S stage are lined up in the reverse order of Case 3. MUX2 selects the outputs of EE2 and EO2 (c), while MUX3 selects the outputs of EEL and EOI (ro). ) is selected.

In other words, in case 3, two stages of registers (EE1+EE
2 or EO1+EO2) minute transit delay data is LD
/ST Adder, while in case 4, data with the same delay is passed to the ALU.

FIG. 8 shows the format of the pipeline used in this embodiment. The basic structure is a six-stage pipeline: I-F (instruction fetch) stage, D (decode) stage, A stage, B stage, C stage, and W (write) stage, and three stages A to C are execution candidate stages. It is said that

The execution candidate stage is formatted as 1 depending on its contents.
and format 2.

Format 11 has the E (execution) stage in the first stage and dummy stages in the remaining stages, and the EL/S (load/store address calculation) stage in the first stage. , a DF (data fetch) stage is placed in the next stage, and a dummy stage is placed in the last stage.Formats 1-2 are available.

Formant 2, a dummy stage is placed in the first stage,
Format 2-1 has an E (execution) stage in the next stage and a dummy stage in the last stage, and a dummy stage in the first stage and EL/S (load/store address calculation) in the next stage. Place the stage and place D- on the last stage.
There are two formats: format 2-2 in which an F (data fetch) stage is arranged.

As a prohibited format, a dummy stage is placed in the first two stages of the execution candidate stage, and an E(
Execution) Set the format in which the stage is placed.

Switching between format 1 and formant 2 follows the state transition diagram shown in FIG. That is, (1) when the instruction next to the current load instruction uses the load data of the current instruction (see ■ in FIG. 10), the state is transitioned from format 1 to format 2. (II) If the previous instruction is in format 2 with respect to the current instruction, there is no dependency, and the resources of the execution section are different (see ■ in Figure 10), or the current instruction is If it is a branch instruction (see ■ in Figure 10), format 2
The state transitions from to format 1.

(1) When the instruction following the current load instruction does not use the load data of the current instruction, that is, in cases other than (1) (for example, see ■ in FIG. 5), the state of format 1 is maintained. (IV) When instructions that use the same resource continue, that is, when the previous instruction is format 2 and uses the same resources as the execution part of that instruction (see Figure 12), the format 2 state maintain.

Here, to explain branching, branching in this embodiment is based on the adoption of a delayed branching method, as shown in FIG. 11. Therefore, a penalty occurs due to failure of the branch instruction.

In other words, in the current six-stage dynamic pipeline, if a branch is not taken in the state of format l, a penalty of one cycle occurs (see Figure 12), and in the state of format 2, a penalty of two cycles occurs (see figure 12). (see figure).

In many conventional pipeline systems, the penalty for an untaken branch is limited to one cycle, and in this respect, the number of penalties in this embodiment may seem disadvantageous, but in reality, there is an advantage by avoiding interlocks that depend on load data. The disadvantage of the penalty can be absorbed in one cycle, and no inconvenience occurs.

In other words, if a branch is not taken in the format 2 state, a branch is not taken in a state where one cycle is gained during the state transition from format 1 to format 2.

That is, in FIG. 14, in order to avoid the load data dependent interlock at ■ in the figure, the state transitions from format 1 to format 2, gaining l cycles, and then at ■ in the figure. Considering the worst case where a branch is not taken while the format 2 is still in the state, in this case there will be a penalty of 2 cycles, but
If one cycle worth of the previous gain is taken into account, the penalty is only one cycle after all, which can be the same penalty as in the conventional pipeline system. Moreover, in this case, we have only assumed the worst case, and as long as the branch is not taken in the format 1 state,
The penalty will not exceed 1 because the 1 cycle gained by avoiding the interlock will remain.
Therefore, processing speed can be improved compared to the conventional pipeline method.

Note that in the above embodiment, a dummy stage is added to the simple pipeline configuration to avoid "load data dependent interlock," but this is not limited to this. For example, depending on the implementation, multi-cycle instructions may be Interlock caused by two cycle instructions can be avoided. Furthermore, by increasing the number of dummy stages, interlocking of other multi-cycle instructions such as 3-cycle instructions and 4-cycle instructions can be easily accommodated.

; Effects of the Invention] According to the present invention, as described above, the position of the predetermined stage including operand read processing can be moved back and forth. In some cases, this can be avoided by positioning the predetermined stage on the rear side, and a decrease in processing speed can be prevented.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIGS. 2 to 14 are diagrams showing an embodiment of the pipeline processing method according to the present invention, and FIG. 2 is a conceptual diagram showing the format of the five-stage pipeline. Part 3 is the basic operation diagram of the 5-stage pipeline, Figure 4 is the configuration diagram of the 6-stage dynamic line circuit, Figure 5 is the configuration diagram of the address queue, and Figure 6 is a diagram of each case. Figure 7 is a diagram showing the basic rules for multiplexer control, Figure 8 is a conceptual diagram showing the former of the six-stage pipeline, and Figure 9 is a diagram of the processing former. State transition diagram, 10th
Figure 11 is a diagram showing the basic operation of the 6-stage pipeline, Figure 11 is a diagram showing the branches of the delayed branch method, and Figure 12 is a diagram showing the branch failure (1 cycle penalty
Figure 3 shows the branch not taken (two-cycle penalty). Figure 14 shows the branch untaken (two-cycle penalty). Figures 15 and 16 are diagrams showing conventional examples. Figure 15 shows the basic concept of pipeline processing. Figure 16 is a diagram explaining the pipeline interlock. 1...Pipeline stage, 2...
Dummy stage, 3... Predetermined stage. Stage execution order Principle of the present invention

Claims (3)

[Claims] (1) Adding a dummy stage that only allows data to pass through a plurality of pipeline stages constituting one instruction, and making it possible to replace the dummy stage with at least a predetermined stage that executes operand read processing, A pipeline processing method characterized in that a predetermined stage position after replacement is located at the rear of the stage execution order. (2) The pipeline processing method according to claim 1, wherein the predetermined stage and a dummy stage are replaced when executing a subsequent instruction that depends on the execution result of the preceding instruction or the preceding instruction itself. (3) The pipeline processing method according to claim 1 or 2, characterized in that upon execution of a subsequent instruction that does not depend on the execution result of the preceding instruction or the preceding instruction itself, the predetermined stage after replacement is returned to the position before replacement. .