JPH04104540A - Multiplexer - Google Patents

Abstract

PURPOSE:To preferentially output information or a bus requester which has information having the highest priority level by dynamically changing the precedence for bus arbitration in accordance with contents of information which each bus requester will send. CONSTITUTION:Each of bus requesters 1a to 1c is provided with a memory control part 9 which determines a priority level corresponding to contents or a data pattern of held information and outputs the determined priority level at the time of outputting a bus request in accordance with the held information storage volume, and a bus arbiter 2 is provided with a precedence control part which determines the precedence of bus requesters 1a to 1c in accordance with priority levels sent from bus requests 5a to 5c. Thus, the bus arbiter 2 outputs information held in bus requesters 1a to 1c to a multiple bus in accordance with priority levels of these information to transfer information having the highest priority level to a multiplexing part 3 even in the case of contention among bus requests 5a to 5c.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplexing device that can preferentially output information of a bus requester having information with the highest priority.

[Conventional technology]

Multiplexing methods used in communications include time division multiplexing, which multiplexes information in a time-division manner, such as circuit switching, and statistical multiplexing, which multiplexes information asynchronously at arbitrary timings when information is generated.

Statistical multiplexing methods include, for example, packet multiplexing and asynchronous transfer mode (ATM).
answerMode), which uses the line only when information is generated as described above, and has the advantage of being efficient. However, since each tries to output information asynchronously, the requests (bus requests) are arbitrated (
A bus arbiter is required.

The concept of bus arbitration is to arbitrate between multiple bus requesters requesting to acquire a common bus.
However, there are two specific reasons.

One is to connect the CPU bus on the rCPU board to the CPU or D
In this case, CP
U and DMAC become bus requesters. The other is "each board takes over a common external bus that connects each board"
In this case, each board (block) attempting to send information becomes a bus requester. Here, we will discuss the latter.

FIG. 6 is a block diagram showing a conventional multiplexing device. In the figure, 18 to 1c are a plurality of bus requestors that output information, and 21 is a bus request from each #1 bus requester 1a to #3 bus requester IC. a bus arbiter that arbitrates the
3 is a multiplexing unit that multiplexes information, 4 is each bus requester 1
This is a multiplex bus common to a to 1c. Note that 5a to 5G represent bus requests from each bus requester 1a to 1c to bus arbiter 21, and 6a to 6c represent bus request approval from path arbiter 21 to each bus requester 18 to 1c. It shows the lotus ground. Further, each of the bus requestors 1a to 1c may have the same configuration, and when there is no particular need for distinction, the bus requestors 1a to 1c may have the same configuration.
, Bus Request 5, and Bus Gran Toro.

FIG. 7 is a block diagram showing the configuration of the main parts of the bus requester 1. In the figure, 8 is a memory for temporarily storing information to be sent and absorbing instantaneous congestion on the multiplexed bus 4;
Reference numeral 1 denotes a memory control unit that controls the memory 8. This memory control unit 91 turns on/off the bus request 5 based on the amount of information stored in the memory 8, and controls the sending of information to the multiplex bus 4 based on the path grand toro.

FIG. 8 is a detailed configuration diagram of a bus arbiter such as the local bus arbiter (SAB82200) manufactured by Siemens.
Indicated by CBRL. ).

68 to 6c are bus grounds (in the figure, ABGL,
BB GL , CB GL te is shown. ), and 1°a to 10f are D-type flip-flops, lla to
11f is a gate. In this example, bus request 5
and Pass Grand Toro are low significant signals, which are turned on when they are logically low.

Next, the operation will be explained. For example, information input to the #1 bus requester 1a is first stored in the memory 8. When the memory control unit 91 confirms that the information on the unit of transmission to the multiplex bus 4 has been accumulated in the memory 8, it turns on the bus request 5a, which is a bus request signal, to the bus arbiter 21.

Here, if only one bus requester 1
Since the path arbiter 21 cannot occupy the multiplexed bus 4, the #2 bus requester 1b and the #3 bus requester lc cannot
Make sure that it is not occupied, then turn on pass grand low a. The memory control unit 91 of the #1 bus requester 1a instructs the memory 8 to send information to the multiplex bus 4 in response to the turning on of the path grandro a. In this way, the information sent to the multiplex bus 4 is sent to the line via the multiplex section 3.

In the path arbiter 21 shown in FIG.
arbitration is performed. This example is an example of a fixed priority system in which #1 bus requester 1a has the highest priority, and #2 bus requester 1b and #3 bus requester 1c have lower priorities in this order.

As a function of the bus arbiter 21, the bus request 5 is suppressed by gates lid to 11f, respectively, in order to ensure that no one returns a pass grand toro to only one bus requester 1. Furthermore, in order to prioritize when a plurality of bus requests 5 are turned on at the same time, the bus request 5a suppresses the bus request 5b and the bus request 5c, and the bus request 5b suppresses the bus request 5c.

When a large amount of information is input to each of the bus requestors 18 to 1c, it is stored in the memory 8 temporarily, and the order of priority is #1 bus requestor 1a, #2 bus requestor 1b, and #3 bus requestor 1c according to a fixed priority order. The information in the memory 8 is sent to the multiplex bus 4.

[Problem to be solved by the invention]

Since the conventional multiplexing device is configured as described above,
The priority of hash arbitration is always fixed regardless of the content of the information to be sent to each bus requester 1a to IC or the multiplex bus 4, and the bus requester 1 with the higher priority often acquires the multiplex bus 4. Even if the lot requester 1, which has a low priority, tries to send more urgent information to the multiplex bus 4, there is a problem in that it is difficult to acquire the multiplex bus 4.

In particular, when applied to a communication system, etc., the degree of urgency when transmitting information to a line varies depending on the content of information held by each bus requester 18 to 1c, and the priority order is not fixed. However, there were issues such as the inability to perform efficient communication.

This invention was made to solve the above-mentioned problems, and it dynamically changes the priority order of bus requesters according to the content (priority) of the information that each bus requester is trying to send. To obtain a multiplexing device capable of transmitting high priority information more quickly by allowing a bus requester that is about to transmit high priority information to acquire a bus preferentially.

[Means to solve the problem]

The multiplexing device according to the present invention determines a priority for each bus requester according to the content and data pattern of the information held, and outputs a bus request according to the amount of information stored. , a memory control section that also outputs the determined priority is provided, and the hash arbiter is provided with a priority control section that determines the priority of each bus requester according to the priority sent out from the bus request.

[Effect]

The bus arbiter in this invention outputs the information held by each bus requester to the multiplex bus according to the priority of the information held by each bus requester, even if bus requests conflict, and hands over the information with the highest priority to the multiplexing unit. make it possible.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. Note that the same reference numerals are used for the same or equivalent parts as in the conventional example, and the explanation thereof will be omitted.

FIG. 1 is a block diagram showing a multiplexing device according to an embodiment of the present invention. In the figure, 7a to 7C are information stored in the memory 8 in each bus requester 1a to 1c (next This shows a signal called priority for notifying the bus arbiter 2 of the priority of the information (information that exists).

Note that when no particular distinction is required, priority 7 is written.

FIG. 2 is a block diagram showing the main structure of the bus requester 1 in this embodiment, and priority 7 is output from the memory control section 9. In FIG. When the memory control unit 9 recognizes that the information for the sending unit has been accumulated in the memory 8, it turns on the bus request 5, as in the conventional case, and also requests information based on the content and data pattern of the information to be sent. Then, according to the predetermined priority order of the information, the priority of the information is notified to the bus arbiter 2 using priority 7. In this example, priority 7 indicates the lowest priority when bus request 5 is off.

FIG. 3 is a detailed blue block diagram of the bus arbiter 2 in this embodiment, and 12 is a priority control unit that dynamically changes the priority order based on priorities 7a to 7c. This priority control unit 12 controls each priority 7a to 7c (in the figure,
Indicated by APRIH, BPRIH, and CPRIH. ) based on each output 13a-13b (in the figure, ABRG
T.L.

Indicated by BBRGTL. ), and this output 13a, 1
3b to control the gates 1la to 11b, the bus requester 1 is about to send out the information with the highest priority (has been notified of the highest priority).
It gives priority to

FIG. 4 is a detailed configuration diagram of the priority control section 12 in the above embodiment, and 12a to 12y are gates. Each of the priorities 7a to 7c is composed of two signal lines, and can indicate four levels of priority. For priority 7a, (Al, AO) = (1, 1)
(7) When the highest priority is (Al, AO) = (
The priority decreases in the order of 1, O), (0°l), and (0, Q). The same applies to priorities 7b and 7c.

FIG. 5 is an explanatory diagram showing an example of a method for determining the priority of information in the bus requester 1, and this example is based on the assumption that the type of data that the bus requester 1 sends to the multiplexed bus 4 is an LAPD frame. be. In this example, the priority of information is determined depending on the type of frame and the presence or absence of poll/final bits, and the memory control unit 9 changes the value of priority 7 based on this.

Next, the operation will be explained. Other than the sequence for determining the priority of bus requester 1, that is, the flow of exchanging bus request 5 and bus grandro and transmitting information via multiplex bus 4 and multiplex unit 3 is the same as in the conventional example. It is.

The difference from the conventional example is that the bus requester 1 determines the priority of the information based on the information that it is going to send next, and the bus arbiter 2, which has been notified of the priority of the information from the bus requester 1, determines the priority of the information. The priority order of the lotus requester 1 is changed according to the value of the lotus requester 1, and its operation will be explained below.

When the information for the sending unit is accumulated in the memory 8, the memory control unit 9 of each of the lot requesters 18 to IC sends bus requests 5a to 5, which are bus request signals, to the bus arbiter 2.
C is turned on, and the information to be sent to the multiplex bus 4 is analyzed, and the priority of the information is determined according to a predetermined priority order, for example, as shown in FIG. The bus arbiter 2 is notified using priorities 7a to 7C. When the bus arbiter 2 receives bus requests 5 from multiple bus requesters 1, it compares the priorities of the information indicated by the priority 7 and determines whether another bus requester 1 occupies the multiplexed bus 4. After confirming that there is no such thing, the path grandro is turned on for the bus requester 1 which is about to send out the information with the highest priority.

For example, #2 bus requester 1b has priority 7b.
(Al, AO) = (1, 1), bus request 5b is significant, #1 bus requester 1a sets priority 7a to (Al, AO) = (1, O), bus request 5a is significant. Sometimes, the #2 bus requester 1b should occupy the multiplexed bus 4. At this time, if the multiplex bus 4 is not occupied by anyone,
Since each of the pass grand lows a to 6C is at a high level, the outputs of the gates 12a to 12c are all at a high level. Therefore, for priority 7a, only gate 12e is at low level, and for priority 7b, only gate 12h is at low level. Further, the output of the gate 120 becomes low level. Therefore, gate 12
The output of e is blocked by the output of gate 120 at gate 12r. Therefore, the output 13 of gate 12x
a is at a high level. On the other hand, since the output of the gate 12h passes through the gate 12y, the output 13b of the gate 12y
is low level. Then, in what is shown in FIG. 3, the bus request 5a is blocked by the gate lla,
Bus request 5b passes through gate Ilb. Therefore, path grand tro b is output to #2 bus requester 1b. Other combinations of priorities 7 can be considered in the same way.

As a result of comparing the priorities of information from each bus requester 1a to IC, if they are equal, the priority is #1 bus requester 1a, #2 bus requester lb, and 33 bus requester IC, as in the conventional example. The order is as follows.

Further, although an example of a method for determining the priority of information in the bus requester 1 is shown in FIG. 5, the priority is not limited to this method, but any method may be used to determine the priority.

Furthermore, the priority of information and the method of determining the priority may be changed for each bus requestor 18 to 1c, and there may be a bus requester 1 with the highest priority, or a bus requester A is always higher than a bus requester B. A fixed priority method may be adopted in some cases, such as having a higher priority.

In the above embodiment, the number of bus requesters 1 is three, but any number may be used as long as it is plural, and there is no limit to the number of signal lines constituting the priority.

〔Effect of the invention〕

As described above, according to the present invention, the multiplexing device is configured to dynamically change the priority order during bus arbitration according to the content of information that each lot requester is trying to send. Even if a bus requester competes with other bus requesters when trying to send out more urgent information or information with a higher priority, any bus requester can acquire the bus preferentially.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a multiplexing device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the main configuration of a bus requester, FIG. 3 is a detailed configuration diagram showing a bus arbiter, and FIG. 4 is a priority diagram. FIG. 5 is an explanatory diagram showing an example of a method for determining the priority of information in a bus requester; FIG. 6 is a block diagram showing a conventional multiplexing device; FIG. 7 is a diagram showing a conventional bus FIG. 8 is a block diagram showing the configuration of the main parts of the requester, and FIG. 8 is a detailed configuration diagram showing the conventional bus arbiter. 1.1a to 1c are lot requesters, 2.21 is a bus arbiter, 3 is a multiplex unit, 4 is a multiplex bus, 5.5a to 5c are bus requests, 6, 6a to 6c are bus grounds, 7, 7
a to 7c are priorities, 8 is a memory, 9.91 is a memory control unit, and 12 is a priority control unit 6. In FIG. 5, the same reference numerals indicate the same or equivalent parts. Agent Masu Oiwa, Figure 4, Figure 5, Figure 8

Claims (1)

[Claims] A plurality of bus requesters each having a memory that temporarily stores information to be sent to a multiplexed bus, and bus request signals outputted from these bus requesters are arbitrated according to priorities, and a bus request approval signal is output to the bus requester with the highest priority. In the multiplexing device, each bus requestor includes a bus arbiter that inputs and multiplexes information sent by the bus requester to the multiplex bus, and each bus requester inputs and multiplexes information sent to the multiplex bus. the bus arbiter further comprises a memory control unit that determines a priority according to attributes such as, and outputs the bus request signal requesting occupancy of the multiplexed bus based on the amount of information stored in the memory together with the priority; , a multiplexing device comprising: a priority control section that determines the priority order of each of the bus requesters according to the priority sent out from the bus requester.