JPH04102300A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To suppress the fluctuation of an output voltage in the burn-in area of a voltage conversion circuit by providing plural fuse means at the voltage conversion circuit, and setting the cutoff state of the fuse means artificially. CONSTITUTION:The voltage conversion circuit VC includes a reference potential generation circuit VRG, a fuse circuit FC, and a reference potential generation circuit VLG, and an internal source voltage generation circuit IVG, and an external source voltage VCC is supplied to those circuits. The unit fuse circuits UFC0-UFC5 of the circuit FC include the fuse means 1 cut off selectively. The cutoff state of the fuse means F1 of corresponding unit fuse circuits UFC0-UFC5 can be generated artificially by coupling test pads PFS0-PFS5 with the external source voltage VCC at the circuit FC. Trimming can be performed by setting the cutoff state of the means F1 selectively by the reference potential VL in the burn-in area. Therefore, the value of the internal source voltage in the burn-in area can be approached to a central value, and only comparatively low fluctuation EC can be displayed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and relates to a technique that is particularly effective when applied to, for example, a dynamic RAM (random access memory) having a built-in voltage conversion circuit. It is something.

[Conventional technology]

As dynamic RAM and other devices become more highly integrated and have larger capacities, circuit elements become increasingly finer. As a means of compensating for the drop in breakdown voltage, the value of the internal power supply voltage within the chip is reduced to, for example, +3.3■. A method has been adopted to do so.

In this case, the value of the external power supply voltage supplied from the outside is, for example, +5. Since it is effective to standardize and unify Ov, a dynamic RAM or the like is provided with a voltage conversion circuit that converts this external power supply voltage to form the stable internal power supply voltage.

On the other hand, in dynamic RAMs such as those mentioned above, MOSFETs (metal oxide semiconductor field effect transistors, in this specification, MOSFETs are used to provide insulated gate electric field In order to detect early the 11111 effect transistors, etc., for example, a so-called burn-in (aging) test is performed in which an accelerated test is performed with the 11111 voltage and ambient temperature abnormally high. At this time, the value of the internal power supply voltage is increased until just before normal circuit elements are destroyed.
This increases the error detection rate and test efficiency of the burn-in test.

A dynamic RAM having a built-in voltage conversion circuit is described in, for example, Japanese Patent Laid-Open No. 110225/1983.

[Problem to be solved by the invention]

Dynamic type R like the one above with a built-in voltage conversion circuit
In AM, etc., the value of the internal power supply voltage is, as mentioned above,
Even if the value of the external power supply voltage fluctuates, it is assumed to remain approximately constant. Therefore, even if the external power supply voltage is increased to perform a burn-in test, the internal %#! The heavy pressure does not change, making it impossible to carry out the desired accelerated test.To deal with this, the inventors of the present application developed a voltage conversion circuit having output characteristics as shown in FIG. 3 prior to the present invention. was developed.

That is, in the normal region NM where a dynamic RAM or the like normally operates, the output signal of the voltage conversion circuit VC, that is, the internal power supply heavy pressure VCLO value, is a constant value such as +3.3■, regardless of the external power supply voltage VCLO value. Voltage VCLN
It is said that Then, when the external 14 source voltage VCL is further increased and reaches the so-called burn-in region BT, the internal power source voltage VCL is increased in proportion to the external power source voltage VCL.

As a result, the internal power supply voltage VCL can be set to a predetermined high voltage VCLB and a desired burn-in test can be performed by simply increasing the external power supply voltage VCL to a predetermined value, as in the case of conventional dynamic RAMs. It is something that can be done.

However, the inventors of the present invention have further revealed that these dynamic RAMs still have the following problems. That is, in the voltage conversion circuit having the output characteristics shown in FIG. 3, the external power supply voltage VCL in the burn-in region BT and the internal As is well known, the threshold voltage of a MOSFET fluctuates relatively largely depending on the manufacturing process and ambient temperature. Therefore, even if the external power supply voltage VCL is set to a predetermined design value, the value of the internal power supply voltage VCL is j83
It exhibits a relatively large fluctuation EO as shown by the dotted line in the figure. This reduces the error detection rate of the burn-in test, that is, the screening accuracy.
In addition to causing a decline in AM reliability, dynamic RA
This results in a decrease in testing efficiency for M, etc., and a decrease in yield due to so-called overkill.

An object of the present invention is to suppress output voltage fluctuations in a burn-in region of a voltage converter circuit built into a dynamic RAM or the like and having a burn-in region.

Another object of the present invention is to improve the screening accuracy of a burn-in test of a dynamic RAM having a voltage conversion circuit, and to improve the reliability of the dynamic RAM.

A further object of the present invention is to improve the testing efficiency and yield of dynamic RAMs and the like, and to reduce their costs.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A typical summary of the inventions disclosed in this application is as follows.

In other words, the voltage converter is built into a dynamic RAM and has a so-called burn-in region in which the output voltage, that is, the value of the internal power supply voltage is increased in proportion to the external power supply voltage during accelerated test operation, is disconnected in a predetermined combination. A plurality of fuse means are provided for selectively switching the value of the internal power supply voltage in the burn-in region.

Further, a pseudo-cutting means is provided which can pseudo-disconnect these fuse means, and furthermore, the value of the internal power supply voltage can be monitored via a predetermined external terminal in a predetermined test mode.

[For production]

According to the above-described means, it is possible to efficiently and accurately trim the value of the internal power supply voltage in the burn-in region, and to suppress fluctuations due to manufacturing variations or the like. As a result, the error detection rate of the burn-in test, that is, the screening accuracy can be improved, and damage to normal circuit elements due to so-called overkill can be reduced, and product yield can be increased. As a result, it is possible to reduce the cost of the dynamic RAM and the like while increasing its reliability.

〔Example〕

FIG. 10 shows a dynamic 7 type R to which this invention is applied.
A block diagram of one embodiment of an AM is shown. Further, FIG. 9 shows a block diagram of an embodiment of the voltage conversion circuit VC built in the dynamic RAM of FIG.
Figure 1, 613! (l, Figures 7 and 8 include the 9th
Reference potential generation circuit VL included in voltage conversion circuit VC shown in the figure
A circuit diagram of a practical example of G, reference potential generation circuit VRG, fuse circuit 1) FC, and internal power supply voltage generation circuit IVG is shown, respectively. Further, FIG. 2 shows an example of a partial equivalent circuit diagram of the reference potential ordering circuit VLG of FIG. 1, and FIG. 3 shows an output characteristic diagram of one embodiment thereof. Based on these figures, an overview of the configuration, operation, and characteristics of the dynamic RAM and voltage conversion circuit of this embodiment, as well as its features, will be described.

Note that the circuit elements in WI1, FIG. 2, and FIGS. 6 to 8 and the circuit elements constituting each block in FIGS. 9 to 11 are not particularly limited by known semiconductor integrated circuit manufacturing techniques. However, 1 like single crystal silicon
formed on a single semiconductor substrate. In the circuit diagrams below, a MOSFET (metal oxide semiconductor field effect transistor) is indicated with an arrow at its channel (back gate).

In this specification, MOSFET is a general term for insulated gate field effect transistors) is a P-channel type, and is shown to be distinguished from an N-channel MO5FET, which is not indicated by an arrow.

Although not particularly limited, the dynamic RAM of this embodiment has a relatively large storage capacity, the circuit elements centering on the memory cells are extremely miniaturized, and the withstand voltage thereof is low.

For this reason, the internal circuit of the dynamic RAM including the memory array uses an internal 1itp voltage VCL of +3.3 V as its operating power source, although this is not particularly limited. and,
Although not particularly limited to dynamic RAM, +
A voltage conversion circuit VC that forms the internal power supply voltage VCL based on the external power supply voltage VCC of S and OV is built-in.

As a result, it is possible to reduce the power consumption of the dynamic RAM and unify the external power supply voltage while preventing voltage breakdown of the circuit elements.

In FIG. 10, the dynamic RAM adopts a so-called shared sense system, although it is not particularly limited, and has a basic configuration of a pair of memory arrays MARYL and MARYR arranged with a sense amplifier SA in between.

Memory arrays MARYL and MARYR include a plurality of word lines arranged in parallel in the vertical direction in the figure, a plurality of sets of complementary focus lines arranged in parallel in the horizontal direction, and lines of these word lines and complementary focus lines. Each includes a large number of dynamic memory cells arranged in a grid pattern at intersections.

Although not particularly limited, the word lines forming memory arrays MARYL and MARYR are coupled to corresponding row address decoders RADL and RADR, respectively, and are alternatively brought into a selected state. Row address decoder RADL
Although not particularly limited, complementary internal address signals axQ to axi-1 (where, for example, non-inverted internal address signal axO and inverted internal address signal axOB) are expressed as a complementary internal address signal axO, and the inverted internal address signal a
xOB (expressed by adding B to the end of the signal name, the same applies hereinafter) is commonly supplied, and the timing generation circuit T
Timing signals φxi and φXr are supplied from G, respectively. In addition, the row address buffer RAB is supplied with an X address signal AXO via address input terminals AO to Ai.
~AXi is supplied in a time-division manner, and the refresh address counter RFC generates a Freso share address signal arO~
ari is supplied. Furthermore, row address buffer R
AB is supplied with timing signals φar and φrf from the timing generation circuit TG, and the refresher address counter RFC is supplied with a timing signal φrc.

The row address decoder RADL receives the timing signal φx
By setting J to a high level, it is selectively put into an operating state. In this operating state, the row address decoder R
ADL decodes the complementary internal address signals axQ to axi-1 and selectively sets the corresponding word line of the memory array MARYL to a high level selected state. Similarly, the row address decoder RADR receives the timing signal φX'
is selectively activated by setting it to a high level,
According to complementary internal address signals axO to -axi-1, corresponding word lines of memory array MARYR are alternatively set to a high level selected state.

Row address buffer RAB is a dynamic RAM
When is in the normal operation mode and the timing signal φrf is set to low level, the X address signals AXO to AX are supplied in a time-sharing manner via the address input terminals AO to A1.
i is taken in according to the timing signal φar, and when the dynamic RAM is in the refresh mode and the timing signal φrf is set to high level, the refresh address signals arQ to ari supplied from the refresh address counter RFC are taken in.

Complementary internal address signals xO to xi are formed based on these row address signals.

Of these, the most significant bit of the complementary internal address signal xi
are supplied to the timing generation circuit TG, and the other complementary internal address signals axO to axi-1 are commonly supplied to the row address decoders RADL and RADR, as described above.

When the dynamic RAM is placed in the refresh mode, the refresh address counter RFC performs a walk-through operation in accordance with the timing signal φrc, forms the refresh address signal arp-ari, and supplies it to the row address buffer RAB.

On the other hand, the complementary bit lines constituting the memory array MARY are coupled to the corresponding unit amplifier circuits of the sense amplifier SA via the corresponding shared MO3FETs of the sense amplifier SA. The complementary input/output nodes of these unit amplifier circuits are further coupled to a complementary common data line CD via a pair of corresponding switches MO3FET. The timing signal φsl or φsr is commonly supplied to the shared MO3FETs of the sense amplifier SA, and the internal power supply voltage VCL is supplied to the unit amplifier circuit via a pair of driving MO3FETs that are selectively turned on according to the timing signal φpa. and ground potential are selectively supplied. Each pair of switches MO3FET of the sense amplifier SA is supplied with a corresponding column selection signal from the column address decoder CAD. Column address decoder CAD
is supplied with the complementary internal address signal yO-yi of i+l pin from the column address buffer CAB, and is supplied with the timing signal φy from the timing generation circuit TG. The column address buffer CAB also receives a Y address signal AYO via address input terminals AO to Ai.
-AYi is supplied in a time-division manner, and the timing generation circuit T
A timing signal φac is supplied from G.

The shared MO3FETs of the sense amplifier SA are selectively and all at once turned on by setting the corresponding timing signal φsl or φsr to a high level. Thereby, the complementary bit lines of memory array MARYL or MARYR are selectively connected to the complementary input/output nodes of the corresponding unit amplifier circuits of sense amplifier SA.

The unit amplification circuit of the sense amplifier SA receives the timing signal φ
When pa is set to high level and internal power supply voltage VCL and ground potential are supplied via the drive MO5FET, it is selectively put into an operating state. In this operating state, each unit amplifier circuit of the sense amplifier SA is connected to the memory array MARY.
A minute read signal outputted from a plurality of memory cells coupled to a selected word line of L or MARYR via a corresponding complementary bit line is amplified and made into a high level or low level binary read signal.

As described above, each unit circuit of the sense amplifier SA further includes multiple pairs of N-channel type switch MOSFETs, one of which is connected to the complementary input/output node of the corresponding unit amplifier circuit of the sense amplifier SA. The other is connected to a complementary common data line CD.
are commonly coupled to the non-inverting or inverting signal line of. In addition, the commonly coupled gates of each pair of switch MO3FETs have
Corresponding column selection signals are supplied from a column address decoder CAD, which will be described later. These column selection signals are normally all set to low level, and when the dynamic RAM is in the selected state, the Y address signal A
It is alternatively set to high level according to YO=AYi.

The switch MO5FET of each pair of sense amplifier SA is selectively turned on when the corresponding column selection signal is alternatively set to high level, and the complementary input/output node of the corresponding unit amplifier circuit and the complementary common data edge are selectively turned on. Selectively connect standing.

Column address decoder CAD receives timing signal φy
is set to a high level, thereby being selectively put into an operating state. In this operating state, column address decoder C
AD decodes complementary internal address signals ayQ to ayi and selectively sets the corresponding column selection signal to high level.

Column address buffer CAB has address input terminal A.
The Y address signals AYO to AYi supplied in a time-division manner via O to Ai are taken in and held in accordance with the timing signal φac. Furthermore, complementary internal address signals yO to yi are formed based on these Y address signals and supplied to the column address decoder CAD.

Complementary common data line CD is coupled to main amplifier MA. The main amplifier MA has a data input cover sofa DIB.
A complementary write signal WD is supplied from the output signal WD, and its output signal is a complementary read signal or data output signal WD.
B is supplied. The input terminal of the data input buffer DJH is coupled to the data input terminal Din, and the output terminal of the data output buffer DOB is coupled to the data output terminal pout. Main amplifier MA is supplied with timing signals φW and φr from timing generation circuit TO, and data output buffer DOB is supplied with timing signal φOe.

The main amplifier MA forms a predetermined write signal based on the complementary write signal WD supplied from the data input buffer sofa DIB when the dynamic RAM is selected in the write mode and the timing signal φW is set to a high level. , write to the selected memory cell of the memory array MARYL or MARYR via the complementary common data @CD, and when the dynamic RAM is in the selected state in the read mode and the timing signal φr is set to high level, the memory array MARY L or MARY
Complementary common data line -〇D from the selected memory cell of R
The read signal outputted via the read signal is further amplified and transmitted to the data output buffer DOB as a complementary read signal RD.

Data input cover sofa DIB is dynamic RAM7
! 1<When selected in the write mode, a complementary write signal -WD is formed based on the write data supplied via the data input terminal Din, and the main amplifier M
Supply to A.

The data output buffer DOB is a dynamic RAM#
<Selected state in M extraction mode and timing signal φO
When e is set to high level, a predetermined output signal is formed based on the complementary read signal R2D supplied from the main amplifier MA, and is output to the outside via the data output terminal [) out.

Incidentally, in the dynamic RAM of this embodiment, an N-channel MO3FET Q79, which receives an internal control signal tvo at its gate, is provided between the internal power supply voltage supply point VCL and the data output terminal Dout, although this is not particularly limited. This internal control signal tvo is not particularly limited, but the column address strobe signal CASB and write enable signal WEB are the row address strobe signal R.
So-called WCBR which is set to low level prior to ASH
When the cycle is executed and predetermined bits of the address signals AO to At are set to high level at the same time, the dynamic RAM is selectively set to high level when the dynamic RAM is placed in a predetermined test mode. This high level is internal 1! & is formed by boosting the source voltage VCL, and from this internal power supply voltage VCL at least the above MO3FETQ7
The voltage is set to be a high voltage that is higher than the threshold voltage of 9. internal is
When the double signal vo is set to high level, MO3FETQ
79 is turned on, and the internal power supply voltage VCL is outputted via the external terminal, that is, the data output terminal Dout.

As a result, the internal power supply voltage VCL can be trimmed and evaluated efficiently without adding any special external terminals, and the number of man-hours required for testing a dyna-type RAM can be reduced.

Although not particularly limited, the timing generation circuit TG receives a row address strobe signal RASB and a column address strobe signal CA which are externally supplied as activation control signals.
Forming the above various timing signals and internal control signals based on SB and write enable signal WEB, complementary internal address signal axt of the most significant bit supplied from row address buffer RAB, and address signals AO to Ai, Supplied to each circuit of the dynamic RAM.

Although not particularly limited, the voltage conversion circuit VC is supplied with an external power supply voltage CC via a power supply voltage supply terminal VCC, and is supplied with a timing signal φvc from a timing generation circuit TG. Here, the external power supply voltage ■CC is +5.0■, although not particularly limited, and the timing signal φVC
is selectively set to high level while the dynamic RAM is in the selected state. The external power supply voltage vCC is not particularly limited, but may be a high voltage internal power supply voltage vCC,
For example, row address buffer RAB, column address buffer CAB, and data input buffer sofa D I B
It is supplied to input/output circuits such as the output cover and sofa DOB.

The voltage conversion circuit VC includes, but is not particularly limited to, a reference potential generation circuit VRG, as shown in the block diagram of FIG.
These circuits include the fuse circuit FC, the reference potential generation circuit VLG, and the internal voltage source voltage generation circuit IVG.
The external 1!7i source voltage CC is supplied. Test control signals PF50 to PF55 are supplied to the fuse circuit FC via six test pads, although not particularly limited thereto, and the output signals, that is, internal signals FNO to FN7 and FBO to FB7, are supplied to the reference potential generation circuit VLG. supplied to The reference potential generation circuit VLG is further supplied with reference potentials VRN (first reference potential) and VRB (second reference potential) from the reference potential generation circuit VRG, and the output signal, that is, the reference potential VL, is generated from the internal power supply voltage. Circuit I
Supplied to vG. The internal power supply voltage generation circuit IVG includes
Further, the timing signal φvc is supplied, and its output signal, that is, the internal power supply voltage VCL is of the dynamic type R
It is supplied to each AM circuit.

Here, the reference potential ordering circuit VRG of the voltage conversion circuit VC is not particularly limited, but as shown in FIG.
Equipped with RGB.

Among these, the bias circuit BC is not particularly limited, but
Three P-channel MO3FETQ17 provided in series between external power supply voltage VCC and circuit ground potential
Q19 and one N-channel MO3FET Q67. MOSFETQ1? and Ql8 and Q
MOSFET QI 67 has a diode form by having its gate and train commonly coupled, and MOSFET QI 9 is always turned on by having its gate coupled to the ground potential of the circuit. This allows MOSFETQ17 and Q
As the gate voltage of IB and Q67, these MO
Predetermined bias voltages VBI to VB3 set by the source-drain voltages, that is, the threshold voltages of the SFETs are obtained.

On the other hand, the reference potential generation circuit VR (, N is not particularly limited or may be three P-channel MO3FETQ provided in series between the external power supply voltage CC and the ground potential of the circuit).
20~Q22 and one N-channel MO3FETQ68
and another P-channel MO5FE provided in parallel with the MO3FETs Q22 and Q68.
Here, MOSFETQ23 is a high threshold voltage type MOSFET, and its threshold voltage is higher than that of a normal P-channel MO3 such as MO3FETQ22.
Approximately twice the FET threshold voltage VTMP, or 2VTM
It is considered to be P.

The gate of MOSFETQ2D is connected to the bias circuit B mentioned above.
Bias voltage VBI is supplied from C, MO3FETQ
Bias voltages VB2 and VB3 are supplied to the gates of 21 and Q6B, respectively. Also, MO3FETQ2
2 and Q23 have their gates and drains commonly coupled to form a diode, and MO3FETQ22
The commonly coupled drain potential of Q6B and Q6B is the output signal of this reference potential generation circuit VRGN, that is, the reference potential VR
It is supplied as N to the subsequent reference potential generation circuit VLG.

In the reference potential generation circuit VRGN, MOSFETQ2
The current available through MOSFET Q
MO5FETQ22 and Q2 due to the current limiting action of 68
It is divided equally into 3. For this reason, MO5FETQ22
The source-drain voltage of MOSFETQ23 becomes approximately its threshold voltage VTor, and the source-drain pressure of MOSFETQ23 also becomes approximately its threshold voltage 2VTHP. As a result, the drain voltage of MO5FETQ22, that is, the reference potential VRN, becomes approximately +VTHP. In this example, a P-channel MO5FET including MOSFET Q22
Although the threshold voltage VTNP is not particularly limited to WiJ,
The voltage is about 0.9V, and the reference potential VRN is about +0.9■. However, in reality, the threshold voltage VTHP varies depending on the manufacturing process, etc., so the reference potential VRN includes the variation ΔVTHP +VTHP±ΔVTHP.
In other words, it is approximately +0.9±ΔVTHF.

Similarly, the reference potential generation circuit VRGB includes, although not particularly limited to, three P-channel MOSFETQs provided in series between the external power supply voltage vCC and the ground potential of the circuit.
I 1-Ql 3 and one N-channel MOSFETQ
66, and two P-channel MO5FETQI provided in parallel configuration with MO5FETQII to Q13.
Here, MOSFETs Q14 and Q15 are high threshold voltage type MOSFETs, and their threshold voltages are similar to MO3FETQ23 above.
The threshold voltage VTHP is approximately twice the threshold voltage VTHP of ordinary P-channel MO3FETs such as MO3FETQI1-Ql3, that is, 2VTHP. The bias voltage VBI is supplied to the gate of MOSFETQll, and MOSFETQll is supplied with the bias voltage VBI.
A bias voltage VB3 is supplied to the gate of 66. M
O3FETQ12 and Ql3 and Ql4 and Ql5
has its gate and drain commonly coupled, so that
It is assumed to be in the form of a diode. The drain potential of MO3FETQI1, that is, the source potential of MO3FETQI2, is supplied to the reference potential generation circuit VLG as the output signal of this reference potential generation circuit VRGB, that is, the reference potential VRB.

In the reference potential generation circuit VRGB, MOSFETQ6
The current obtained through 6 is equally shunted to MOSFETs QI2 and Ql3 and MO3FETs QI 4 and Ql5 by the current limiting action of MOSFET QII.

Therefore, the source-drain voltages of MO3FETs Q12 and Ql3 are approximately equal to their threshold voltages VTHP.
Therefore, the source/drain voltages of MOSFETs Q14 and Ql5 are approximately equal to their threshold voltages 2VTHP.
becomes. As a result, the drain voltage of MO3FETQIl, that is, the reference potential VRB, becomes approximately CC2VTHP
becomes. In this example, a P-channel MO5FE
As mentioned above, the threshold voltage of T is about 0.9
V, and the reference potential VRN is approximately Vcc-1.8V. However, in reality, the threshold voltage VTHP varies due to the manufacturing process, etc., so the reference potential VRB includes the variation Δ■Tl(P, VCC-2(VTHP±
ΔVT14F) In other words, it is approximately V CC -1,8±2 Δ■ HP.

Next, although the fuse circuit FC is not particularly limited, the seventh
As shown in the figure, test control signals PF50 to PF55
Six unit fuse circuits tJFc are provided corresponding to
O~UFC5 and two decoders DEC1 and DEC2
Equipped with

Unit of fuse circuit FC Fuse circuit UFCO~UFC
5 is a unit fuse circuit UFCO, although it is not particularly limited.
One of these fuse means F1 includes, for example, a fuse means F1 selectively cut by a laser beam or the like, as shown in FIG.
P-channel MO3FETQ31 (pseudo image cutting means)
is coupled to the external power supply voltage vCC via. In addition, the other ones are N-channel MO5FETQ77 and Ql8
It is coupled to the ground potential of the circuit through the inverter circuit N1, and further coupled to the input terminal of the inverter circuit N1. MO3FETQ31
The gate of the test pad PF50 is coupled to the ground potential of the circuit through the corresponding resistor R20, and the gate of the test pad PF50
- PF55, respectively. Also, MO3FET
External power supply voltage VCC is supplied to the gate of Q77,
The output signals of the corresponding inverter circuits Nl are supplied to the MO3FETQ7 B gates. This results in
MO3FETQ77 acts as a load MO3FET,
MOSFET Q7B acts as a feedback MO3FET that transmits the output signal of inverter circuit Nl to its input terminal. Although not particularly limited, test bands PF50 to PFS5 are normally kept open and selectively coupled to external power supply voltage VCC during a predetermined test operation.

The output signal of the inverter circuit N1 is the output signal of the inverter circuit N2.
After being inverted by FOB-F5B, the inverted output signal FOB-F5B of each unit fuse circuit is obtained. These inverted output signals are
Further, after being inverted by an inverter circuit N3, it is made into non-inverted output signals FO to F5 of each unit fuse circuit. Complementary output signal FO of unit fuse circuit UFCO-UFC2
-F2 is supplied to the decoder DBCI, and the complementary output signals L3 to L5 of the unit fuse circuits UFC3 to UFC5 are
The signal is supplied to the decoder DEC2.

When the Guinamink type RAM is in the normal operating state and the test pads PF50-PF55 are in the open state, the MO3FETQ31 of the unit fuse circuits UFCO-UFC5 is supplied with the circuit ground potential through the corresponding resistor R20. , turns on. At this time, if the corresponding fuse means Fl is not disconnected, the input of the inverter circuit Nl becomes high level, so the inverted output signal FOB-F5B of the unit fuse circuit UFCO-UFC5 becomes high level, and the non-inverted output signal FO -F5 becomes low level. Also, at this time, the corresponding fuse means F1
is disconnected, the input of the inverter circuit N1 becomes low level, so the unit fuse circuits UFCO to UF
The inverted output signal FOR-F5B of C5 becomes low level, and the non-inverted output signal FO-F5 becomes high level.

On the other hand, when the dynamic RAM is put into a predetermined test operation state and the corresponding test pads PF50-PFS5 are coupled to the external power supply voltage VCC, the unit fuse circuits UFCO~
MO3FETQ31 of UFC5 is turned off. Therefore, the input of the inverter circuit N1 is connected to the fuse means F
Regardless of whether it is 1 or not, it is forcibly set to low level. Therefore, the inverted output signals FOB-F5B of the unit fuse circuits UFCO to UFC5 are forcibly set to a low level regardless of the corresponding fuse means F1, and the non-inverted output signal t=FO
~F5 becomes high level. That is, in the fuse circuit FC of this embodiment, by coupling the test pads PF50 to PF55 to the external voltage VCC, it is possible to create a pseudo disconnected state of the fuse means F1 of the corresponding unit fuse circuits UFCO to UFC5. can.

The decoder DEC1 of the fuse circuit FC includes, although not particularly limited to, eight NOR gate circuits NOI to NOB.

The inverted output signal FOB-F2B and the non-inverted output signal FO-F2 of the unit fuse circuits UFCO to UFC2 are supplied to the first to third input terminals of these NOR gate circuits in a predetermined combination. Noah gate circuit NOI
The output signals of -N08 are supplied to the normal area reference potential generation circuit VLGN of the reference potential generation circuit VLG as output signals of the fuse circuit FC, that is, internal signals FNO to FN7. As a result, the internal signals FNO to FN7 are alternatively set to a high level when the fuse means F1 of the unit fuse circuit tJFco-UFC2 is brought into the disconnected state or pseudo-disconnected state in a predetermined combination. That is, for example, the fuse means F of the unit fuse circuit UFCO-UFC2
When all fuse means 1 are not in a disconnected state or a pseudo-disconnected state, the internal signal FNO is alternatively set to a high level, and when all of these fuse means are in a disconnected state or a pseudo-disconnected state, an internal signal FN7 is alternatively set to a high level. considered to be at a high level.

Similarly, the decoder DEC2 of the fuse circuit FC includes eight NOR gate circuits NO9 to N016. F3B-
F5B and non-inverted output signals F3 to F5 are supplied in a predetermined combination. Noah gate circuit NO9~N016
The output signals of the burn-in region reference potential generation circuit VL of the reference potential generation circuit VLG are outputted as internal signals FBO to FB7.
Supplied to GB. As a result, internal signals FBO to FB
7 is alternatively set to a high level when the fuse means F1 of the unit fuse circuits UFC3 to UFC5 are brought into a disconnected state or a pseudo disconnected state in a corresponding combination.

Although the reference potential generation circuit VLG is not particularly limited, the first
As shown in the figure, the reference potential generation circuit for normal area VL
It includes a GN (first reference potential generation circuit), a burn-in region reference potential generation circuit VLGB ($2 base #! potential generation circuit), and a reference potential switching circuit VLS.

Among these, the normal region reference potential generation circuit VLGN includes an operational amplifier circuit OAI whose basic configuration is a pair of differential MO5FETs Q55 and Q56, although the drains of these MOS FETs are connected to a pair of P-channel External 1! via MO3FETQ7 and Q8! A source voltage vCC, whose commonly coupled source is N
It is coupled to the circuit ground potential via channel MO5FETQ57. The MO3FETs Q7 and Q8 act as active loads for the differential MO3FETs Q55 and Q56 by being configured in a tii style mirror configuration, and
FETQ57 acts as a constant current source by supplying a predetermined constant voltage VSI to its gate. MO3FE
The gates of TQ55 and Q56 are respectively an inverting input terminal (first input terminal) and a non-inverting input terminal + (second input terminal) of the operational amplifier circuit OAI, and MO5FETQ7
The commonly coupled drains of Q55 and Q55 are used as the output terminal of the operational amplifier circuit OAI.

Inverting input terminal of operational amplifier circuit OAI - that is, MO5F
The reference potential generation circuit VRG is connected to the gate of ETQ55.
The reference potential VRN is supplied from the P-channel type control @MO3FETQ9, and its output signal, that is, the commonly coupled drain potential of the MOS FETQ7 and Q55.
is supplied to the gate. The source of the control MO5FET Q9 is coupled to the external voltage CC, and its drain is coupled to the output terminal VLN of the reference potential generation circuit VLGN via the P-channel MO3FET QIO, which receives the internal control signal TVLK at its gate. . Output terminal VL
Resistors RIO to R18 forming a feedback circuit are provided in series between N and the ground potential of the circuit. Further, each commonly coupled node of these resistors is connected to the feedback MO3.
It is commonly coupled to the non-inverting input terminal of the operational amplifier circuit OAI via FETs Q58 to Q65. Feedback MO3FET
Corresponding internal signals FNO-FN7 are supplied from the fuse circuit FC to the gates of Q58 to Q65, respectively. The potential of the output terminal VLN is the output signal of the normal area reference potential generation circuit VLGN, that is, the reference potential VLN (
At the same time, it is supplied to the internal voltage source voltage generation circuit VG as the output signal of the reference potential generation circuit VLG, that is, the reference potential VL. This output terminal VL
A smoothing capacitor C2 having a relatively large capacitance is provided between N and the ground potential of the circuit.

As mentioned above, the internal signals FNO to FN7 can alternatively be set to high level by setting the fuse means F1 of the unit fuse circuits UFCO to UFC2 of the fuse circuit FC to the disconnected state or pseudo-disconnected state in a predetermined combination. be done. At this time, in the normal region reference potential generation circuit VLGN, the corresponding feedback MO3FETs Q58 to Q65 are alternatively turned on. Therefore, the reference potential VLN is
), the voltage is divided by the feedback resistor RA consisting of the resistance on the output terminal VLN side and the feedback resistor RB consisting of the resistance on the ground potential side of the circuit from the feedback MO3FET that is turned on, and the internal voltage is It is fed back as a potential VX to the non-inverting input terminal of the operational amplifier circuit OAI.

As is well known, the output signal of the operational amplifier circuit OAI is set high when its non-inverting input signal (ie, internal potential VX) is higher than the inverting input signal (ie, reference potential VRN), and is set to a low level in the opposite state. Operational amplifier circuit OAI
When the output signal of is made high, the control@M OS F E
The conductance of T Q 9 is reduced, thereby lowering the reference potential VLN, that is, the internal potential VX.

On the other hand, when the output signal of the operational amplifier circuit OAI is made low,
The conductance of the control jMO3FET Q9 is increased, thereby raising the reference potential VLN, that is, the internal potential XX. As a result, the operational amplifier circuit OAI receives its non-inverting input signal +, that is, the internal potential VX, and its inverting input signal -
That is, it acts to match the reference potential VRN.

When the non-inverted long signal of the operational amplifier circuit OAI, that is, the internal potential VX, and its inverted input signal, that is, the reference potential VRN, match, the internal potential VX becomes X-VRN - VLNxRB/ (RA+RB), and is therefore in the normal region. Reference potential generation circuit VL
The reference potential VLN formed by G is VLN−VRN
X(RA+RB)/RB-VRNxα.Needless to say, α is α-(RA+RB)/RB, which corresponds to the feedback factor for the operational amplifier circuit OAI. In this embodiment, the feedback rate α is set at a center value of approximately 3.67, although it is not particularly limited.

As described above, since the reference potential VRN is approximately +0.9■, the output signal of the normal area reference potential generation circuit VLGN, that is, the center value of the reference potential VLN is approximately +3.3■.

Here, as described above, the reference potential VRNO value includes a variation ΔVTMP in the threshold voltage of the MOS FET due to the manufacturing process, etc., and the reference potential VLNO value varies accordingly. In this case, fuse circuit FC
The value of the reference potential VLN is trimmed by selectively cutting off the fuse means F1 of the unit fuse circuits UFCO to UFC2 in a predetermined combination and selectively turning on the corresponding feedback MOSF'ETQ58 to Q65. However, it can be set to a desired value, that is, +3.3■. In this trimming step, the fuse means F1 of the unit fuse circuits UFCO to UFC2 of the fuse circuit FC are connected to the corresponding test bands PF50 to PF5 as described above.
By supplying external power supply voltage VCC to 2, it is possible to create a pseudo disconnected state. As a result, fuse means F
The combination of fuse means F1 to be cut can be found without physically cutting the fuse means F1, and the reference potential VLN can be trimmed efficiently and accurately.

By the way, the normal area reference potential generation circuit VLGN has the following:
A MOSFETQ whose gate receives the internal control signal TVLK is connected between the control @MO8FETQ9 and the output terminal VLN.
IO is provided. Although not particularly limited, this internal control signal TVLK is normally set to a low level, and is selectively set to a high level like the external power supply voltage VCC when a test operation for evaluating the operating margin of the dynamic RAM is completed. . When the dynamic RAM is in the normal operation mode and the internal control signal TVLK is set to a low level, the MOSFET QIO is turned on in the normal region reference potential generation circuit VLGN, and the above-described control operation of the reference potential VLN is performed. It will be done. However, when a test operation for evaluating the operating margin of the dynamic RAM is performed and the internal control signal TVLK is set to high level, the MOSFET QIO is turned off, and the normal area reference potential generation circuit VLGN is substantially turned off. Stop operation.

Next, the burn-in region reference potential generation circuit VLGB of the reference potential generation circuit VLG includes, but is not particularly limited to, an operational amplifier circuit OA2 whose basic configuration is P-channel type differential MOSFETs Q5 and Q6, and an output of the operational amplifier circuit OA2. This system includes an N-channel control MO3FET Q49 that receives the signal a! The drain of IMO8FETQ49 is
It is coupled to external power supply voltage VCC through series resistors R1 to R9, which together with N-channel MO5FETs Q41 to Q48 constitute a feedback circuit. Feedback MO5FETQ41~Q
The corresponding internal signals FBO to FB7 are respectively supplied from the fuse circuit FC to the gates of 48, and the commonly coupled sources thereof are coupled to the inverting input terminal 10 of the operational amplifier circuit 0A20, ie, the gate of MOSFET Q6. Inverting input terminal of operational amplifier circuit OA2 - that is, MOS
The gate of FETQ5 is connected to the reference potential generation circuit VRG.
A reference potential VRB is supplied from. Control MO3FETQ
The drain potential of 49 is used as the output signal of the burn-in region reference potential ordering circuit VLGB, that is, the reference potential VRB.

As mentioned above, the internal signals FBO to FB7 can alternatively be set to a high level by setting the fuse means F1 of the unit fuse circuits UFC3 to UFC5 of the fuse circuit FC into the disconnected state or pseudo-disconnected state in a corresponding combination. be done.

At this time, in the burn-in region reference potential generation circuit VLGB, the corresponding feedback MO3FETs Q41-Q4B are alternatively turned on. Therefore, the reference potential VLB is
As shown in the equivalent circuit diagram in Figure (b), the feedback resistor RC consisting of a resistor on the external power supply voltage VCC side and the feedback resistor RD consisting of a resistor on the output terminal VLB side from the MOS FET that is turned on. is fed back to the non-inverting input terminal of the operational amplifier circuit OA2 as an internal potential vy.

As is well known, the output signal of the operational amplifier circuit OA2 is made high when its non-inverting input signal, ie, the internal potential vy, is made higher than the inverting input signal, ie, the reference potential VRB, and is made low in the opposite situation. When the output signal of the operational amplifier circuit OA2 is made high, the conductance of the control MO3FETQ49 is increased, thereby increasing the reference potential V
LB, that is, internal potential VY is lowered. On the other hand, when the output signal of the operational amplifier circuit OA2 is made low, the control MO3
The conductance of FETQ49 is made small, thereby raising the reference potential VLB, that is, the internal potential vy. As a result, the operational amplifier circuit OA2 operates to match its non-inverted output signal 0, that is, the internal potential vy, with its inverted input signal, that is, the reference potential VRB.

When the non-inverting input signal (ie, internal potential) Y of the operational amplifier circuit OA2 and its inverted input signal (ie, the reference potential VRB) match, the internal potential vy is Y-VRB -VLB+ (VCC-VLB)X RD/ (RC+RD ) However, as mentioned above, the reference potential VRB is VRB=VCC-2VTMP, so rearranging the above equation, VLB [1-RD/ (RC+RD) co-
VCCEl-RD/ (RC1RD)L-2VTHP
Therefore, VLB-VCC 2VTHP / [1-RD/ (RC0RD)
CC- 2V7Hr X (RC+RD)/RC-VCC-2V
Needless to say, β is β-(RC+RD)/RC, which corresponds to the feedback factor for the operational amplifier circuit OA2. In this embodiment, the feedback rate β is set so that its center value is approximately 1.5, although it is not particularly limited.

As mentioned above, since the threshold voltage vT)IP of the P-channel MO3FET is approximately 0.9V, the output signal of the burn-in region reference potential generation circuit VLGB, that is, the center value of the reference potential VLN is VCC-2, 7V, which is increased in proportion to the external power supply voltage VCC(7) value.

Here, as described above, the reference potential VRBO value includes the variation ΔVTHP of the threshold voltage of the MOSFET due to the manufacturing process, etc., and is set as VRB=VCC-2 (VTHP±ΔVTHP). The value of potential VLB changes in accordance with this variation ΔVTHP.

In this case, unit fuse circuit UFC of fuse circuit FC
The reference potential VLBO value is trimmed by selectively setting the fuse means F1 of 3 to UFC5 in a cut-off state or a pseudo-cut state in a predetermined combination, and selectively turning on the corresponding feedback MO3FETs Q41 to Q48. can be set to a value of VCC-2.7.

Reference potential switching circuit VLS of reference potential generation circuit VLG
includes, but is not particularly limited to, a pair of N-channel MO3FETs Q50 and Q51 that are in a differential configuration. An N-channel MO is coupled to CC and between its commonly coupled source and circuit ground potential.
A constant current source consisting of 3FETQ52 is provided.

The gate of MO5FETQ50 is supplied with the output signal of the burn-in region reference potential generation circuit VLGB, that is, the reference potential VLB, and the gate of the other MO3FETQ51 is supplied with the output signal of the normal region reference potential generation circuit VLGN, that is, the reference potential VLN. A reference potential VL is supplied. A P-channel type control MO5FETQ3 is installed between the external power supply voltage CC and the gate of MO3FETQ51, that is, the output terminal VL.
The drain potential of the MO3FETQ50 is supplied to the gate of TQ3. This allows MO3FETQ50
The differential circuit whose basic configuration is Q51 and Q51 has a reference potential VL
Acts as a comparison circuit to compare the levels of B and VLN, and controls the! jMO3FETQ3 selectively acts as a control MO3FET for the reference potential VL on the condition that the output signal of the comparison circuit is at a low level, in other words, on the condition that the level of the reference potential VLB is higher than the reference potential VLN. do.

That is, when the reference potential VLB is lower than the reference potential VLN, the output signal of the comparison circuit made up of MO3FETQ50 and C51 becomes a high level like the external power supply voltage VCC. Therefore, MO3FETQ3 is turned off,
does not act as a control MO3FET, while the reference potential V
When LB becomes higher than the reference potential VLN, the output signal of the comparison circuit becomes low level in accordance with the reference potential VLB.

Therefore, the MO3FET Q3 is turned on and acts as a control MO3FET for the reference potential VL. As mentioned above, the value of the reference potential VLB is equal to the external power supply voltage CC
is increased in proportion to. As a result, the reference potential VL is
When the external power supply voltage VCCO value is below a predetermined value, that is, when the external power supply voltage CC is in the first region, the output signal of the normal region reference potential generation circuit VLGN, that is, the reference potential VLN, When the power supply voltage VCC is a predetermined value or more, that is, when the external power supply voltage CC is in the second region, the burn-in region reference potential generation circuit V
It changes according to the LGB output signal, that is, the reference potential VLB.

The output signal of the reference potential generation circuit VLG, that is, the reference potential V
As described above, L is supplied to the internal power supply voltage generation circuit IVG.

Although the internal power supply voltage generation circuit IVG is not particularly limited,
As shown in FIG. 8, it includes two internal power supply voltage generation circuits IVGI and 1VG2. There is a capacitor C3 between the commonly coupled output terminals of these internal power supply voltage generating circuits and the ground potential of the circuit, although it is not particularly limited.
and C4 and a resistor R19 are provided.

The internal power supply voltage generation circuit IVGI includes, but is not particularly limited to, N-channel type differential MO3FETQ69 and C70.
The drains of the differential MO3FETs Q69 and C70, including the operational amplifier circuit OA3 whose basic configuration is
5 to external power supply voltage VCC, and its commonly coupled sources are coupled to the ground potential of the circuit via N-channel MO3FETQ71. MO3FETQ7
A timing signal φvc is supplied to the gate of No. 1 from a timing generation circuit TG. As described above, the timing signal φvc is selectively set to a high level while the dynamic RAM is in the selected state. As a result, the operational amplifier circuit OA3 is selectively brought into operation by setting the dynamic RAM to a selected state and setting the timing signal φvc to a high level.

Inverting input terminal of operational amplifier circuit OA3 - that is, MO3F
The reference potential VL is supplied to the gate of ETQ69. The output signal of the operational amplifier circuit OA3 is connected to the external power supply voltage VCC and its non-inverting input terminal, that is, MO3FE.
It is supplied to the gate of a P-channel type control MO5FETQ27 provided between the gate of TQ70 and the gate of TQ70. Here, the control MO3FETQ27 is designed to have a relatively large conductance. viI! MOSFETQ
The drain of 27 has the above-mentioned timing signal φ at its gate.
It is coupled to the ground potential of the circuit via the N-channel MOSFET Q72 that receives
Connected to CL.

Furthermore, external power supply voltage VCC and control jMOsFETQ2
A P-channel MO5FETQ26, which receives the timing signal φvc at its gate, is provided between the gate of MO5FETQ7 and the gate of MO5FETQ26.

From these facts, the internal power supply voltage generation circuit rvG1 is
When the dynamic RAM is brought into a selected state and the timing signal φVC is brought to a high level, it is selectively brought into operation, and acts to match the level of its output signal, that is, the internal power supply voltage VCL, with the reference potential VL. At this time, the current supply capacity of the internal power supply voltage generation circuit IVGI is
By increasing the conductance of the control MO5FETQ27, it is made relatively large. Dynamic RAM
When the timing signal φvc is set to a low level when the input signal φvc is in the nose selection state, the operation of the internal power supply voltage generation circuit IVGI is stopped.

On the other hand, the internal power supply voltage generation circuit IVG2 includes an operational amplifier circuit OA4 whose basic configuration is N-channel type differential MOSFETs Q73 and C74, and the drains of these differential MO3FETs Q73 and Q74 are connected to an active load, although this is not particularly limited. P-channel MOSFETQ2
8 and Q29 to the external power supply voltage ■Cc,
Its common coupled source is an N-channel MOSFE
It is coupled to the ground potential of the circuit via TQ74.

The gate of MO3FETQ75 is connected to external power supply voltage CC
is supplied, so that the operational amplifier circuit OA4 is always in an operating state.

Inverting input terminal of operational amplifier circuit OA4 - that is, MO3F
The reference potential VL is supplied to the gate of ETQ73. Further, the output signal of the operational amplifier circuit OA4 is connected to the external power supply voltage VCC and its non-inverting input terminal, that is, MO3FE.
It is supplied to the gate of a P-channel type control MO3FETQ30 provided between the gate of TQ74. Here, the control MO3FET Q30 is designed to have a relatively small conductance. Control mMO3FETQ30
The drain of the Nchi? receives external power supply voltage VCC at its gate? It is coupled to the ground potential of the circuit via a 7-channel Mo SF ETQ 76, and also to the internal power supply voltage supply point VCL.

For these reasons, the internal power supply voltage generation circuit IVG2 is
Regardless of the selection state of the dynamic RAM, it is always in an operating state, and its output signal, that is, the internal power supply voltage VCL
It acts to match the level of VL with the reference potential VL.

At this time, the current supply capability of the internal power supply voltage generation circuit IVG2 is made relatively small by reducing the conductance of the control MO3FETQ30. As a result, the current supply capability of the internal power supply voltage generating circuit IVG as a whole is increased when the dynamic RAM is in the selected state, and is reduced to the necessary minimum when the dynamic RAM is in the non-selected state.

By the way, as mentioned above, the reference potential VL supplied from the reference potential generation circuit VLG becomes the reference potential ■LN, that is, 13.3
(2) When the external power supply voltage (2)CC exceeds a predetermined value, it is increased in proportion to the external power supply voltage (2)CC.

However, as shown in the output characteristic diagram of FIG.
When CC is in the normal area NM (first area), VCL
N, that is, +3.3■, and when the external power supply voltage vCC is set to be above a predetermined value, in other words, when the external power supply voltage ■cc is in the burn-in region BT (second region), VCL-VCC-VS =VCC-2VTHPXβ-VCC-2,7, and is increased in proportion to the external power supply voltage VCC.

Furthermore, in the dynamic RAM of this embodiment, the reference potential VL, that is, VLB in the burn-in region is different from the unit fuse circuit UFC of the fuse circuit FC, as described above.
Trimming is performed by selectively setting the fuse means F1 of the fuses F3 to UFC5 in a disconnected state or a pseudo disconnected state. Therefore, the value of the internal power supply voltage VCL in the burn-in region BT is the value of the P-channel MO3F that determines the reference potential VRB.
Although the threshold voltage VTHP of ET fluctuates depending on the manufacturing process, etc., it is brought close to the above-mentioned central value, and as shown by the solid line in FIG. 3, the fluctuation ECL is relatively small.
It becomes something that does not appear. As a result, the value of the internal power supply voltage CL during the burn-in test can be adjusted to the desired voltage VCL.
It becomes possible to set the value sufficiently close to B. As a result, the error detection rate of the burn-in test, that is, the screening accuracy, is increased, the reliability of dynamic RAM is increased, and damage to normal circuit elements due to so-called overkill is reduced, and the yield of dynamic RAM is improved. .

As shown in the above embodiment, the following effects can be obtained by applying the present invention to a semiconductor integrated circuit device such as a dynamic RAM having a built-in voltage conversion circuit. That is, (1) A voltage conversion circuit built into a dynamic RAM or the like and having a so-called burn-in region in which the output voltage, that is, the internal power supply voltage is increased in proportion to the external power supply voltage during a burn-in test, is disconnected in a predetermined combination. By providing a fuse means that can selectively switch the value of the internal power supply load, the value of the internal 17 Mm voltage in the burn-in region can be trimmed, and variations due to manufacturing variations can be suppressed.

(2) Item (1) above provides the effect of increasing the error detection rate of the burn-in test and improving its screening accuracy.

(3) By using the above (1), damage to normal circuit elements due to so-called overkill can be reduced, and dynamic type R
The effect of increasing the yield of AM, etc. can be obtained.

(4) In items (J, ) to (3) above, by providing other fuse means that can selectively cut the value of internal power supply pressure during normal operation by being disconnected in a predetermined combination. , the value of the internal power supply voltage in the so-called normal region can be trimmed, and variations due to manufacturing variations can be suppressed.

(5) Item (4) above provides the effect of stabilizing the operation of the dynamic RAM in the normal operation mode.

(6) In items (1) to (5) above, by providing a pseudo disconnection means such as a MOSFET that is selectively turned off according to a predetermined test control signal in series with the fuse means, The fuse means can be put into a pseudo-cut state, and the combination of fuse means to be cut can be determined and checked in advance, thereby achieving the effect that trimming accuracy can be improved.

(7) According to the above item (6), it is possible to trim the internal power supply voltage, etc. without physically cutting off the fuse means.

(8) In items (1) to (7) above, when test operations are performed to evaluate the operating margin of dynamic RAM, etc., the value of the internal power supply load in the normal region is proportional to the external power supply voltage. By making it possible to increase the
This provides the advantage that the value of the internal 1i source voltage during operation margin evaluation can be set in accordance with the external power source voltage.

(9) In items (1) to (8) above, a dynamic RA
By providing a MOSFET that is selectively turned on when M is in a predetermined test mode, the dynamic type R
After the AM is completed, it is possible to monitor the value of the internal power supply pressure via the external terminal.

(10) The above-mentioned items (6) to (9) make it possible to improve the efficiency of testing operations for dynamic RAMs, etc., and to reduce the number of testing steps.

(11) Items (1) to (10) above have the effect of increasing the reliability of the dynamic RAM while reducing its cost.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in FIG. 1, the MOS that constitutes the feedback circuit of each reference potential generation circuit
The number of FETs and resistors, that is, the number of trimming steps for internal power supply heavy pressure VCL, can be set arbitrarily. Furthermore, various methods can be considered as means for trimming the reference potentials VLN and VLB and VL, and the specific values of these reference potentials and reference potentials VRN and VRB are arbitrary. In FIG. 3, the voltage conversion circuit VC can also have output characteristics as shown in FIG. 4 or 5, for example. That is, in the case of FIG. 4, if the internal power supply voltage VCL is
In the normal region NM, the voltage gradually increases in proportion to the external power supply voltage CC. Further, in the case of FIG. 5, the internal power supply voltage VCL is in the burn-in region BT even in the normal region NM.
is increased in proportion to external power supply voltage VCC at the same ratio as . In either case, the value of the internal power supply voltage VCL in the burn-in region BT is trimmed, for example, by selectively cutting off the fuse means, and fluctuations due to manufacturing variations or the like are suppressed. In FIG. 7, the number of need means provided in the fuse means FC is arbitrary, and the method of identifying the cut state and the method of decoding are as follows.
Various embodiments may be considered, and if the number of trimming steps of the reference potential is very large and the number of fuse means installed is large, the fuse circuit FC may adopt a modified example as shown in FIG. 11. I can do it. That is, in FIG. 811, fuse circuit FC corresponds to the normal area and includes fuse circuit FCN including n unit fuse circuits,
The fuse circuit PCB corresponds to the burn-in region and includes n unit fuse circuits, and further includes n-bit counter circuits CTRN and CTRB provided corresponding to these fuse circuits FCN and PCB. These counter circuits are commonly supplied with a reset signal R3T and a count-up pulse CU, and are supplied with an enable signal TE.
N and TEB are supplied respectively. These counter circuits then receive a corresponding enable signal TEN or T.
When EB is set to high level, a step operation is selectively performed by the count amplifier pulse CU, and its output signal, that is, the internal signal CNO to CNn-1 or CBO-CB
n-1 is valid. As a result, the pseudo-cut state of the fuse means of the fuse circuit FCN or PCB can be realized in various combinations without providing a large number of test bands corresponding to each unit fuse circuit. In FIG. 8, internal power supply voltage generation circuit IVG does not need to include a plurality of internal power supply voltage generation circuits having different current supply capacities, nor does it need to selectively put them into an operating state according to a predetermined timing signal. In FIG. 9, external power supply voltage VCC does not particularly need to be supplied to circuits other than voltage conversion circuit VC, and the specific values of external power supply voltage VCC and internal power supply voltage VCL are also arbitrary. Further, the dynamic RAM can include, for example, a plurality of similar voltage conversion circuits with different output voltages. In FIG. 1O, the dynamic RAM can include a plurality of memory mats, or may have a so-called multi-bit configuration in which multiple bits of storage data are input/output at the same time. The external terminal for monitoring the internal power supply voltage VCL, which does not require the adoption of the shared sense method or the address multiplex method, may be either the data input terminal Din or the address input terminal AO"Ai. Furthermore, specific circuits of the reference potential generation circuit VLG, reference potential generation circuit VRG, fuse circuit FC, and internal power supply voltage generation circuit vG shown in FIG. 1 and FIGS. 6 to 8 Various embodiments can be adopted for the configuration, the block configuration of the voltage conversion circuit VC and the dynamic RAM shown in FIGS. 9 and 10, and the combinations of control signals, address signals, power supply voltages, etc.

The above explanation will mainly focus on the dynamic type RA, which is the application field that is the background of the invention made by the present inventor.
Although the description has been given of a case where the present invention is applicable to M, the present invention is not limited thereto, and can also be applied to, for example, various semiconductor memory devices incorporating a voltage conversion circuit, logic integrated circuit devices such as gate array integrated circuits, and the like. Further, the invention in which the fuse means is placed in a pseudo disconnected state applies to various semiconductor memory devices and logic devices equipped with a fuse means for selectively switching a defective element to a redundant circuit and a fuse means for trimming other circuit constants. The present invention, which can also be applied to integrated circuit devices, is widely applicable to at least semiconductor integrated circuit devices that incorporate a voltage conversion circuit or are provided with fuse means.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, in a voltage converter circuit that is built into a dynamic RAM or the like and has a so-called burn-in region in which its output voltage, that is, the internal power supply voltage changes in proportion to the external i4 source voltage during accelerated test operation, it is disconnected in a predetermined combination. A fuse means is provided which can selectively switch the value of internal power supply pressure in the burn-in region.

In addition, a pseudo-cutting means is provided which can pseudo-disconnect these fuse means, and the internal type IIj! Allows you to monitor the voltage value. Thereby, it is possible to efficiently trim the value of the internal power supply voltage in the burn-in region, suppress fluctuations due to manufacturing variations, etc., and improve the screening accuracy of the burn-in test. Furthermore, damage to normal circuit elements due to so-called overkill can be reduced, and the yield of dynamic RAMs and the like can be increased. As a result, it is possible to improve the reliability of dynamic RAMs and the like while reducing their costs.

[Brief explanation of the drawing]

Figure 1 shows a dynamic RAM to which this invention is applied.
2 is a partial equivalent circuit diagram showing an example of the reference potential generation circuit in FIG. 1; FIG. 3 is a circuit diagram showing an example of the reference potential generation circuit included in the voltage conversion circuit of FIG. FIG. 4 is an output characteristic diagram showing a first embodiment of the voltage conversion circuit including the reference potential ordering circuit shown in FIG. 1, and FIG. 4 shows a second embodiment of the voltage conversion circuit including the reference potential generation circuit shown in FIG. 5 is an output characteristic diagram showing a third embodiment of the voltage conversion circuit including the reference potential generation circuit of FIG. 1, and FIG. 6 is an output characteristic diagram of a dynamic type RA to which the present invention is applied.
A circuit diagram showing a practical example of the reference potential generation circuit included in the voltage conversion circuit of M, @Figure 7 is a dynamic RAM to which this invention is applied.
Figure gJ8 is a circuit diagram showing a practical example of a fuse circuit included in a voltage conversion circuit of this invention.
- of the internal power supply voltage generation circuit included in the voltage conversion circuit of M
A circuit diagram showing a practical example, FIG. 9, is a dynamic RAM to which this invention is applied.
The block diagram illustrating a practical example of the voltage conversion circuit of
FIG. 11 is a block diagram showing another embodiment of the fuse circuit included in the voltage conversion circuit of the dynamic RAM, in which the present invention was first published. VLG...Reference potential generation circuit, VLGN...Reference potential generation circuit for normal area, VLGB...Reference potential generation circuit for burn-in area, VLS...Reference potential switching circuit, C1-c31...P-chie ? 7 channel MO3FET, C
41~Q79--- N-channel MO3FET, C1
~c4... Capacitor, R1-R20... Resistor. OAI~OA4... operational amplifier circuit, R^~RD...
return resistance. VRG...Reference potential generation circuit, BC...Bias circuit, VRGN...Reference potential generation circuit for normal area, VR
GB...Reference potential starting circuit for burn-in region. FC---fuse circuit, UFCO-UFC5...unit fuse circuit, DEC1~DEC2...decoder,
Fl...Fuse means, N1-N3...Inverter circuit, NOI-N016...Nor gate circuit. IVG, IVGI-IVG2---Internal power supply voltage generation circuit. VC...Voltage conversion circuit. DRAM...-Dynamic RAM, MARYL, M
ARYR...Memory array, SA...Sense amplifier, RADL, RADR...Row address decoder, R
AB...Row address decoder, RFC...Refresh address counter, CAD...Column address decoder, CAB...Column address decoder, MA
...Main amplifier, DIR...Data input buffer, DOB...Data output puff noah, TO...Timing ordering circuit. FCN, PCB...Fuse circuit, CTRN. CTRB...Counter circuit.

Claims (1)

[Claims] 1. When the value of the external power supply voltage supplied from the outside is in the first region, step down the external power supply voltage to form a predetermined internal power supply voltage necessary for normal operation; a voltage conversion circuit that changes the value of the internal power supply voltage according to the external power supply voltage in order to perform a predetermined test operation when the value of the external power supply voltage is in the second region; A semiconductor integrated circuit device characterized in that the value of the internal power supply voltage when in the second region can be trimmed. 2. The value of the internal power supply voltage is approximately fixed at a predetermined value when the value of the external power supply voltage is in the first region, and the value of the external power supply voltage is approximately fixed at a predetermined value when the value of the external power supply voltage is in the second region. 2. The semiconductor integrated circuit device according to claim 1, wherein the voltage is changed in proportion to the power supply voltage. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the test operation is an accelerated test operation. 4. Claim 1, wherein the voltage conversion circuit is capable of trimming the value of the internal power supply voltage when the external power supply voltage is in a first region.
The semiconductor integrated circuit device according to item 2 or 3. 5. The voltage conversion circuit receives the first reference potential and converts the first reference potential to the first reference potential.
a first reference potential generating circuit that forms a reference potential of
a second reference potential generation circuit that receives a reference potential to form a second reference potential; and a second reference potential generation circuit that transmits the first reference potential when the external power supply voltage is in a first region and is in a second region. When the reference potential switching circuit transmits the second reference potential, and the first reference potential switching circuit transmits the second reference potential, the reference potential switching circuit transmits the second reference potential.
or an internal power supply voltage generation circuit that receives a second reference potential and forms the internal power supply voltage.
The semiconductor integrated circuit device described in . 6. Each of the first and second reference potential generation circuits has an operational amplifier circuit that receives the first or second reference potential at its first input terminal, and an output signal of the operational amplifier circuit at its gate. and a feedback circuit that transmits the first or second reference potential to a second input terminal of the operational amplifier circuit at a predetermined feedback rate, 6. The semiconductor integrated circuit device according to claim 5, wherein: is trimmed by selectively switching the feedback rate. 7. The semiconductor integrated circuit device according to claim 6, wherein the feedback rate is selectively switched by cutting fuse means in a predetermined combination. 8. The semiconductor integrated circuit device according to claim 7, wherein the voltage conversion circuit includes a pseudo-cutting means for creating a pseudo-cutting state of the fuse means. 9. The semiconductor according to claim 8, wherein the pseudo disconnection means includes a MOSFET that is provided in series with the fuse means and is selectively turned off according to a predetermined test control signal. Integrated circuit device. 10. The value of the internal power supply voltage when the external power supply voltage is in the first region is, during other predetermined test operations,
Claims 1 and 2 are characterized in that the voltage is selectively changed in proportion to the external power supply voltage.
The semiconductor integrated circuit device according to item 3, 4, 5, 6, 7, 8, or 9. 11. The semiconductor integrated circuit device according to claim 10, wherein the test operation is for determining an operating margin of the semiconductor integrated circuit device. 12. Claim 1, wherein the value of the internal power supply voltage can be monitored via a predetermined external terminal when the semiconductor integrated circuit device is placed in a predetermined test mode. The semiconductor integrated circuit device according to item 2, item 3, item 4, item 5, item 6, item 7, item 8, item 9, item 10, or item 11. 13. The external terminals are used for other predetermined purposes when the semiconductor integrated circuit device is in the normal operation mode, and in the test mode, the startup control signals are in a predetermined combination. 13. The semiconductor integrated circuit device according to claim 12, wherein the semiconductor integrated circuit device is selectively specified by. 14. The semiconductor integrated circuit device is a dynamic type RA
Claims 1 and 2 characterized in that M is
Semiconductor integrated circuit as described in item 3, item 4, item 5, item 6, item 7, item 8, item 9, item 10, item 11, item 12, or item 13. Device. 15. A semiconductor integrated circuit device comprising fuse means that is selectively cut, and pseudo-cutting means for creating a pseudo-cutting state of the fuse means. 16. The semiconductor according to claim 15, wherein the pseudo cutting means includes a MOSFET that is provided in series with the fuse means and is selectively turned off in accordance with a predetermined test control signal. Integrated circuit device. 17. The semiconductor integrated circuit device is equipped with a voltage conversion circuit that forms a predetermined internal power supply voltage based on an external power supply voltage supplied from the outside, and the fuse means is configured to convert the internal power supply voltage into a predetermined internal power supply voltage. 17. The semiconductor integrated circuit device according to claim 15 or 16, wherein the semiconductor integrated circuit device is for trimming values. 18. Equipped with a voltage conversion circuit that forms a predetermined internal power supply voltage based on an external power supply voltage supplied from the outside, and monitors the value of the internal power supply voltage through a predetermined external terminal in a predetermined test mode. A semiconductor integrated circuit device characterized by: 19. The semiconductor integrated circuit device according to claim 18, wherein the external terminal is used for another predetermined purpose in a normal operation mode. 20. The semiconductor integrated circuit device includes a MOSFET that is provided between the internal power supply voltage supply point and the external terminal and is selectively turned on in the test mode. The semiconductor integrated circuit device according to scope 18 or 19. 21. The test mode according to claim 18, 19, or 20, wherein the test mode is selectively specified by a predetermined combination of activation control signals. Semiconductor integrated circuit device.