JPH04102263A - Receiving signal recorder - Google Patents
Receiving signal recorderInfo
- Publication number
- JPH04102263A JPH04102263A JP21916990A JP21916990A JPH04102263A JP H04102263 A JPH04102263 A JP H04102263A JP 21916990 A JP21916990 A JP 21916990A JP 21916990 A JP21916990 A JP 21916990A JP H04102263 A JPH04102263 A JP H04102263A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- recorder
- outputted
- band filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は音声又はデータの受信機に関し、特に受信した
音声及びデータを記録する受信信号記録装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voice or data receiver, and more particularly to a received signal recording device for recording received voice and data.
従来の受信信号記録装置は、第2図に示すような受信入
力信号の有無を検知する回路(スケルチ回路)を用いて
いる。図で中間周波増幅回路1の後に、検波回路3を設
け、中間周波入力信号S1のレベルが大きくなった時に
、レコーダ5に記録制御信号S5を出力し、復調回路2
で復調されたデータがレコーダ5で記録されるようにし
ている。A conventional received signal recording device uses a circuit (squelch circuit) for detecting the presence or absence of a received input signal as shown in FIG. In the figure, a detection circuit 3 is provided after the intermediate frequency amplification circuit 1, and when the level of the intermediate frequency input signal S1 increases, a recording control signal S5 is output to the recorder 5, and the demodulation circuit 2
The data demodulated is recorded by the recorder 5.
また、その検知レベル設定はボリューム6により行う。Further, the detection level is set using the volume 6.
従来の受信信号記録装置では入力信号のレベルが大きく
なった時に、記録制御信号を出力するので大きなノイズ
が入力した時も、レコーダが動作し、不要なノイズを記
録してしまう。また制御信号が出力されてからレコーダ
の動作するまでの時間があるため、入力信号の最初の部
分が切れて記録される。入力信号を検知する回路として
一般的な中間周波増幅回路の後に検波回路を設けている
ため入力信号に対し、直線的な範囲が狭い検波出力にな
り、広範囲にわたり適切な検知レベル設定かてきないと
いう問題があった。Conventional received signal recording devices output a recording control signal when the input signal level becomes high, so even when large noise is input, the recorder operates and records unnecessary noise. Furthermore, since there is a time period from when the control signal is output until the recorder starts operating, the first part of the input signal is cut off and recorded. Since the detection circuit is installed after the intermediate frequency amplifier circuit, which is a common circuit for detecting input signals, the detection output has a narrow linear range with respect to the input signal, making it impossible to set the detection level appropriately over a wide range. There was a problem.
ご課題を解決するための手段〕
本発明の受信信号記録装置においては、復調回路から出
力される出力を高域と低域の周波数帯域に分け、そのレ
ベルを比較し、レベル差がある場合は信号と判断してレ
コーダの記録制御を行う。Means for Solving the Problem] In the received signal recording device of the present invention, the output output from the demodulation circuit is divided into high and low frequency bands, their levels are compared, and if there is a level difference, It is determined that it is a signal and controls the recording of the recorder.
口実絶倒〕 次に本発明について図面を参照して説明する。Absolute excuse] Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例を示す図で、中間周波入力信
号S1は復調回路2により復調信号S2として、出力さ
れる。ノイズ又は受信信号である復調信号S2を低域濾
波器8と高域濾波器9によって2つの周波数成分に分け
、比較回路10てレベルを比較する。比較を行う回数及
び時間はサンプルホールド信号S7により決定される。FIG. 1 is a diagram showing an embodiment of the present invention, in which an intermediate frequency input signal S1 is outputted by a demodulation circuit 2 as a demodulated signal S2. The demodulated signal S2, which is noise or a received signal, is divided into two frequency components by a low-pass filter 8 and a high-pass filter 9, and the levels are compared by a comparison circuit 10. The number and time of comparisons are determined by the sample and hold signal S7.
比較回路10により出力されるS/N判別信号S6か演
算処理回路12に於て、例えは6回比較してレベル差か
ある回数が3回以上であれば信号と判断して、S判定信
号S8を出力する。レコーダへ入力される復調信号82
″は上記の判別回路の処理時間とレコーダの記録動作立
上り時間を加算した時間について遅延回路7により遅延
させる。In the arithmetic processing circuit 12, the S/N discrimination signal S6 outputted by the comparator circuit 10 is compared six times, and if the number of times is three or more, it is determined to be a signal, and an S judgment signal is generated. Output S8. Demodulated signal 82 input to the recorder
'' is delayed by the delay circuit 7 by the sum of the processing time of the above-mentioned discrimination circuit and the start-up time of the recording operation of the recorder.
本発明では更に検知レベル設定手段(スケルチ回路)を
具備し、これは対数増幅回路12.検波回路3.検知レ
ベル設定ボリューム6、比較回路4で構成され、スケル
チ信号S、を出力する。S判定信号S8とスケルチ信号
S、はAND回路14を経て、レコーダを記録動作させ
る記録制御信号S5となる。The present invention further includes a detection level setting means (squelch circuit), which is a logarithmic amplifier circuit 12. Detection circuit 3. It is composed of a detection level setting volume 6 and a comparison circuit 4, and outputs a squelch signal S. The S determination signal S8 and the squelch signal S pass through an AND circuit 14 and become a recording control signal S5 that causes the recorder to perform a recording operation.
以上説明したように本発明は受信機の復調信号を低減濾
波器、高域濾波器等で構成されているS/N判別回路に
より、信号入力時のみレコーダを動作させて記録するこ
とにより、記録媒体の効率化を計り、また遅延回路によ
り記録された信号の頭切れを防き、正確に情報を記録す
るという効果を有する。As explained above, the present invention records the demodulated signal of the receiver by operating the recorder only when the signal is input using the S/N discriminating circuit composed of a reduction filter, a high-pass filter, etc. This has the effect of increasing the efficiency of the medium, preventing the beginning of the recorded signal from being cut off by the delay circuit, and recording information accurately.
第1図は本発明の一実施例のフロック図、第2図は従来
の一実施例のブロック図である。
1・・・・・・中間周波増幅回路、2・・・・復調回路
、3・・・・・検波回路、4.10・・・・・・比較回
路、5・・・・・lz=+−ダ、5・・・・・・検知レ
ベル設定ボリューム、7・・・・・遅延回路、8・・・
・・・低域濾波器、9・・・・・高域濾波器、11・・
・・・・サンプルホールド信号発生回路、12・・・・
演算処理回路、13・・・・・・対数増幅回路、14・
・・・・AND回路、s、、s、’・・・・・・中間周
波入力信号、S2+ 82’、S2 ・・・・・復調信
号、S3・・・・・検波出力信号、S4・・・・・・検
知レベル設定信号、S5・・・・・・記録制御信号、S
6・・・・・・サンプルホールド信号、S7・・・・・
・S/N判別信号、S8・・・・・S判定信号、S9・
・・・・・スケルチ信号。
代理人 弁理士 内 原 晋FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional embodiment. 1...Intermediate frequency amplification circuit, 2...Demodulation circuit, 3...Detection circuit, 4.10...Comparison circuit, 5...lz=+ -da, 5...detection level setting volume, 7...delay circuit, 8...
...Low pass filter, 9...High pass filter, 11...
...Sample and hold signal generation circuit, 12...
Arithmetic processing circuit, 13... Logarithmic amplifier circuit, 14.
...AND circuit, s,,s,'...Intermediate frequency input signal, S2+82', S2...Demodulated signal, S3...Detected output signal, S4... ...Detection level setting signal, S5... Recording control signal, S
6...Sample hold signal, S7...
・S/N discrimination signal, S8...S judgment signal, S9・
...Squelch signal. Agent Patent Attorney Susumu Uchihara
Claims (1)
調した信号を受ける低減濾波器及び高域濾波器と、前記
2つの濾波器の出力を比較することによりノイズあるい
は信号と判定する比較手段と、前記比較手段の出力を記
録制御信号として前記レコーダに出力する制御手段とを
具備することを特徴とする受信信号記録装置に関する。a recorder for recording the demodulated audio or data output; a reduction filter and a high-pass filter for receiving the demodulated signal; a comparing means for comparing the outputs of the two filters to determine whether the signal is noise or a signal; The present invention relates to a received signal recording apparatus characterized by comprising a control means for outputting the output of the comparison means to the recorder as a recording control signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21916990A JPH04102263A (en) | 1990-08-21 | 1990-08-21 | Receiving signal recorder |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21916990A JPH04102263A (en) | 1990-08-21 | 1990-08-21 | Receiving signal recorder |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04102263A true JPH04102263A (en) | 1992-04-03 |
Family
ID=16731286
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21916990A Pending JPH04102263A (en) | 1990-08-21 | 1990-08-21 | Receiving signal recorder |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04102263A (en) |
-
1990
- 1990-08-21 JP JP21916990A patent/JPH04102263A/en active Pending
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