JPH0399347A - Semiconductor integrated circuit device and password system - Google Patents

Abstract

PURPOSE:To protect data from illegal access by comparing an inputted password with a password self-allocated to a device, and only at the time of coincidence of both the passwords, allowing access. CONSTITUTION:A comparator is driven by a comparing signal and outputs a coincidence/discrepancy detection signal between password data B and a password A from a password register. When both the passwords A, B coincide with each other, the coincidence signal of the comparator is turned to the high level. An SR flip flop (FF) circuit is set up by the high level signal and its output signal Q is turned to the high level. An access permission signal is generated by the high level output signal Q and the acceptance of a command sent from the host side is started. Thus, the generation of data destruction due to a software bug or the like is prevented and the generation of data destruction or reading due to malice is prevented.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device and a password system, and relates to a file data processor (a file data processor) as a peripheral LSI (semiconductor integrated circuit device) constituting a microcomputer system, for example. (Hereinafter, it may be simply referred to as FDP).

[Conventional technology]

A conventional FDP is an FDP equipped with a host bus controller, a drive, and the software that controls them.
It is controlled by a general-purpose microprocessor called M (File Manager). This FM receives commands issued from the Hotos bus and decodes them. As a result of this decoding, when it is necessary to perform processing such as data read/write, the above FM
Perform the necessary settings and issue the command. Data transfer after issuing this command is performed directly between the FDP and the host bus controller without going through the FM.

A data buffer is used in the data transfer between the FDP and the host bus controller described above. This data buffer consists of two fixed sides.

There are two ways to use this data buffer: a high-speed transfer mode and a low-speed transfer mode. In the high-speed transfer mode, a transfer operation is started when data is set on one side of the data buffer. In the low-speed transfer mode, transfer is started when one sector (one block) of data is set in the data buffer.

[Problem to be solved by the invention]

The peripheral LSIs constituting the microcomputer system as described above receive commands issued from a host such as a microprocessor and perform a series of data processing corresponding to the commands. Therefore, there is a problem in that even if an invalid command is received due to a software bug or the like, it will be executed, resulting in data destruction. In the future, as microcomputer systems tend to become more sophisticated, more complex, and more accessible, data destruction due to software bugs as described above will become a serious problem.

An object of the present invention is to provide a semiconductor integrated circuit device that realizes a protection function against unauthorized access.

Another object of the present invention is to provide a password system with enhanced protection functions.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the input password is compared with the password assigned to the user, and access is permitted only when the two match. In addition, the undefined data generated when the power is turned on is used as a password, and the undefined data can be read only once and is used as the password.

[For production]

According to the above-mentioned means, data can be protected because unauthorized access due to software bugs or the like is not accepted. In addition, since undefined data at the time of power-on is used as a password, security protection can be strengthened.

〔Example〕

Figure 3 shows the file data to which this invention is applied.
A block diagram of one embodiment of a processor (F D P) is shown. Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

FM Zane-Face is FDP as mentioned above.

Constructs an interface circuit between the host bus controller and the file manager that controls the drives. The following signals are exchanged between the FDP and FM.

If access is permitted by matching passwords as described below, the FM receives commands issued from the host bus and decodes them. As a result of deciphering the command, if it is necessary to perform processing such as data read/write, the FM makes the necessary settings for the FDP and issues the command. When an ECC error occurs in data read from the drive, the FDP notifies the FM that an error has occurred. When correction is necessary, the FM issues a correction command after making the necessary settings for the FDP. With the result of this command, the FM corrects the data left in the FDP's data buffer.

The above-described transmission and reception of FM and FDP signals is performed via the FM interface. The FM interface sets data in indirect registers, data buffers, and format buffers based on data set in serial registers by FM, decodes direct commands, and displays command execution status.

The host interface generates signals necessary for data transfer with the host and controls data transfer between the host and the data buffer. In this embodiment, the host interface is provided with a password determination circuit as described below in order to prevent response to unauthorized access due to software bugs or the like. The password judgment circuit is
It consists of a register that holds password data, a password register that takes in passwords, a comparator, etc.

The format buffer stores format commands. The formant control automatically writes data to the format buffer when specified data is set in each of the indirect registers, and when a start command is issued, reads the contents of the format buffer and executes the code as follows. Output to PLA.

When a start command is issued, the PLA (programmable logic array) controls the drive interface, ECC, registers, and format control according to the format command.

The drive interface reads/writes/conveys drive data under the control of the PLA. It also converts serial data/parallel data.

The ECC circuit generates and checks ECC and CRC, and
It performs calculations to obtain a CC correction pattern.

The register stores data and mode setting information necessary for accessing the drive.

The data buffer stores data transferred between the drive and the host. Alternatively, it can also be used as an external RAM for the FM.

Buffer control switches between two buffers during command execution so that accesses from the hotos and from the drive do not conflict.

The timer monitors the number of retries and index pulse input.

The port is an input/output data port.

The outline of the data transfer operation of FDP in this example is as follows:
It is as follows.

(1) If the password supplied from the host matches the password assigned to itself, the FM (local processor) receives the command from the host.

(21FM sets the transfer address and number of bytes to FDP.

(31F M issues a command to the FDP.

(The 41FDP stores the data read from the disk in the data buffer.

(5) When data storage is completed, a transfer operation is started and the data is output to the host (MPU or DMAC) through the host interface.

FIG. 1 shows a block diagram of an embodiment of a password determination circuit provided in the host interface.

The password register holds the password assigned to the peripheral LSI on which it is mounted.

As this password register, an electrically writable programmable ROM is used.

With this configuration, the user can set any password B. Instead of using such a ROM, a storage circuit such as a flip-flop circuit may be used. In this case, each time the power is turned on, it is necessary to select the password register and write an arbitrary password A at the time of starting the system immediately thereafter. The register that holds this password data is not particularly limited, but
To maintain security, writing is permitted only once at system startup, and reading is disabled.

Password data is set from the host side prior to accessing peripheral LSIs such as the above-mentioned FDP. A comparison signal is formed from this password data write instruction signal. In response to this comparison signal, the comparator starts a comparison operation and outputs a match/mismatch detection signal between the password data B and the password A written in the password register. If both passwords A and B match, the comparator sets the match signal to high level. The high level of this match signal sets the SR flip-flop circuit, causing the output signal Q to go high. An access permission signal is generated by the high level of the signal Q, and the reception of commands sent from the host side is started. When an access from the host side as described above is started by such an access permission signal, an access instruction signal is generated to reset the SR79717071 circuit. This makes it a condition that the passwords match for the next access as well.

If the passwords A and B do not match, the comparator sets the matching signal to low level.

As a result, the output signal Q of the SR79717071 circuit remains at a low level, the access permission signal remains at a low level, and commands etc. sent from the host are not accepted.

By providing such a password determination circuit in a peripheral LSI such as the above-mentioned FDP, even if an unauthorized access is attempted due to a software bug or the like in the microcomputer system, the password determination circuit will eliminate it. This makes it possible to prevent a program from running out of control and destroying data in a peripheral LSI such as an FDP.

In addition to preventing data destruction due to password settings and software bugs as described above, it is also possible to prevent data destruction and data reading caused by malicious intent.

FIG. 2 shows a block diagram of an embodiment for explaining the password method.

In the method of setting a password using a password register as described above, there is a risk that the password may be deciphered by maliciously changing the password data one after another and accessing the password. Therefore, in this embodiment, a plurality of flip-flop circuits (latch circuits) which are not writable are used as the password register. A flip-flop circuit consists of, for example, two CMOS inverter circuits whose inputs and outputs are cross-connected to each other, and the logic threshold voltage of both inverter circuits, N-channel M
The element size and arrangement of the OS FET and the P-channel MO3FET are set symmetrically and designed so that the input capacitance and output capacitance are both equal. In this configuration, the data of each flip-flop circuit becomes undefined when the power is turned on. In other words, the probability that the logic becomes stable at "0" or "1" becomes 1/2, and indefinite data is formed. Therefore,
Even the user himself cannot know the password immediately after turning on the power. Reading the above-mentioned undefined data is enabled only once at the first access within a certain period of time after power is turned on. That is, the holding signal S of the flip-flop circuit FF
Reading of undefined data is permitted by controlling the gate to open. The flip-flop circuit FF is assigned a secret address and is first accessed within a certain period of time immediately after power is turned on to write set data, thereby generating the signal S and opening the gate. When the flip-flop circuit FF is set, it is automatically reset after a certain period of time, and cannot be accessed thereafter. As a result, only the user himself/herself who accurately knows the address of the flip-flop circuit FF and the setting method or setting conditions can read the password. In this method, the password changes every time the power is turned off, so even if the password is read out by some accident, it can be rendered meaningless the next time.

Note that a password may be provided even for one-time access to the flip-flop circuit.

In this embodiment as well, password data is set from the data bus and a comparison operation is performed by the comparator in the same way as in the embodiment shown in FIG.

The match signal of this comparator causes SR7971707
1 circuit is set and an access permission signal is generated.

If they do not match, the access permission signal will not be generated.

The effects obtained from the above examples are as follows. In other words, (1) the entered password is compared with the password assigned to the user, and only when the two match, access to the password is denied, making it possible to protect data.

(2) With the above (1), it is possible to prevent undesired data destruction due to malice or erroneous operation.

(3) Use the undefined data generated in the flip-flop circuit when the power is turned on as a password, and use the undefined data as a password.
By making the information readable only once and using it as a password, security can be strengthened.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the password determination circuit may be any circuit as long as it has a function of determining whether a held password matches/mismatches an input password. In addition to the above-mentioned FDP, the semiconductor integrated circuit device incorporating the password determination circuit may be any peripheral LSI having data input/output and certain processing functions. In addition to the password determination circuit mounted on the peripheral LSI in the microcomputer system, the method of using undefined data formed by a flip-flop circuit as a password when the power is turned on is applicable to
It can be widely used in password systems configured with various semiconductor integrated circuit devices, such as specific access permissions that require confidentiality for microprocessors or one-chip microcomputers.

The present invention can be widely used in peripheral LSIs and password systems in microcomputer systems.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, the input password is compared with the password assigned to the user, and only when the two match, the access can be denied, thereby making it possible to protect data. In addition, security can be strengthened by using undefined data generated in the flip-flop circuit when the power is turned on as a password, and using the undefined data as a password so that it can be read only once.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the password determination circuit according to the present invention, FIG. 2 is a block diagram showing an embodiment of the password determination circuit according to the present invention, and FIG. 3 is a block diagram showing an embodiment of the password determination circuit according to the present invention. Fair Isle Data
FIG. 2 is a block diagram illustrating an embodiment of a processor. FF...Flip-flop circuit

Claims (1)

[Claims] 1. A semiconductor integrated device having a data processing function, comparing an input password with a password assigned to the device, and permitting access only when the two match. circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device constitutes a peripheral device of a microcomputer. 3. A password method characterized in that undefined data generated in a latch circuit when the power is turned on is used as a password, and the undefined data can be read only once and used as the password.