JPH0398483A - Motor controller - Google Patents

Abstract

PURPOSE:To permit a device to come into a steady state quickly by counting up/down the differential clock between the detected rotational frequency of a motor and a desired value, and by setting a count value when the difference comes to nothing, to be a self correcting value and controlling a speed. CONSTITUTION:When a motor is started, then from an input terminal 39, reference clock phiREF and rotational angle speed signal DFG are fed, and from a control counter 40, the output of speed controlling signal SCS is generated, and they are added 53 to each other and are D/A-converted 48 and the output 49 is generated. In the meantime, logical operation is performed on the DPL signal of the decoded 51 output of an adder 53, the output of a coincidence counter 42, the signal DFG and retrigable signal RTB, and a U/D counter 50 and the coincidence counter 42 are set/reset. By a decoder 41, a difference between the signal SCS and a desired value is detected, and is counted up/down 50, and the difference is reduced, and counting is stopped by the output of the coincidence counter 42, and then count value is set to be a self correcting value and is added 53 to the signal SCS.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a control device for a motor such as a drum motor or a capstan motor of a VTR, and particularly to a control device for automatically correcting a steady speed error in a speed control system. The present invention relates to a motor control device configured as described above.

[Conventional technology]

Generally, the servo circuit of a VTR's drum motor or cab stan motor consists of two systems: a speed control system that keeps the motor's rotational speed constant and a phase control system that sets the rotational phase to a specified value. Digital servo has been adopted to improve performance and reliability. Among these, in the speed control system, in order to extremely reduce the steady speed error, an offset corresponding to the steady speed error is generated to reduce the steady speed error, as described in, for example, Japanese Patent Laid-Open No. 195757/1983. A speed self-correction device is used to correct the Here, a conventional motor speed control system will be explained using FIGS. 9 and 10. FIG. 9 is a block diagram showing this speed control system, in which 1 is a counter, 2 is a latch circuit, 3 is a digital/analog converter (hereinafter referred to as D/A
4 is rpp (low pass filter),
5 is a reference clock generator, 6 is a motor, and 7 is a driver.
8 is a speed self-correction value generator, and 9 is an FG detector. In the figure, when the motor 6 rotates, an FG signal with a period inversely proportional to the rotation speed is detected by the FG detector? is detected by and supplied to counter 1. Further, the reference clock φAffF generated by the reference clock generator 5 is also supplied to the counter 1. Here, the reference clock φRII
The station wave number f sty is set equal to the frequency fya of the FG signal when the motor 6 rotates at a steady speed with a difference k.

To be more specific, the counter 1 is a counter A. which counts the reference clock φJIffF. A counter B that counts the FG signal and these counters A. and a subtracter that generates a difference between the H count values. These counters A and B are reset simultaneously, and after the reset is released, counter A counts the reference clock φxzy and counter B counts the FG signal, respectively. These counters A. The count value of H is supplied to the subtracter, and the difference value is supplied to the latch circuit 2, but when the motor 6 is rotating at a steady speed with an error txL, the counter A is calculated by the rotation period of the motor 6. When φxzy is counted, the difference value output from the subtracter at this time is latched in the latch circuit 2, and then the counters A and B are reset and the above operation starts again. Therefore, the difference value latched by the latch circuit 2 represents the deviation of the current rotational speed of the motor 6 from the steady rotational speed. Hereinafter, when the motor 6 rotates at a steady rotation speed without error, this rotation period will be referred to as a target rotation period, and will be referred to as angular velocity and target angular velocity.

The difference value (i.e., the difference between the current rotation period of the motor 6 and the target rotation period) launched by the latch circuit 2 is converted into an analog speed error signal by the D/A converter 3, and then the LP
Some unnecessary harmonics are removed by F4 and the driver amplifier 7
The motor 6 is controlled by the output signal of the driver amplifier 7.

Therefore, when the current rotation period of the motor 6 is longer than the target rotation period, the speed of the motor 6 is controlled to accelerate.
Conversely, when the current rotation period is shorter than the target rotation period, the speed is controlled to reduce the speed.

By the way, in such a speed control system, a speed offset due to the influence of a certain amount of disturbance (voltage disturbance AV, }lucent disturbance A) cannot be ignored. Here, the voltage external aJV is a disturbance that affects the control voltage of the motor 6, which occurs due to constant variations of external analog components used in each circuit, characteristic variations due to temperature changes, time constant variations due to the moisture absorption state of the capacitor, etc. The torque disturbance 4τ is a disturbance that occurs due to a decrease in the torque of the motor 6 at low temperatures and variations in the characteristics of the motor 6, and affects the control voltage of the motor 6.

Therefore, conventionally, the speed self-correction value obtained by sequentially accumulating the speed error signals obtained from the LPF 6 is held in the speed self-correction value generator 8, and the driver amplifier 7 generates the speed error signal using this speed self-correction value. By performing this correction, disturbance components such as voltage disturbance 1V and torque disturbance 4τ in this speed error signal were canceled. Next, the speed self-correction operation will be explained using Fig. 10. However, in FIG. 10, the horizontal axis shows the angular velocity of the motor 60, and the vertical axis shows the control voltage from the driver amplifier 7 to the motor 6. In the figure, a characteristic 41 indicates the control voltage characteristic when the disturbance component (voltage disturbance AV, torque disturbance 4τ) is completely small, and a characteristic 42 indicates the control voltage characteristic when the disturbance component (voltage disturbance AV, torque disturbance 4τ) is completely small.
r. }This shows the control voltage characteristics when a torque disturbance (τ) is included. The rotational speed of the motor 6 is determined by the duty ratio of its drive signal, and the control voltage is defined as "BiJ", which is the level at which the duty ratio of the drive signal is fixed at maximum tx゛rr゜ (high level). Yes. When the control voltage is "Lo", it means that the duty ratio of the drive signal is at the Kino level when it is fixed at the minimum tL°L° (low level). First, in characteristic 11, the control voltage for setting the angular velocity of the motor 6 to the target angular velocity ω0 is expressed as the control center vo
= (control voltage Hi + control voltage Lo) / 2.

This characteristic j1 has disturbance components (voltage disturbance AV, }lux disturbance A)
When τ) is mixed, the characteristic at this time is tx, which is the characteristic j2 obtained by vertically shifting the characteristic l1 in parallel. In this characteristic l2, the target angular velocity ω. The control voltage according to ν1=ν. +v
(AV+lτ》), and from the control center v0, υ(AV+
Jr.) It will shift. Here, υ(AV+Jτ》
is the voltage offset of the ATM pressure that is affected by the disturbance command (voltage disturbance 4r. torque disturbance Aτ).

Therefore, in order to cancel this voltage offset,
A speed self-correction value in accordance with this voltage offset is stored in the speed correction value generator 8 in FIG. 9, and the speed self-correction voltage V (V+Aτ>
is added, and the speed of the motor 6 is controlled equivalently in accordance with the characteristic l1 tx.

[The problem that the invention attempts to solve]

However, in the above-mentioned conventional technology, although speed adjustment is automated, no consideration is given to the rise time of the motor 6 or the accuracy of the speed self-correction value, which are caused by the speed correction value generation process. 1. That is, in the above-mentioned prior art, when the motor 6 is started, speed error signals are accumulated to generate a speed self-correction value, and at the same time, speed self-correction is performed tx using this cumulative value. For this reason, the start-up characteristics of the motor 6 change. 5. Therefore, if the startup of the motor 6 becomes steep due to this speed self-correction, the rotational angular velocity will oscillate with a large amplitude around the target angular velocity during the transient period until the rotational angular velocity of the motor 6 stabilizes after startup. Therefore, the transition period becomes longer. In order to improve the accuracy of speed self-correction, it is necessary to generate a speed self-correction value until the rotational angular velocity of the motor 6 becomes stable. Therefore, the time required for speed self-correction is long < 7, C 2 Therefore, the retracting time of the motor 6 becomes longer.

Therefore, if an attempt is made to shorten the generation period of the speed self-correction value to shorten the pull-in time of the motor 6, the rotation of the motor 6 becomes ti'l! Is it stable? ．． This generation period ends before the speed self-correction value is set. Therefore, the accuracy of the speed self-correction value is low < tx, and the voltage offset of the speed control voltage of the motor 6 cannot be sufficiently compensated for. It is impossible to remove it.

Furthermore, if the start-up of the motor 6 is made gradual, the above-mentioned problem during the transient period will be resolved, but the start-up time after the motor 6 starts will be longer, and the period for speed self-correction will also be longer. ．． SUMMARY OF THE INVENTION An object of the present invention is to provide a motor control device that solves these problems, shortens the speed self-correction period, and obtains a stable speed self-correction value with high accuracy.

[l! Means to solve the problem]

In order to achieve the above object, the present invention provides a counting means for up-counting the clock on one side and down-counting the nuclear clock on the other hand when the rotational speed of the motor is larger or smaller than its target rotational speed; detection control means for detecting that the rotational speed of the motor is stabilized near the target rotational speed and stopping the counting operation of the counting means; means for causing the mosquito counting means to perform a counting operation only when the speed is within the speed lock range; and addition for adding the count value when the counting operation is stopped by the detection control means of the corpse counting means to the speed control signal as a speed self-correction value. and means. The present invention further provides determination means for determining whether the count value of the counting means is within a preset tolerance range, and determination means for determining whether the count value of the determination means is outside the tolerance range. Accordingly, a count gain converting means for changing the count gain of the counting means is provided.

The present invention also provides determining means for determining whether or not the self-correction value of prestart speed generated by the counting means is within a preset tolerance range; memory means for storing the speed self-correction value every time the speed self-correction value is obtained from the counting means; and a memory means for storing the speed self-correction value whenever the speed self-correction value generated by the counting means is controlled by the determination means and is within the permissible range. switch means for selecting a speed self-correction value stored in the memory means when the speed self-correction value generated by the counting means is outside the permissible range;

[For production]

The counting operation of the counting means is started when the rotational speed of the motor enters the speed range.

As a result, the counting means requires only the minimum necessary number of bits, and the time required to generate the speed self-correction value is also minimized, resulting in good motor control responsiveness.

“Also, the speed self-correction value is always monitored, and if the speed self-correction value exceeds the permissible range while generating the speed self-correction value, (1) changing the count gain of the counter means or (2) ) By using the previously generated speed self-correction value instead of the currently generated speed self-correction value, errors in the speed self-correction value can be prevented.

〔Example〕

First, a VTR using the present invention will be explained with reference to FIG. However, in the same figure, 10 is a magnetic tape, an IL
12 is a recording/reproducing head, 13 is a tack head that detects the rotation phase of the Dojim motor 14, 15 is a DFG head that detects the rotational angular velocity of the drum motor 14, 16 is a cab stan, 17 is a capstan motor, and 1B is a cab stan. The CFG head detects the rotational angular velocity of the motor 170, and 19 indicates the operation of the velocity self-correction value generator 20.23. 20 is a speed self-correction value generator for the drum motor IA 14; 21 is a speed controller for the drum motor 14; 22
is a phase controller for the drum motor 14, 25 is a speed self-correction generator for the cab stan motor 17, 24 is a speed controller for the cab stan motor 17, 25 is a branching unit, 26 is a phase controller for the cab stan motor 170, 27- 30 is an adder,
31.32 is a digital/analog converter (hereinafter referred to as A/D
converter). 53.34 is LPF, 55 is drum motor 1
4 driver amplifier, 36 capstan motor 17
37.38 is the reference voltage source.
In FIG. 3, first, control during the process in which the drum motor 14 moves from a stopped state to a steady rotational angular velocity state g will be explained. When the drum motor 14 starts up, the phase controller 22 and the speed self-correction value generator 20 are in an OFF state.

1, the speed controller 21 is connected to the DFG from the DFG head 15.
A signal is supplied, its period is compared with the target DFG period, and the difference value therebetween is outputted as the speed control signal DE. As a result of the above, the speed self-correction value DV output from the speed self-correction value generator 20 and the output signal of the phase controller 22 are in a zero state. Therefore, only the speed control signal DB output from the speed controller 21 is sent to the adder 50. 29 to the D/A converter 31, where it is converted into an analog speed control signal. This speed control signal is supplied to the LPF 5S, unnecessary high-frequency waves are converted into P waves, and the resulting signal is supplied to the driver amplifier 35, thereby driving the drum motor 14.

Then, when the rotational speed of the drum motor 14 rises to its speed lock range (a range of ±x% of the target angular velocity of the drum motor 14, which is, for example, a range of ±5 points), a speed self-correction value is generated. The device 20 starts operating and generates a velocity self-correction value DV. However, phase controller 2
2 is also in the OFF state at this time. The speed filljll signal DE outputted from the speed controller 21 and the speed self-correction value DV outputted from the speed self-correction value generator 20 are added by an adder 30, and the output signal is sent via an adder 29 to the D/ It is supplied to the A converter 51, and thereafter the speed of the drum motor 14 is controlled in the same manner as described above. after that,
When the generation of the speed self-correction value for the drum motor 14 by the speed self-correction value generator 20 is completed as described later, the speed control of the drum motor 14 is completed and the drum motor 14 rotates at the target angular velocity.

When the speed control of the drum motor 14 is completed in this way, the phase controller 22 starts operating at the same time.

Here, the rotational phase signal TP of the drum motor 14 is detected by the tack head 13 and provided to the phase controller 22. The phase controller 22 compares the reference phase and the rotational phase signal rp, outputs a phase control signal representing the phase difference between them, and adds this to the output signal of the adder 30. This completes speed control and phase control. Also for the cab stan motor 17, the speed controller 24. Phase controller 26 and speed self-correction value generator 25
The control for the drum motor 14 is performed in the same manner as described above. In other words, the speed control of the cabstan motor 17 is performed using the CFG which indicates the rotation period of the capstan motor 17 as a comparison signal with the target CFG period of the speed controller 24.
The CFG signal from the head 1B is used, and its phase is controlled by using a signal obtained by frequency-dividing this CFG signal by a divider 25 as a comparison signal with respect to the 26° C. reference phase of the phase controller. Hereinafter, since the driving method of the cab stan motor 17 and the operation of the speed self-correction value generator 23 are the same as those of the drum motor 14, their explanation will be omitted here. Next, embodiments of the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a motor control device according to the present invention, in which 59 is an input terminal for a reference clock φJIJl7, 40 is a control counter, and 41 is a check mark indicating whether the current rotational angular velocity of the motor is faster than the target angular velocity. Decoder to determine if it is slow,
42 is a coincidence counter that counts the output of the decoder 41 by a specified value and outputs a count end signal of ゜H゜ (tolerance level) upon completion of the count; 46 is an inverter; 44.
45 is an AND gate, and 46 is a third clock as a basic clock.
In the figure, 47 is the input terminal for the DFG signal, 47 is the input terminal for the IJ} regregable signal, 48 is the D/A converter, 49 is the output terminal for the speed control signal, and 50 is the U/n (acp/n) that generates the speed self-correction value. down) counter, 51 is @H when the rotational angular frequency of the motor is within the speed range.
52 is a latch circuit, and 55 is an adder.

Figure 2 shows the start-up process of the motor and the mode of the U/0 counter 5o, with time on the horizontal axis and the angular velocity of the motor on the vertical axis. In Figures 1 and 2, the control Counter 4o is the third
It corresponds to the speed controller 21 in the figure, and is composed of the counter 1 and the control circuit 2 in Figure 9. Reference clock φJgF from input terminal 39 at the same time as motor startup
A speed control signal is output from the control counter 40 to which the and DFG signals are supplied, and is supplied to the adder 53.
3 is converted into an analog signal by a D/A converter 48 and output from an output terminal 49.゛The output signal of the adder 55 is also supplied to the decoder 51. As shown in FIG. 2, this decoder 51 has a speed lock range set around the target angular velocity of the motor, and determines whether the rotational angular velocity of the motor is within the speed lock range based on the output signal of the adder 53. It is determined whether or not. When the rotational angular velocity of the motor is within this speed lock range, the output signal DPL of the decoder 51 is “H°” and “K”.
When this rotational angular velocity is within the velocity lock range, it is set to "L".

A retriggerable signal R is also input to the input terminal 47 of the housing.
TB is normally °H", and when resetting the speed self-correction value at an arbitrary time, it is set to "L".

Therefore, when the motor starts from a stopped state, the output signal DPL of the decoder 51 is ゜H'', and if the trigger pull signal RTB is ゜H゜ at this time, the output signal DPL of the decoder 51 is ゜H゜.
The output signal of 50 is also held at "H°" and the U/n counter 50
and the coincidence counter 42 are set to a reset state. Here, the DFG signal is input from the input terminal 46 as the clock φ of the U/0 counter 50, but the coincidence counter 42
When is in the reset state, its output signal is ゜H“
The inverter 43 inverts the signal to .L. and supplies it to the AND gate 44. For this reason, the DFG signal from the input terminal 46 is blocked by the AND gate 44 and
/n to be supplied to the counter 50. When time T has elapsed after the motor was started, and the rotational angular velocity of the motor reaches the speed lock range, as shown in FIG.
The output signal DPI of the decoder 51 becomes "L°", and the output signal of the AND gate 45 becomes "L°" and "U".
/n counter 50 and coincidence counter 42 are reset. Along with this, the output signal of the coincidence counter 42 is @
The signal r is inverted to "H" by the inverter 45 and supplied to the AND gate 44.

As a result, DFGCFa from the input terminal 46 is supplied to the U/n counter 50 via the AND gate 44 as a clock φ.

On the other hand, the decoder 41 determines whether the current rotational angular velocity of the motor is larger or smaller than the target angular velocity based on the output of the control counter 40, sends this determination result to the U/0 counter 50, and outputs the current rotational angular velocity to the target angular velocity. When the angular velocity matches, a match pulse representing this is sent to the match counter 42. According to the determination result of the decoder 41, the U/n counter 50 detects the DF when the current rotational angular velocity is smaller than the target angular velocity.
The G signal is counted up, and when the current rotational angular velocity is greater than the target angular velocity, the DFG signal is counted down. Therefore, when the rotational angular velocity of the motor approaches the target angular velocity and enters the speed lock range, as shown in Figure 2, it approaches the target angular velocity while vibrating approximately around the target angular velocity, but during this vibration period, Every other period T@*T4 during which the rotational angular velocity of the motor is smaller than the target angular velocity
+ Ta +... The U/n counter 50 counts up, and every other period T 1 +T, .・・・・・・
- The U/n counter 50 counts down.

In this way, when the motor's rotational angular velocity enters the speed lock range, it oscillates, approaches the target angular velocity, and finally becomes constant, but the difference between the rotational angular velocity and the target angular velocity at this time is the offset amount of the rotational angular velocity. And. U/n counter 50 forms a speed self-correction value that cancels this amount of offset. For this purpose, the U/n counter 50 is
When the rotational angular velocity of the motor becomes constant f(), the counting is terminated, and the count value at this time is latched in the latch circuit 52 as a speed self-correction value. However, when the rotational angular velocity of the motor is constant The matching circuit 42 determines whether or not p is reached.

That is, when the coincidence counter 42 is reset as described above, it starts counting coincidence pulses from the decoder 41, and when it reaches a count value representing a period during which the rotational angular velocity of the motor is constant, its output is The signal is set to 1H". As a result, the output signal of the inverter 43 becomes ゜L゜, and the DFG signal from the input terminal 46 is input to the AND gate 44.
The U/n counter 50 stops counting. Also, depending on the rising edge of the output signal of the coincidence counter 42 from “L° to “H°”, the current U/
The count value of the 0 counter 50 is latched in the delay circuit 52 as a speed self-correction value.

Here, it is assumed that the count value of the coincidence counter 42 is 7 when the rotational angular velocity of the motor is constant and is equal to 1, but it is not limited to this.

The speed self-correction value of the latch circuit 52 is added by an adder 55 so that the offset amount of the speed control signal from the control counter 40 is canceled. The output signal of the adder 53 is converted into an analog speed control signal by a D/4 converter 48, and outputted from an output terminal 49 for use in motor speed control. In this way, the motor rotates at the target angular velocity °C. As described above, according to this embodiment,
Since the speed self-correction starts generating after reaching the speed lock range, the speed self-correction value can be generated in the minimum necessary period. The number of U/n counter 500 bits can be kept to the minimum necessary. FIG. 4 is a block diagram showing another embodiment of the motor control device according to the present invention, in which 54 is a count gain switcher for switching the count gain of the U/1) counter 50;
is the upper limit indicating the allowable range of the speed self-correction value, which will be described later. Memory that stores the lower limit data, 56 is a U/n counter 500
The upper limit of the count value and the speed self-correction value stored in the memory 55. This is a comparator for comparing lower limit data, and parts corresponding to those in FIG. 1 are given the same reference numerals and redundant explanations will be omitted. In Fig. 1, when the count gain of the bt counter 50 is high, that is, when the frequency of the DFG signal, which is the count clock of the U/0 counter 50, is high, the motor rises abruptly and the speed self-corrects. Although the time required is shorter, the accuracy of the speed self-correction value is reduced. Furthermore, when the count gain of the U/n counter 50 is low, that is, when the clock frequency of the U/n counter 50 is low, the accuracy of the speed self-correction value is required to be high.
On the other hand, the time required for speed self-correction becomes longer.

The embodiment shown in FIG. 4 uses a U/D counter 5 to optimize the speed self-correction period and the accuracy of the speed self-correction value.
This embodiment is designed so that the 00 count gain can always be optimally set, and this embodiment will be explained below with reference to FIG. Note that, similarly to FIG. 2, FIG. 2 (.) shows the start-up characteristics of the motor, with the horizontal axis representing time and the vertical axis representing the rotational angular velocity of the motor. Same figure (b'').
(,) shows time on the horizontal axis and the count value (speed self-correction value) of the U/n counter 50 on the vertical axis. However, U/
The count gain of the D counter 50 is higher in the figure (,). In FIG. 4, the count value of the U/f) counter 50 is also supplied to a comparator 56, and the upper limit value from the memory 55 is supplied to the comparator 56. It is constantly compared with lower limit data to determine whether this count value is within or outside the self-permissible speed range. Then, the count gain switch 54 switches the count gain of the U/0 counter 50 in accordance with this determination result.

Therefore, in the speed self-correction value production process in Figure 5 (,) where the count gain is high based on the characteristics shown in Figure 5 (A), the slope of the count is large, so compared to Figure 5 (A), Generates speed self-correction error. Therefore, in order to reduce this speed self-correction error, as shown in the figure (,), the comparator 56 has a speed self-correction value permissible range, an Hl over range above this permissible range, and an LO over range below this permissible range. area is set, and the comparator 56 is set. U/n
If the count value at which the count operation of the counter 50 switches from up-counting to down-counting is in the El over range, a gain DOWN control signal is output to lower the count gain of the U/n counter 50, and this is in the LO over range. If so, output a gain UP control signal to increase the count gain. Also,
If the count value that switches from down counting to up counting is in the El over area. U/n counter 5
00 count gain is increased, and if this is in the LO over area, the count gain is increased. In this way. The lc. U
/n counter 500 count gain is set, and optimization of the speed self-correction period and the accuracy of the speed self-correction value is realized.

FIG. 6 is a block diagram showing a specific example of the count gain switch 54 in FIG. is an output terminal to which the output of the switch 61 is supplied;
63 is an input terminal for the DFG signal, 64 is an input terminal for the gain UP control signal output from the comparator 56, and 65 is a gain D OW N f'j! that is also output from the comparator 56. J
This is the input terminal for the l'' signal. Changing the count gain of the U/0 counter 50 in FIG. 4 can be achieved by dividing the clock of the U/N counter 50. Therefore, as shown in FIG. So 11
, DFG as a clock input from the input terminal 63
The signal is frequency-divided by two frequency dividers 57 to 60 to produce four types of divided outputs, so that the count gain can be changed in four ways. Furthermore, each of the branching units 57 to 60 may have a different branching ratio and number of stages. switch 61
divider 5 by 2 according to the gain UP control signal from the input terminal 64 and the gain DOWN control signal from the input terminal 65.
Select any output from 7 to 60.

As described above, in this specific example, by changing the division ratio of the DFG signal. U/n counter 50 force r/
The gain can be changed.

FIG. 7 is a block diagram showing still another embodiment of the motor control device according to the present invention, in which 66 is a switch, 67 is a memory, and FIG. Parts corresponding to those in Fig. 4 are given the same reference numerals and redundant explanations will be omitted. Also, Figure @8 shows the operation of this embodiment,
Similarly to FIG. 5 (,), it shows the process of generating the speed self-correction value.

This embodiment prevents errors that occur in the speed self-correction value when the motor's start-up characteristics go into an abnormal state due to the influence of the outside environment (sudden temperature change, etc.) during motor speed control. .

In FIG. 7, the speed self-correction value outputted from the U/N counter 50 is normally sent to a comparator 56 via a switch 66.
and is compared with the upper and lower limit data of the speed self-correction value in the memory 56. As a result, this time the U/D counter was 50.
The speed self-correction value obtained is above this. When the speed self-correction value determined by the lower data is within the allowable range, this is selected by the switch 66 and latched by the latch circuit 52, and is also stored in the memory 67. Therefore, U/
When the 0 counter 50 generates the next speed self-correction value, the memory 67 stores the speed self-correction value within the final storage range generated in the previous case.

On the other hand, if the speed self-correction value generated by the U/N counter 50 this time exceeds the above-mentioned allowable range as at time t1 in FIG. is an error and h? J:L. The switch 66 is switched to the memory 67 to select, for example, a previously generated speed self-correction value stored therein, and this speed self-correction value is applied to the control circuit 52.

As described above, according to this specific example, when the speed self-correction value exceeds the allowable range and is generated, the speed self-correction value previously stored in the memory 67 is substituted, so that the speed self-correction value is Overcorrection errors can be prevented.

11. Although each of the above embodiments concerns the speed control of the drum motor, the same applies to the speed control of the capstan motor.

[Efficacy of invention]

As explained above, according to the present invention, (1) the speed self-correction generation operation is started after the rotational angular speed of the motor rises and reaches within the preset speed range; therefore, the speed self-correction value is The time it takes to generate the speed self-correction value is shortened, and the number of bits in the counter that generates the speed self-correction value can be kept to the minimum necessary, reducing the time it takes for the motor to reach a steady state and reducing the circuit size. .

(2) The count gain of the counter that generates the speed self-correction value can be changed according to the deviation of the speed self-correction value from a preset tolerance range, thereby ensuring the accuracy of the speed self-correction value at all times. {3} When the speed self-correction value exceeds the preset allowable range, the speed self-correction value determined previously can be substituted, and thereby the speed self-correction value It is possible to prevent malfunctions caused by errors.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing an embodiment of a motor control device according to the present invention, FIG. 2 is a diagram showing its operation, and FIG. 3 is a diagram showing a servo mechanism of a magnetic recording/reproducing device using the motor control device according to the present invention. FIG. 4 is a block diagram showing another embodiment of the motor control device according to the present invention, FIG. 5 is a diagram showing its operation, and FIG. 6 is a specific example of the count gain converter in FIG. 4. FIG. 7 is a block diagram showing still another embodiment of the motor control device according to the present invention, FIG. 8 is a diagram showing its operation, and FIG. 9 is a block diagram showing a conventional motor speed control system. , FIG. 10 is a diagram showing the speed self-correction operation in FIG. 9. 40...1... 42...46...48...48...49...50・・・・・・・・・ 51・・・・・・・・・ 54・・・・・・・・・ 55・・・・・・・・・ 66・・・・・・・・・ Control counter 41...Decoder coincidence counter 44...1...Input terminal for AND gate clock Output terminal for D/I converter speed control signal Up/down counter decoder 53... ...Adder count gain converter

Claims (1)

[Claims] 1. Detecting the rotational speed of a motor and forming a speed control signal according to the difference between the rotational speed and a target rotational speed of the motor;
In a motor control device configured to control the rotational speed of the motor, a clock is counted up when the rotational speed of the motor is larger than the target rotational speed and when it is smaller than the target rotational speed, and the clock is counted down on the other hand. a counting means; a detection control means for detecting that the rotational speed of the motor has stabilized near the target rotational speed and stopping the counting operation of the counting means; and a detection control means for stopping the counting operation of the counting means. 1. A motor control device comprising: an addition means for adding a count value of the time to the speed control signal as a speed self-correction value, so that an offset value of the speed control signal can be removed. 2. The motor according to claim 1, further comprising means for causing the counting means to perform a counting operation only when the rotational speed of the motor is within a predetermined speed lock range including the preset target rotational speed. Control device. 3. In claim 1 or 2, there is provided a determining means for determining whether or not the count value of the counting means is within a preset tolerance range; and a count gain converting means for changing the count gain of the counting means in accordance with the determination of the motor, the motor being configured such that the count value of the counting means can always be maintained within the permissible range. Control device. 4. In claim 3, the count gain conversion means is a frequency division means for dividing the clock of the counting means, and the frequency division ratio is variable according to the determination result of the determination means. Motor control device. 5. In claim 1 or 2, determining means for determining whether or not the speed self-correction value generated by the counting means is within a preset tolerance range; memory means for storing the speed self-correction value each time the speed self-correction value within the range is obtained from the counting means; switch means for selecting a self-correction value and selecting a speed self-correction value stored in the memory means when the speed self-correction value generated by the counting means is outside the allowable range; A motor control device characterized in that a speed self-correction value selected by the switch means is added to the speed control signal.