JPH039647B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to hysteresis circuits. As shown in Figure 1, a conventional comparator with hysteresis characteristics consists of a comparator CM, resistors R ₁ and R ₂ , a reference voltage source V _REF, etc., and the input voltage V _IN gradually increases from the ground level to the power supply voltage V When rising to _DD ,
The input voltage V _IN , _H when the output voltage V _OUT transitions from the power supply voltage V _DD level to the ground level is approximately given by equation (1), and similarly, the input voltage V _IN gradually transitions from the power supply voltage V _DD level to the ground level. level, the output voltage
The input voltage V _IN , _L when V _OUT transitions from the ground level to the power supply voltage V _DD level is given by equation (2). V _IN , _H = R ₂ /R ₁ +R ₂ V _REF +R ₁ /R ₁ +R ₂ V _DD (1) V _IN , _L = R ₂ /R ₁ +R ₂ V _REF (2) However, here V _REF is the potential of the reference voltage source V _REF , and 0V _REF <V _DD . Therefore, this conventional circuit becomes a hysteresis circuit with a hysteresis width of V _H = V _IN , _H − V _IN , _L = R ₁ /R ₁ + R ₂ V _DD ,
Malfunctions caused by electrical noise superimposed on the input voltage V _IN can be reduced. However, these are cases where it is assumed that the comparator CM reference voltage source V _REF is ideal, and the circuit configuration as it is is not suitable for integration into an integrated circuit for the following reasons. First, V _IN , _H and V _IN , _L fluctuate due to the internal impedance of the reference voltage source V _REF , so this internal impedance must be extremely low.
In the case of an integrated circuit, when the reference voltage source is applied to other circuits, it cannot be constructed by simply resistor division of the power supply voltage, and a buffer stage is required. Furthermore, although the output impedance of the comparator CM is ideally zero, it is actually not zero, and V _IN , _H and V _IN , _L vary. In order to suppress this fluctuation, it is necessary to select the resistance values of R ₁ and R ₂ sufficiently high compared to the output impedance of the comparator CM. It is necessary to take measures such as increasing the size or increasing the size of the output transistor of the comparator CM to lower the output impedance, both of which are disadvantageous because they lead to an increase in the element size. In view of these points, the present invention provides a reference voltage source V _REF
It does not depend on the internal impedance of the
The present invention aims to provide a hysteresis circuit with a comparator configuration suitable for CMOS integrated circuits. According to the present invention, each of two outputs having opposite phases to each other of a differential amplifier configured by applying an input voltage to one gate of a pair of field effect transistors and applying a reference voltage to the other gate is first and second transistors of one conductivity type connected to the gate;
and third and fourth transistors of other conductivity types connected in series with each of these transistors, the drains of the third and fourth transistors being cross-connected to the gates of the other transistor, respectively, and the drains of the third and fourth transistors being cross-connected to the gates of the other transistor, , a hysteresis circuit characterized in that the current supply capacity of the second transistor is smaller than the current supply capacity of the third and fourth transistors, respectively. Next, the present invention will be explained in detail according to an embodiment thereof using the drawings. FIG. 2 is a circuit connection diagram showing one embodiment of the present invention. Source V _REF , input voltage
V _IN is applied, one output obtained from the connection point N ₁ of the drain of load 7 and FET 9, and one output obtained from the connection point N 1 of the drain of load 7 and FET 9.
Another one obtained from the connection point N ₂ of the drain of 10
After converting the voltage amplitude of the two outputs by a circuit consisting of FETQ ₁ , Q ₂ , Q ₃ , and Q ₄ , the inverter circuit consisting of FETQ ₅ and Q ₆ is used as a buffer amplifier 13 to amplify and output to the output terminal Vo. be. The operation and hysteresis characteristics of this circuit will be explained below based on the drawings. In the circuit shown in Figure 2, FETQ ₁ and Q ₂ , FETQ ₃ and
It is assumed that Q ₄ , FETs 9 and 10, and loads 7 and 8 are each symmetrical elements. These are on integrated circuits.
Matching can be easily achieved by arranging elements at adjacent positions or using the same pattern on a mask. Now, if the current supply capacity of FETQ ₁ and Q ₂ is sufficiently large compared to the current suction capacity of FETQ ₃ and Q ₄ , the contacts N ₁ , N ₂ , N ₃ ,
For example, as shown in Figure 3, the DC transfer characteristic for input voltage V _IN of N ₄ is based on the straight line V _IN = V _REF .
N ₁ and N ₂ and N ₃ and N ₄ are symmetrical, and in this case, the contact point N when V _IN is changed from a low potential to a high potential and when it is changed from a high potential to a low potential. ₄ pass on the same trajectory, so if the circuit threshold of the inverter circuit 13 is set to 1/2 of the power supply voltage, the potential of the output terminal Vo is reversed at the position of V _IN = Vth in Figure 3, causing hysteresis. Has no characteristics. This invention particularly applies to FETQ ₃ and Q ₄ .
By selecting the element size ratio for FETQ ₁ and Q ₂ ,
By making the current supply capacity of FETQ ₁ and Q ₂ relatively smaller than the current absorption capacity of FETQ ₃ and Q ₄ ,
Contact N ₃ or contact for changes in input voltage V _IN
The rate of increase in the potential of N ₄ is made relatively slow,
Hysteresis characteristics are achieved by making the trajectories of contact _N3 and contact _N4 asymmetrical with respect to V _IN = V _REF when the input voltage V _IN changes from a low potential to a high potential and from a high potential to a low potential. This is what you get. This hysteresis characteristic will be quantitatively explained below. Here, in order to quantitatively evaluate the current supply ability of the FET, equations (3) and (4) are defined. I _DS = β / 2 (V _GS - V _T ) ² - (3) I _DS = β [(V _GS - V _T )・V _DS - V _DS ² /2] - (4) However, in equation (3) I _DS is the drain-source current when the FET is in the saturation region, and is
I _DS is the drain-source current when the FET is in the triode region, and V _GS , V _DS , and V _T are the absolute values of the gate-source voltage, drain-source voltage, and FET element threshold voltage, respectively. where β is a parameter with the unit of A/V ² ,
It is obtained by multiplying K, which has a unit of A/V ² specific to the process, by the ratio of the channel width W and channel length L of the FET, such as β=K·W/L. After that, by adding the number of each FET as a suffix to V _GS , V _T , and β of each FET, each
Let us show the current of the FET. Figure 4 shows the DC transfer characteristics of contacts N 3 and N 4 when the input voltage V _IN is changed from a low potential to a high potential, and Figure 5 shows the DC transfer characteristics of contacts N ₃ and N ₄ when the input voltage V _IN is changed from a high potential to a low potential. Figure 6 shows the DC transfer characteristics of contacts N ₃ and N ₄ when the input voltage V _IN changes.
The DC transfer characteristics of N ₁ and N ₂ are shown respectively. First, in Fig. 4, if the input voltage V _IN is at a much lower potential than the reference voltage V _REF , the constant current source 11
Most of the current flows through the current path between the load 8 and the FET 10, the potential of the contact _N1 is almost close to the potential of the power supply voltage _VDD , and the potential of the contact _N2 is only the voltage drop determined by the current value of the constant current source 11 and the load 8. The potential is lower than the power supply voltage _VDD . This allows FETQ ₁ , Q ₄
is non-conductive, FETQ ₂ and Q ₃ are conductive, the potential of contact N ₃ is approximately the potential of the power supply voltage V _SS , the potential of contact N ₄ is approximately the potential of the power supply voltage V _DD , and the output terminal Vo is approximately the potential of contact N ₄
This is the inverted output of , that is, the potential of the power supply voltage V _SS . By gradually increasing the potential of the input voltage V _IN from this state, a part of the current of the constant current source 11 begins to flow in the current path of the load 7 and FET 9, and the current of the load 8 and FET 10 increases by this amount. Decrease.
Since loads 7 and 8 and FETs 9 and 10 are symmetrical elements, the rate of increase/decrease in this current is symmetrical with respect to V _IN =V _REF , and the rate of increase/decrease in the potential of contacts N ₁ and N ₂ is also symmetrical.
It is symmetrical about V _IN =V _REF . This results in
The current supply capability of FETQ ₁ gradually increases,
The current supply capability of FETQ ₂ gradually decreases. If the input voltage V _IN is further increased from this state, the current capability of FETQ ₁ will further increase, so
The potential of contact _N3 gradually rises from the potential of the power supply voltage V _SS , and it is in a non-conducting state.
The current capability of FETQ ₄ also increases gradually. Here, the potential of the output terminal Vo changes from the power supply voltage V _SS to the power supply voltage
The point where the potential transitions to V _DD is when the current capabilities of FETQ ₂ and FETQ ₄ become equal, and when equation (5) holds true, at which time the required gate-source voltage of FETQ ₄ V _GS4 is derived from equation (5) as shown in equation (6). β ₂ /2 (V _GS2 - V _T2 ) ² = β ₄ /2 (V _GS4 - V _T4 ) ² -(5
) At the same time, at contact N ₃ , FETQ 1 is in the saturation region and FETQ ₁ is in the triode region.
Since the currents of FETQ ₃ are equal, the following equation (7) holds true.
However, from now on, for the sake of simplicity, we will assume that V _SS =0. β ₁ /2 (V _GS1 −V _T1 ) ² = β ₃ [(V _DD −V _T3 ) ・V _G
S4 −V _GS4 ² /2] - (7) At this time, it goes without saying that V _DS3 = V _GS4 holds true, and the gate potential of FETQ ₃ is almost equal to the power supply voltage V _DD until just before the transition. It is electric potential. Since the above equations (6) and (7) hold simultaneously, equation (6) can be
By substituting into equation (7), the following equation (8) is obtained. Here, V _GS1 and V _GS2 are each given by the potential difference between the potential of the power supply voltage V _DD and the potential of contacts N ₁ and N ₂ , and these are symmetrical with respect to V _IN = V _REF , so V _IN =
V _GS1 and V _GS2 in V _REF are set as Vc, and the variable x can be defined as shown in the following equations (9) and (10), as shown in FIG. V _GS1 = Vc + x - (9) V _GS2 = Vc - x - (10) By substituting equations (9) and (10) into equation (8) and solving the quadratic equation for x, x becomes (11 ) can be obtained as shown in the formula. However, β ₂ / β ₄ = β ₁ / β ₃ , V _T1 = V _T2 , V _T3
= V _T4 . x=-C/2+1/2 {C ² -4 [(Vc-V _T1 -C) (Vc -V _T1 )-1/2・β ₃ /β ₁・V _T3・(2V _DD −3V _T3 )] } ^1/2 -(11
) however,

[Formula] In other words, when the input voltage V _IN is gradually increased from a low potential, the point at which the potential of the output terminal Vo is reversed is when the potentials of contacts N ₁ and N ₂ satisfy equations (9) and (10). The value of x at this time is calculated using equation (11) using β ₁ /β ₃ as a parameter, as shown in FIG. 7, for example. Note that the calculation example shown in FIG. 7 is based on the following conditions. Curve A: V _DD = 5V, V _T = 1V for each FET, Vc =
1.5V Curve B: V _DD = 3V, V _T of each FET = 0.5V, Vc =
0.8V Curve C: V _DD = 10V, V _T = 1V for each FET, Vc =
2.0V Curve D: V _DD = 20V, V _T = 1V for each FET, Vc =
2.5V Curve E: V _DD = 30V, V _T of each FET = 1V, Vc =
3V curve F: V _DD = 40V, V _T = 2V of each FET, Vc =
4V curve G: V _DD = 50V, V _T = 2.5V for each FET, Vc
= 5V Curve H: V _DD = 60V, V _T of each FET = 3V, Vc =
6V Note that once the potential of the output terminal Vo is inverted, even if the input voltage V _IN is further increased, the state of the output terminal Vo does not change. Here, the differential amplifier 12 for the input voltage V _IN
Let A _V be the DC voltage gain of A _V
is defined by equation (12). A _V = x/V _H −V _REF - (12) However, V _H is the input voltage V _IN where this transition occurs
is the value of , which gives the hysteresis width on one side
V _H −V _REF is obtained by equation (13). V _H −V _REF = x/A _V − (13) The above is a case where the input voltage V _IN is raised from a low potential. Next, let us change the input voltage V _IN to the reference voltage
The DC transfer characteristics of contacts N ₃ and _{N 4} when lowered from _a potential much higher than V _{REF are} as shown in _FIG . Due _{to the symmetry of}
Due to this symmetry, when V _IN = V _L , the output terminal
The potential of Vo changes from the potential of the power supply voltage V _DD to the power supply voltage V _SS
V _L at this time is similarly given by equation (14). V _REF - V _L = x/A _V - (14) In this case as well, no change in state occurs even if the input voltage V _IN is lowered further than V _L. That is, from equations (13) and (14), the circuit of the present invention becomes a hysteresis circuit with a hysteresis width of V _H −V _L = 2x/A _V , and this hysteresis width is determined by β ₁ /β ₃ and the differential amplifier. DC voltage gain of 12
It can be arbitrarily selected by selecting A _V appropriately. At this time, as shown in the calculation example in FIG. 7, this circuit can be realized using a C-MOS process. for example
When V _DD is set to 3V to 60V, it is possible to provide hysteresis characteristics by appropriately selecting β ₁ /β ₃ . Furthermore, in this circuit, the reference voltage source is received at high impedance at the gate of the FET 10, so it is stable regardless of the internal impedance of the reference voltage source, and does not adversely affect the reference voltage source. Furthermore, the above explanation
FETQ ₁ , Q ₂ are P channel FETs, FETQ ₃ , Q ₄ ,
9 and 10 are N-channel FETs, and it is assumed that V _DD > V _SS , but it goes without saying that a similar hysteresis circuit can be obtained by reversing the polarity of each FET and the relationship between the power supply voltages. . As described above, according to the present invention, hysteresis characteristics can be easily obtained with a very small number of elements and a simple circuit configuration, and the parameters that determine the hysteresis width are β ₁ /β ₃ and the DC voltage of the differential amplifier. Since it is an element that is easy to control, such as the gain A _V , it exhibits stable characteristics and can provide a hysteresis circuit suitable for integration into an integrated circuit, which has great practical benefits.

[Brief explanation of drawings]

FIG. 1 shows an example of a conventional circuit. FIG. 2 shows a circuit connection diagram of an embodiment of the present invention. FIG. 3 shows DC transfer characteristics when the circuit configuration of the present invention does not exhibit hysteresis operation. FIG. 4, FIG. 5, and FIG. 6 each show DC transfer characteristics explaining the hysteresis characteristics of the present invention. FIG. 7 shows an example of calculating the hysteresis width. V _DD V _SS : Power supply line, V _IN : Input voltage, V _S : Output terminal, R ₁ , R ₂ : Resistance, V _REF : Reference voltage source, Q ₁ ,
Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆ , 9, 10: FET: 7,
8: load, 11: constant current source, 12: differential amplifier,
13: Inverter circuit, N ₁ , N ₂ , N ₃ , N ₄ : Contact.

Claims (1)

[Claims] 1 A differential amplifier is constructed by applying an input voltage to one gate of a pair of field effect transistors and a reference voltage to the other gate, and each of the two outputs of the differential amplifier having opposite phases to each other. comprising first and second transistors of one conductivity type connected to the gates and third and fourth transistors of the other conductivity type connected in series with each of these transistors, the drains of the third and fourth transistors; are each cross-connected to the gate of the other transistor, and the current supply capabilities of the first and second transistors are smaller than the current supply capabilities of the third and fourth transistors, respectively.