JPH0394468A - Laminated type solid-state image sensing device - Google Patents
Laminated type solid-state image sensing deviceInfo
- Publication number
- JPH0394468A JPH0394468A JP1230482A JP23048289A JPH0394468A JP H0394468 A JPH0394468 A JP H0394468A JP 1230482 A JP1230482 A JP 1230482A JP 23048289 A JP23048289 A JP 23048289A JP H0394468 A JPH0394468 A JP H0394468A
- Authority
- JP
- Japan
- Prior art keywords
- pixel electrode
- insulating layer
- imaging device
- state imaging
- pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003860 storage Methods 0.000 claims abstract description 8
- 238000003384 imaging method Methods 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 abstract description 10
- 230000007547 defect Effects 0.000 abstract description 8
- 230000035945 sensitivity Effects 0.000 abstract description 7
- 238000000151 deposition Methods 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 229910021332 silicide Inorganic materials 0.000 abstract description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910020328 SiSn Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910017875 a-SiN Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、固体撮像素子チップ上に光導電膜を積層して
構威される積層型固体撮像装置に係り，特に画素電極部
構造の改良をはかった積層型固体撮像装置及びその製造
方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a stacked solid-state imaging device constructed by stacking a photoconductive film on a solid-state imaging device chip, and particularly relates to a stacked solid-state imaging device constructed by stacking a photoconductive film on a solid-state imaging device chip. The present invention relates to a stacked solid-state imaging device with an improved electrode structure and a method of manufacturing the same.
（従来の技術）
固体撮像素子チップ上に光導電膜を積層した構造の固体
撮像装置（以下，積層型固体撮像装置という。）は、感
光部の開口面積を広くすることができるため、高感度で
低スミアという優れた特徴を有する。このため、この固
体撮像装置は、各種監視用テレビジョンや高品位テレビ
ジョン等のカメラとして有望視されている。この種の固
体撮像装置用の光導電膜としては、現在のところアモル
ファス材料膜が用いられている。例えば．Ｓｅ一Ａｓ−
Ｔｅ膜． ＺｎＳｅ−ＺｎＣｄＴｅ． ａ−Ｓｉ ：
Ｈ膜（水素化非晶質シリコン膜）等である．これらの材
料の中でとくに特性や加工性の良さ、低温形成の可能性
から、ａ−Ｓｉ ： Ｈ膜が本命になりつつある。(Prior art) A solid-state imaging device (hereinafter referred to as a stacked solid-state imaging device), which has a structure in which a photoconductive film is stacked on a solid-state imaging device chip, has a high sensitivity because the aperture area of the photosensitive section can be widened. It has the excellent feature of low smear. Therefore, this solid-state imaging device is seen as promising as a camera for various surveillance televisions, high-definition televisions, and the like. At present, an amorphous material film is used as a photoconductive film for this type of solid-state imaging device. for example. Se-As-
Te film. ZnSe-ZnCdTe. a-Si:
Such as H film (hydrogenated amorphous silicon film). Among these materials, the a-Si:H film is becoming the favorite because of its good properties, workability, and possibility of low-temperature formation.
第３図はこの種の積層型固体撮像装置の従来例の概略構
造を示す断面図であり、図中１０はｐ型シリコン基板，
１１はｐ十層（素子分離領域），１２はｎ＋層（垂直Ｃ
ＯＤチャネル）、ｌ３はｎ＋十層（蓄積ダイオード）
． １５ａ， １５ｂは転送ゲート電極、１６は第１絶
縁層，１７は画素電極配線、１８は第２絶縁層、２０は
画素電極、２１は光導電膜，２２は透明電極を示してい
る。FIG. 3 is a cross-sectional view showing the schematic structure of a conventional example of this type of stacked solid-state imaging device, in which 10 is a p-type silicon substrate,
11 is a p-layer (element isolation region), 12 is an n+ layer (vertical C
OD channel), l3 is n+10 layer (storage diode)
．． 15a and 15b are transfer gate electrodes, 16 is a first insulating layer, 17 is a pixel electrode wiring, 18 is a second insulating layer, 20 is a pixel electrode, 21 is a photoconductive film, and 22 is a transparent electrode.
ここで、画素電極２０および光導電膜２ｌは、第４図に
示す様に形成される．
まず、第４図（ａ）に示す様に、第２絶縁層ｌ８上に電
極材料２０’を堆積した後、 この上にレジスト３２を
形成する。次いで，第４図（ｂ）に示す様にレジスト３
２をマスクに電極材料２０’ をエッチングして画素電
極２０を形成し、その後同図（ｃ）に示す様にレジスト
３２を除去する．その後，第４図（ｄ）に示す様に、全
面に光導電膜２１を堆積する．ところで，この様な光導
電膜を用いる固体撮像装置では、固体走査部表面の凹凸
が光導電膜の膜貿に大きな影響を与え、画像欠陥が増加
するという問題がある．画像欠陥は、光導電膜堆積時の
基板表面形状、特に画素電極端部の段差形状により，光
導電膜の異常成長が起こり光導電膜の耐圧が低下するこ
とで発生し，再生画像上では白色の点キズとして現われ
る。このため、この画素電極電極端部の形状と光導電膜
の異常戒長の関係から異常成長の無い電極端部の形状が
提案されている〔特願昭５９−９６５８２号（特開昭６
０−２４１２６０号公報参照）〕．この先行技術によれ
ば、画素電極の膜厚と電極端部の傾斜角の積がＩＯ−・
ｄｅｇｒｅｅ以下であれば良いとしている。さらに、こ
の電極形状を実現する方法として、画素電極材料を堆積
した後、さらにこの材料の上に画素電極材料よりもエッ
チング速度の速いモリブデンのような材料をキャップ膜
として蒸着する．その後、レジストを形成、バターニン
グし、フォトエッチング法等の等方性エッチングにより
積層された前記両材料をエッチング処理し、その後レジ
スト及びキャップ膜を除去することによって電極端部が
傾斜して形威される．しかし、この様な従来の画素電極
自身に傾斜をつける構造では、等方性のエッチングを用
いる必要がある．等方性エッチングを用いた場合パター
ンの加工精度が低く、画素毎に分離して形成される画素
電極の面積がバラつき、感度ムラが発生するという問題
があった。Here, the pixel electrode 20 and the photoconductive film 2l are formed as shown in FIG. First, as shown in FIG. 4(a), an electrode material 20' is deposited on the second insulating layer l8, and then a resist 32 is formed thereon. Next, as shown in FIG. 4(b), the resist 3
2 as a mask, the electrode material 20' is etched to form the pixel electrode 20, and then the resist 32 is removed as shown in FIG. 2C. Thereafter, as shown in FIG. 4(d), a photoconductive film 21 is deposited on the entire surface. However, in a solid-state imaging device using such a photoconductive film, there is a problem in that unevenness on the surface of the solid-state scanning section has a large effect on the film thickness of the photoconductive film, resulting in an increase in image defects. Image defects occur when the photoconductive film is abnormally grown due to the substrate surface shape during deposition of the photoconductive film, especially the step shape at the end of the pixel electrode, and the withstand voltage of the photoconductive film decreases, resulting in a white color on the reproduced image. It appears as a dotted scratch. Therefore, from the relationship between the shape of the end of the pixel electrode and the abnormal length of the photoconductive film, a shape of the end of the electrode without abnormal growth has been proposed [Japanese Patent Application No. 59-96582 (Japanese Unexamined Patent Publication No. 1986-1991)
0-241260)]. According to this prior art, the product of the film thickness of the pixel electrode and the inclination angle of the electrode end is IO-
It is said that it is sufficient as long as it is below the degree. Furthermore, as a method to achieve this electrode shape, after the pixel electrode material is deposited, a material such as molybdenum, which has a faster etching rate than the pixel electrode material, is deposited on top of this material as a cap film. After that, a resist is formed and buttered, and both of the laminated materials are etched by isotropic etching such as photo etching, and then the resist and cap film are removed, so that the end of the electrode is tilted and shaped. It will be done. However, in such a conventional structure in which the pixel electrode itself is inclined, it is necessary to use isotropic etching. When isotropic etching is used, there is a problem in that pattern processing accuracy is low, and the areas of pixel electrodes formed separately for each pixel vary, resulting in uneven sensitivity.
（発明が解決しようとする課題）
この様に従来の積層型固体撮像装置においては、光導電
膜堆積前の基板表面に画素電極端部による段差が生じ、
この段差形状に起因して画像欠陥が発生するという問題
があった。この問題を解決するために画素電極端部自身
に傾斜をつける事が前述のように提案，されているが，
この方法でも、電極形成後の画素電極の面積がバラッキ
、感度ムラが発生するという問題がある。(Problem to be Solved by the Invention) As described above, in the conventional stacked solid-state imaging device, a step occurs on the substrate surface before the photoconductive film is deposited due to the end portion of the pixel electrode.
There is a problem in that image defects occur due to this stepped shape. In order to solve this problem, it has been proposed and proposed to slope the end of the pixel electrode itself, as described above.
Even with this method, there is a problem that the area of the pixel electrode after electrode formation varies and sensitivity unevenness occurs.
本発明は、上記事情を考慮してなされたもので、その目
的とするところは、感度ムラを発生させること無く画素
電極端部に実効的に傾斜を形成し，画像欠陥の少ない積
層型固体撮像装置及びその製造方法を提供することにあ
る。The present invention has been made in consideration of the above circumstances, and its purpose is to effectively form an inclination at the end of the pixel electrode without causing sensitivity unevenness, and to form a stacked solid-state imaging device with fewer image defects. An object of the present invention is to provide a device and a method for manufacturing the same.
（課題を解決するための手段）
本発明の骨子は、積層型固体撮像装置において画素電極
形成前の絶縁層表面の画素電極端部に対応する部分に傾
斜を付けることにより、加工精度の高い異方性エッチン
グ方法を用いて、画素電極端部に実効的に傾斜をつける
事にある。(Means for Solving the Problems) The gist of the present invention is to provide a multilayer solid-state imaging device with high processing accuracy by slanting a portion of the insulating layer surface corresponding to the end of the pixel electrode before forming the pixel electrode. The objective is to effectively slope the end of the pixel electrode by using a directional etching method.
即ち本発明は、半導体基板上に信号電荷蓄積ダイオード
及び信号電荷読み出し部が配列され、絶縁層を設け、且
つ最上部に信号電荷積ダイオードに電気的に接続された
画素電極を形成された固体撮像素子チップと、このチッ
プ上に積層された光導電膜とを備えた積層型固体撮像装
置において、絶縁層表面の画素電極端部に対応する部分
に該電極端部に傾斜が付くように溝を形或する。その後
、画素電極材料を堆積、形或するようにしたものである
．
また、本発明は、上記構造の積層型固体撮像装置の製造
方法において、前記画素電極形成前に、画素電極端部に
対応する部分に傾斜が付くように，前記絶縁体層表面に
溝を形成した後、画素電極材料を堆積する。次いで，レ
ジストを形成、パターニングし、加工精度の高い異方性
エッチングを用いるようにした方法である。That is, the present invention provides a solid-state image sensor in which a signal charge accumulation diode and a signal charge readout section are arranged on a semiconductor substrate, an insulating layer is provided, and a pixel electrode electrically connected to the signal charge accumulation diode is formed on the top. In a stacked solid-state imaging device comprising an element chip and a photoconductive film stacked on the chip, a groove is formed in a portion of the surface of the insulating layer corresponding to the end of the pixel electrode so that the end of the electrode is inclined. take shape Thereafter, pixel electrode material is deposited and shaped. The present invention also provides a method for manufacturing a stacked solid-state imaging device having the above structure, in which, before forming the pixel electrode, a groove is formed on the surface of the insulating layer so that a portion corresponding to the end of the pixel electrode is inclined. After that, pixel electrode material is deposited. Next, a resist is formed and patterned, and anisotropic etching with high processing accuracy is used.
（作用）
本発明によれば、画素電極材料を堆積前に画素電極端部
に対応する部分に傾斜が付くように，前記絶縁層表面に
溝を形或することにより、加工精度の高い異方性エッチ
ングを用いても実効的に画素電極端部に傾斜を付ける事
が可能となる．従って、感度ムラを発生させる事無く，
画素電極端部の段差に起因する画像欠陥を低減すること
が可能となる。(Function) According to the present invention, by forming grooves on the surface of the insulating layer so that the portion corresponding to the end of the pixel electrode is inclined before depositing the pixel electrode material, anisotropic processing with high processing accuracy can be achieved. It is also possible to effectively create a slope at the end of the pixel electrode by using static etching. Therefore, without causing sensitivity unevenness,
It becomes possible to reduce image defects caused by steps at the ends of the pixel electrodes.
（実施例）
以下，本発明の一実施例を第１図及び第２図（ａ）〜（
ｉ）によって説明する。(Example) An example of the present invention will be described below with reference to FIGS. 1 and 2 (a) to (a).
This is explained by i).
第ｌ図は、本発明の実施例に関わる積層型固体撮像装置
の概略構造を示す断面図であり信号電荷読み出し部にイ
ンターライン転送（：， （：， Ｉ） （Ｉｎｔａｒ
−１ｉｎｅ Ｔｒａｎｓｆｅｒ ＣＣＤ）を用いた例で
ある。FIG. 1 is a cross-sectional view showing the schematic structure of a stacked solid-state imaging device according to an embodiment of the present invention, in which interline transfer (:, (:, I) (Intar
-1ine Transfer CCD).
これを製造工程に沿って説明すれば、まずｐ型シリコン
半導体基板１０の表面にｐ十層（素子分離領域）１１．
ｎ十層（垂直ＣＯＤチャネル）１２およびｎ＋＋層（蓄
積ダイオード）１３を形成する。さらに、この基板１０
上にＣＶＤ．熱酸化等によるＳｕｎ２からなるゲート絶
縁膜を介して垂直ＣＯＤの転送ゲート電極１５ａ， １
５ｂを多結晶シリコンにより形成する。To explain this along the manufacturing process, first, a p layer (element isolation region) 11.
An n10 layer (vertical COD channel) 12 and an n++ layer (storage diode) 13 are formed. Furthermore, this substrate 10
CVD on top. Vertical COD transfer gate electrodes 15a, 1 are formed via a gate insulating film made of Sun2 by thermal oxidation or the like.
5b is formed of polycrystalline silicon.
次いで、この上にＳｉｎ，の第１絶縁層１６をＣＶＤな
どで堆積した後に、該絶縁層１６に画素電極配線１７と
蓄積ダイオード１３との電気的導通のためのコンタクト
ホールを形或する。そして、画素電極配線ｌ７をポリサ
イドやシリサイドなどで形成した後に、表面形状を平坦
化する目的でＢＰＳＧ （ｂｏｒｏｐｈｏｓｐｈｏ−ｓ
ｉｌｉｅａｔｅ ｇｌａｓｓ）或いはＰ Ｓ Ｇ （ｐ
ｈｏｓｐｈｏｓｉｌｉｃａｔｅｇｌａｓｓ）から成る第
２絶縁層１８をＣＶＤ法などで形成する。続いて、この
絶縁層１８に画素電極２０の隙間に対応する位置に溝１
９を形威した後、画素コンタクトホールを形或する．た
だし、画素コンタクトと溝の形成の順番は前後しても構
わない．次に，画素電極２０を形成、最後に光導電膜２
１と透明電極２２を形或する．
次に、本発明による第２絶縁層形或以降の工程について
，第２図に示す工程断面図を用いて説明する。第２図は
、第１図における画素電極間の溝１９、画素電極２０．
光導電膜２１及び絶縁膜１８を拡大して示す図であり、
その他の部分については省略している。Next, a first insulating layer 16 of Sin is deposited thereon by CVD or the like, and then a contact hole for electrical connection between the pixel electrode wiring 17 and the storage diode 13 is formed in the insulating layer 16. After forming the pixel electrode wiring l7 with polycide, silicide, etc., BPSG (borophospho-s
ilieate glass) or P S G (p
A second insulating layer 18 made of phosphosilicate glass is formed by CVD or the like. Subsequently, a groove 1 is formed in this insulating layer 18 at a position corresponding to the gap between the pixel electrodes 20.
After forming 9, form the pixel contact hole. However, the order of forming the pixel contacts and grooves may be changed. Next, the pixel electrode 20 is formed, and finally the photoconductive film 2
1 and a transparent electrode 22. Next, the process of forming the second insulating layer and subsequent steps according to the present invention will be explained using the process cross-sectional diagram shown in FIG. FIG. 2 shows the groove 19 between the pixel electrodes and the pixel electrode 20 in FIG.
It is a diagram showing an enlarged view of a photoconductive film 21 and an insulating film 18,
Other parts are omitted.
第２図（．）は絶縁層１８及びコンタクトホールを形成
した直後の状態であり、この状態で同図（ｂ）に示す如
くフォトリソグラフィにより画素電極の隙間に対応する
位置が開く様にレジスト３１を形成する．次いで、第２
図（Ｑ）に示す如くレジスト３１をマスクにしてＣＦ，
，Ｏ，の混合ガスを用いたＣＤＥ （Ｃｈｅｍｉａｌ
Ｄｒｙ Ｅｔｃｈｉｎｇ）、または１〜３％程度のＨＦ
のＨＦ４Ｆ溶液を用いたウエットエッチング等の等方性
エッチングを用いて絶縁層１８に溝１９を形成する。こ
こで、等方性エッチングを用いて溝ｌ９を形成すると、
側壁に傾斜を持った溝を形成することが可能となる。そ
の後、第２図（ｄ）に示す如くレジスト３１を除去する
。FIG. 2(.) shows the state immediately after the insulating layer 18 and contact holes have been formed, and in this state, as shown in FIG. form. Then the second
As shown in Figure (Q), using the resist 31 as a mask, CF,
CDE (Chemical
Dry Etching) or 1-3% HF
Grooves 19 are formed in the insulating layer 18 using isotropic etching such as wet etching using an HF4F solution. Here, if the groove l9 is formed using isotropic etching,
It becomes possible to form grooves with an inclination on the side walls. Thereafter, the resist 31 is removed as shown in FIG. 2(d).
次いで、第２図（ｅ）に示す如＜．Ｔｉ等の電極材料２
０′をスパッタ法により１０００〜３０００人程度堆積
して同図（ｆ）に示す如くフォトリソグラフィにより画
素領域のパターンにレジスト３ｌを形成する。Next, as shown in FIG. 2(e). Electrode material 2 such as Ti
Approximately 1,000 to 3,000 layers of 0' are deposited by sputtering, and a resist 3l is formed in the pattern of the pixel area by photolithography as shown in FIG. 3(f).
続いて，第２図（ｇ）に示す如＜ ＣＦ４． Ｈ２及び
０２混合ガスを用いた異方性エッチングである、たとえ
ばＲ Ｉ Ｅ （Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈ
ｉｎｇ）により、レジスト３１をマスクにＴｉ電極材料
２０′ を選択エッチングし画素電極２０を形成する。Next, as shown in FIG. 2(g), < CF4. For example, RIE (Reactive Ion Etch) is an anisotropic etching using H2 and 02 mixed gas.
ing), the Ti electrode material 20' is selectively etched using the resist 31 as a mask to form the pixel electrode 20.
ここで異方性エッチングである．ＲＩＥを用いてエッチ
ングすると、エッチングはレジストパターンに沿って垂
直方向に進行するため，平面的な寸法に対する加工精度
は高くなる．その後、第２図（ｈ）に示す如くレジスト
３１を除去する。ここで，画素電極２０の端部の形状を
見ると、下地の絶縁層１８に形威した溝１９のため、実
効的に傾斜が形成されている．次いで、第２図（ｉ）に
示す如く、光導電膜２１として例えば水素化非品質シリ
コン膜をプラズマＣＶＤ法により、全面に２ｔ！Ｍ程度
堆積し、最後に光導電膜２１上の感光部全面に透明電極
２２として例えばＩ Ｔｏ （Ｉｎｄｉｕｍ Ｔｉｎ
Ｏｘｉｄｅ）をスバッタ法により形成することで、前記
第１図の構造の積層型固体撮像装置を得る。This is anisotropic etching. When etching is performed using RIE, the etching progresses in the vertical direction along the resist pattern, resulting in high processing accuracy for planar dimensions. Thereafter, the resist 31 is removed as shown in FIG. 2(h). Here, looking at the shape of the end of the pixel electrode 20, we see that it is effectively sloped due to the groove 19 formed in the underlying insulating layer 18. Next, as shown in FIG. 2(i), as a photoconductive film 21, for example, a hydrogenated non-quality silicon film is coated over the entire surface by plasma CVD. Finally, for example, I To (Indium Tin) is deposited as a transparent electrode 22 on the entire surface of the photosensitive area on the photoconductive film 21.
The layered solid-state imaging device having the structure shown in FIG. 1 is obtained by forming the layered solid-state imaging device using a sputtering method.
上述の実施例では、画素コンタクトホールと溝１９の形
成を別に行う例を用いたが、同一工程で形成すれば、従
来構造と同様の工程数で制作することが可能である．
なお、本発明は上述した実施例に限定されるものではな
い。実施例ではＣＣＤ撮像素子を用いたが、ＭＯＳ型や
ＢＢＤ型撮像素子チップを用いて、これにａ−Ｓｉ ：
Ｈ光導電膜を積層する場合でも，本発明を適用する事
が出来る．さらに，ａ−Ｓｔ：Ｈ光導電膜の製法も、実
施例のものに限らず，例えば光励超成膜形成法により形
威しても良い．また、光導電膜はａ−Ｓｉ ： Ｈが主
体であれば良く、ａ−ＳｉＣ ：Ｈ， ａ−ＳｉＧｅ
： Ｈ， ａ−ＳｉＮ ： Ｈ， ａ−ＳｉＳｎ ：
Ｈ、さらにこれらのＦを含有するものを用いた場合にも
本発明は有効である。In the above embodiment, an example was used in which the pixel contact hole and the groove 19 were formed separately, but if they were formed in the same process, the structure could be manufactured using the same number of steps as the conventional structure. Note that the present invention is not limited to the embodiments described above. In the example, a CCD image sensor was used, but a MOS type or BBD type image sensor chip was also used, and a-Si:
The present invention can also be applied to the case where H photoconductive films are laminated. Furthermore, the method for producing the a-St:H photoconductive film is not limited to that of the embodiments, and may also be formed by, for example, a photoexcited super-deposition method. Further, the photoconductive film may be mainly composed of a-Si:H, a-SiC:H, a-SiGe
: H, a-SiN : H, a-SiSn :
The present invention is also effective when using a material containing H and further F.
さらに、実施例では、ＣＣＵをＮチャネルとして説明し
たが、ｐチャネル型ＣＣＤでも本発明に適用できること
は勿論である。Further, in the embodiments, the CCU is described as an N-channel CCU, but it goes without saying that a p-channel type CCD can also be applied to the present invention.
その他、本発明の要旨を逸脱しない範囲で、種々変形し
て実施することができる。In addition, various modifications can be made without departing from the gist of the present invention.
以上詳述したように本発明によれば、加工精度の高い異
方性エッチングを用いても画素電極端部に実効的に傾斜
を確保することが可能であるため、感度のムラを発生さ
せることなく表面段差に起因する画像欠陥を大幅に低減
できる。As detailed above, according to the present invention, it is possible to effectively ensure an inclination at the end of the pixel electrode even when using anisotropic etching with high processing precision, so that unevenness in sensitivity can be prevented. Image defects caused by surface steps can be significantly reduced.
第１図は本発明の実施例に係る積層型固体撮像装置の概
略構造を示す断面図、第２図（ａ）〜（ｉ）は第ｌ図の
装置の製造工程の主要部を示す断面図、第３図は従来の
積層型固体撮像装置の概略構造を示す断面図、第４図は
第３図に示す従来の装置の製造工程を示す断面図である
。
１０・・・ｐ型シリコン半導体基板、
１１・・・ｐ十層（素子分離領域）、
１２・・・ｎ十層（垂直ＣＣＤチャネル）、１３・・・
ｎ千十層（蓄積ダイオード）、１５ａ， １５ｂ−垂直
ＣＣＤ転送ゲート電極、１６・・・第１絶縁層、
ｌ７・・・画素電極配線、１８・・・第２絶縁層、
ｌ９・・・画素電極の間隙に位置する溝、２０・・・画
素電極、 ２ｌ・・・光導電膜、２２・・・透
明電極、 ３１． ３２・・・レジスト．（８
７３３）代理人 弁理士 猪 股 祥 晃（ほか１名）
第１図
第
３
図FIG. 1 is a cross-sectional view showing a schematic structure of a stacked solid-state imaging device according to an embodiment of the present invention, and FIGS. 2(a) to (i) are cross-sectional views showing main parts of the manufacturing process of the device shown in FIG. , FIG. 3 is a sectional view showing a schematic structure of a conventional stacked solid-state imaging device, and FIG. 4 is a sectional view showing a manufacturing process of the conventional device shown in FIG. 10...p-type silicon semiconductor substrate, 11...p ten layers (element isolation region), 12...n ten layers (vertical CCD channel), 13...
n110 layers (storage diode), 15a, 15b - vertical CCD transfer gate electrode, 16... first insulating layer,
l7... Pixel electrode wiring, 18... Second insulating layer, l9... Groove located in the gap between pixel electrodes, 20... Pixel electrode, 2l... Photoconductive film, 22... Transparent electrode, 31. 32...Resist. (8
733) Agent Patent attorney Yoshiaki Inomata (and 1 other person) Figure 1 Figure 3
Claims (3)
が配列された半導体基板上に絶縁層および前記絶縁層上
に画素毎に分離し、かつ信号電荷蓄積ダイオードに電気
的に接続された画素電極を設けてなる固体撮像素子チッ
プと、このチップ上に積層された光導電膜とを備えた積
層型固体撮像装置において、前記絶縁層の前記画素電極
間の間隙に対応する位置に、側面に傾斜を持つ溝が形成
されたことを特徴とする積層型固体撮像装置。(1) An insulating layer is provided on a semiconductor substrate on which a signal charge storage diode and a signal charge readout section are arranged, and a pixel electrode is provided on the insulating layer, separated for each pixel and electrically connected to the signal charge storage diode. In a stacked solid-state imaging device comprising a solid-state imaging device chip and a photoconductive film stacked on the chip, the insulating layer has a slope on its side surface at a position corresponding to the gap between the pixel electrodes. A stacked solid-state imaging device characterized in that a groove is formed.
いて形成し、前記画素電極を異方性エッチングを用いて
形成することを特徴とする請求項１記載の積層型固体撮
像装置の製造方法。(2) The stacked solid-state imaging device according to claim 1, wherein the groove formed in the insulating layer is formed using isotropic etching, and the pixel electrode is formed using anisotropic etching. Production method.
オードと前記画素電極とを接続させるためのコンタクト
ホールとを同時に形成すことを特徴とする請求項１記載
の積層型固体撮像装置の製造方法。(3) Manufacturing the stacked solid-state imaging device according to claim 1, wherein the groove formed in the insulating layer is simultaneously formed with a contact hole for connecting the signal charge storage diode and the pixel electrode. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1230482A JPH0394468A (en) | 1989-09-07 | 1989-09-07 | Laminated type solid-state image sensing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1230482A JPH0394468A (en) | 1989-09-07 | 1989-09-07 | Laminated type solid-state image sensing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0394468A true JPH0394468A (en) | 1991-04-19 |
Family
ID=16908487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1230482A Pending JPH0394468A (en) | 1989-09-07 | 1989-09-07 | Laminated type solid-state image sensing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0394468A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020173985A1 (en) * | 2019-02-27 | 2020-09-03 | Trinamix Gmbh | Optical sensor and detector for an optical detection |
-
1989
- 1989-09-07 JP JP1230482A patent/JPH0394468A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020173985A1 (en) * | 2019-02-27 | 2020-09-03 | Trinamix Gmbh | Optical sensor and detector for an optical detection |
| US11908956B2 (en) | 2019-02-27 | 2024-02-20 | Trinamix Gmbh | Optical sensor and detector for an optical detection |
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