JPH0389608A - High input impedance amplifier - Google Patents

High input impedance amplifier

Info

Publication number
JPH0389608A
JPH0389608A JP1225828A JP22582889A JPH0389608A JP H0389608 A JPH0389608 A JP H0389608A JP 1225828 A JP1225828 A JP 1225828A JP 22582889 A JP22582889 A JP 22582889A JP H0389608 A JPH0389608 A JP H0389608A
Authority
JP
Japan
Prior art keywords
amplifier
operational amplifier
input
transistor
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1225828A
Other languages
Japanese (ja)
Inventor
Misao Furuya
操 古谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsumi Electric Co Ltd
Original Assignee
Mitsumi Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsumi Electric Co Ltd filed Critical Mitsumi Electric Co Ltd
Priority to JP1225828A priority Critical patent/JPH0389608A/en
Publication of JPH0389608A publication Critical patent/JPH0389608A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize a high input impedance amplifier with less sensitivity variance and signal loss in comparison with a conventional amplifier using an FET by constituting the amplifier, which amplifiers the output signal of a condenser microphone, of only bipolar transistors TRs and a resistor. CONSTITUTION:A bias part 5 essentially consists of an operational amplifier A1, an amplifier A2 (the gain is, for example, one), TRs X1 and X2, and resistors R1 and R2, and amplifiers A1 and A2 form a negative feedback loop. An amplifier 6 consists of an amplifier A3 having the same constitution as the amplifier A2, and a condenser microphone 1 is connected to the connection point between the bias part 5 and the amplifier 6. The feedback loop consists of the operational amplifier A1, the amplifier A2, and the TR X1 and the loop controls to equalize two input voltages of the operational amplifier A1 and the TR X2 and the input of the amplifier A3 are connected so that the input voltage of the operational amplifier A1 is the bias voltage of a signal source 1. In this case, constant current circuits Ic1 and Ic2 of amplifiers A2 and A3 are constituted with minute currents.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高入力インピーダンス増幅器に係り、特に、コ
ンデンサマイクロホンの出力信号を増幅するために必要
な入力容量の小さい高入力インピーダンス増幅器に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high input impedance amplifier, and more particularly to a high input impedance amplifier that requires a small input capacitance to amplify the output signal of a condenser microphone.

〔従来の技術〕[Conventional technology]

現在、コンデンサマイクロホンは多方面に種々の目的で
使用されている。一般に、コンデンサマイクロホンの出
力インピーダンスは10pF〜20pFと小さく、この
ためにマイクロホン機能を持たせるには入力容量の小さ
い高入力インピ−ダンス増幅器にてインピーダンス変換
してやる必要がある。
Currently, condenser microphones are used in many fields for various purposes. Generally, the output impedance of a condenser microphone is as small as 10 pF to 20 pF, and therefore, in order to provide a microphone function, it is necessary to perform impedance conversion using a high input impedance amplifier with a small input capacitance.

第4図は従来の一例の回路図を示す。同図において、コ
ンデンサマイクロホン1(音声信号源1a及び容量素子
16)からの音声信号はFET2a及びダイオード2b
にて構成される高入力インピーダンス増幅器2にて増幅
され、出力端子3より出力される。この場合、FETは
一般に入力インピーダンスが極めて高いため、コンデン
サマイクロホンの増幅器としてよく用いられる。
FIG. 4 shows a circuit diagram of a conventional example. In the figure, an audio signal from a capacitor microphone 1 (audio signal source 1a and capacitive element 16) is transmitted through an FET 2a and a diode 2b.
The signal is amplified by a high input impedance amplifier 2 composed of , and outputted from an output terminal 3 . In this case, since FETs generally have extremely high input impedance, they are often used as amplifiers for condenser microphones.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

FETG、を高入力インピーダンスであるため、コンデ
ンサマイクロホンの増幅器としてよく用いられるが、F
ETは一般にその特性にばらつきが大きく、従って、バ
イアス電流やバイアス電圧のばらつきが大となって感度
のばらつきや信号損失が大きくなる問題点があった。
FETG is often used as an amplifier for condenser microphones due to its high input impedance.
ETs generally have large variations in their characteristics, and therefore have the problem of large variations in bias current and bias voltage, resulting in large variations in sensitivity and signal loss.

本発明は、コンデンサマイクロホンの増幅器に使用した
場合、感度のばらつきや信号損失の少ない高性能の増幅
器を提供することを目的とする。
An object of the present invention is to provide a high-performance amplifier with less variation in sensitivity and less signal loss when used as an amplifier for a condenser microphone.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、第2図に示す如く、任意の電圧を一方の入力
とする演算増幅器AIと、バイポーラトランジスタ及び
抵抗のみで構成されており、微小電流に設定された定電
流源1o+を設けられ、演算増幅器A1の出力にて低電
流領域でかつ定電流特性を利用して動作し、出力電圧を
演算増幅器A1の他方の入力に帰還させる第1の増幅器
A2と、バイポーラトランジスタ及び抵抗のみで構成さ
れており、微小電流に設定された定電流源102を設け
られ、演算増幅器A1の出力にて低電流領域でかつ定電
流特性を利用して動作し、入力端子に信号源1を供給さ
れてこれを増幅して取出す第2の増幅器A3と、演算増
幅器A+の出力端子にベースを共通に接続されており、
演算増幅器AIの出力でオンして第1及び第2の増幅器
A2.A3の夫々の入力電流を流してこれらを夫々動作
させる第1及び第2のトランジスタX+。
As shown in FIG. 2, the present invention is composed of only an operational amplifier AI which receives an arbitrary voltage as one input, a bipolar transistor and a resistor, and is provided with a constant current source 1o+ set to a minute current. The first amplifier A2 operates in a low current region using constant current characteristics at the output of the operational amplifier A1, and is composed only of a bipolar transistor and a resistor, and a first amplifier A2 that feeds back the output voltage to the other input of the operational amplifier A1. The circuit is equipped with a constant current source 102 set to a minute current, operates in the low current region at the output of the operational amplifier A1 and utilizes constant current characteristics, and is supplied with the signal source 1 to the input terminal. The base is commonly connected to the output terminal of the second amplifier A3, which amplifies and takes out the signal, and the operational amplifier A+.
The output of operational amplifier AI turns on and the first and second amplifiers A2 . The first and second transistors X+ conduct the respective input currents of A3 to operate them respectively.

X2とからなる構成とする。The configuration consists of X2.

〔作用〕[Effect]

演算増幅器A+、第1の増幅器A2.第1のトランジス
タX1で構成される帰還ループで演算増幅器へ1の2つ
の入力電圧が等しくなるように制御し、第2のトランジ
スタ×2と第2の増幅器A3の入力との接続によって油
算増幅器A1の入力電圧が信号源1のバイアス電圧とな
るようにする。こ9場合、第2の増幅器A3の定電流回
路を微小%i流に構成しているので、バイポーラトラン
ジスタのみで高入力インピーダンス、小入力容量の増幅
器を構成することができる。バイポーラトランジスタは
FETに比して一般に特性のばらつきが少ないため、F
ETを用いた従来の高入力インピーダンス増幅器に比し
て感度ばらつきがなく、又、信号損失も少なくでき、高
性能の増幅器を得ることができる。
operational amplifier A+, first amplifier A2. The feedback loop composed of the first transistor X1 controls the two input voltages of 1 to the operational amplifier to be equal, and the connection between the second transistor x2 and the input of the second amplifier A3 creates an oil amplifier The input voltage of A1 is made to be the bias voltage of signal source 1. In this case, since the constant current circuit of the second amplifier A3 is configured to have a minute current of %i, it is possible to configure an amplifier with high input impedance and small input capacity using only bipolar transistors. Bipolar transistors generally have less variation in characteristics than FETs, so F
Compared to conventional high input impedance amplifiers using ET, there is no variation in sensitivity, signal loss can be reduced, and a high-performance amplifier can be obtained.

〔実施例〕〔Example〕

第1図は本発明の一実施例の回路図、第2図はその概略
回路図を示し、各図中、同一構成部分には同一番号、同
一符号を付す。同図中、5はバイアス部で、主として演
算増幅器AI、増幅器A2(利得は例えば1)、トラン
ジスタX+ 、X2 。
FIG. 1 shows a circuit diagram of an embodiment of the present invention, and FIG. 2 shows a schematic circuit diagram thereof. In each figure, the same components are denoted by the same numbers and symbols. In the figure, 5 is a bias section, which mainly includes an operational amplifier AI, an amplifier A2 (gain is 1, for example), and transistors X+ and X2.

抵抗R+ 、R2にて構成されており、増幅器At。It consists of resistors R+ and R2, and an amplifier At.

A2は負帰還ループを形成している。6は増幅部で、増
幅器A2と全く同じ構成の増幅器A3にて構成されてい
る。コンデンサマイクロホン1はバイアス部5と増幅部
6との接続点に接続されている。
A2 forms a negative feedback loop. Reference numeral 6 denotes an amplifier section, which is composed of an amplifier A3 having exactly the same configuration as the amplifier A2. A condenser microphone 1 is connected to a connection point between a bias section 5 and an amplification section 6.

いま、増幅器A+ 、A2は負帰還ループを構成してお
り、増幅器A+のトランジスタQ+への入力電圧をvl
、トランジスタQ2への入力端子をvlとすると、この
負帰還ループは電圧V+とV2  (=V< )とが等
しくなるようにIIJIする。
Now, amplifiers A+ and A2 constitute a negative feedback loop, and the input voltage to transistor Q+ of amplifier A+ is
, the input terminal to the transistor Q2 is vl, this negative feedback loop performs IIJI so that the voltages V+ and V2 (=V<) are equal.

即ち、増幅器A1の出力によりトランジスタ×1がオン
されてそ増幅器A2のトランジスタQ3のベース電流i
esが流れ、トランジスタQ3と対で構成されているト
ランジスタQ4のベース電圧(増幅器A2の出力電圧)
V4  (−V2 )が増幅器A1の入力電圧■1と等
しくなるように1lil[される。これにより、増幅器
A+ 、A2はバランス状態となり、V+ =V2 =
V3 =V4 となる。この場合、定電流回路rotの
定電流1 cc、を微小電流にしておけば、トランジス
タQ3のベース電流ie3は1001)A〜数nAのオ
ーダの低電流となる。
That is, transistor x1 is turned on by the output of amplifier A1, and the base current i of transistor Q3 of amplifier A2 is
es flows, and the base voltage of transistor Q4, which is configured as a pair with transistor Q3 (output voltage of amplifier A2)
1liil[ is applied so that V4 (-V2) is equal to the input voltage 1 of the amplifier A1. As a result, amplifiers A+ and A2 are in a balanced state, and V+ = V2 =
V3=V4. In this case, if the constant current 1 cc of the constant current circuit rot is made a minute current, the base current ie3 of the transistor Q3 will be a low current on the order of 1001)A to several nA.

又、トランジスタ×1のオンと共にトランジスタ×2も
オンとなり、増幅器A3のトランジスタQ5のベース電
流issが流れる。この場合、増幅器A2とA3、トラ
ンジスタ×1と×2、抵抗R1とR2を夫々同一にして
おけば、増幅器A3のトランジスタQ5のベース電圧V
)は増幅器A2のトランジスタQ3のベース電圧■3と
同一となり、出力端子3の電圧をv6とすると、V+”
=Vs”=Vaとなる。増幅器A2の定電流回路Io+
 と同様に、増幅器A3の定電流回路I02の定電流I
CC2を微小電流にしておけば、トランジスタQsのベ
ース電流iasも増幅器A2のトランジスタQ3のベー
ス電流is3と同様に10(IIA〜数nAのオーダの
低電流となる。このように、増幅器A3の入力端に流れ
る電流は低電流領域であり、かつ、トランジスタの定電
流特性を利用して流れているので、増幅器A3の入力イ
ンピーダンスを1000MΩ以上に確保するのは容易で
あり、入力容量を数1)F以下に設定できる。即ち、F
ETを用いず、バイポーラトランジスタのみで高入力イ
ンピーダンス小入力容量の増幅器を構成することができ
、トランジスタQ5のベースに入来したコンデンサマイ
クロホン1の音声信号を増幅して同相で出力端子3に出
力できる。
Further, when transistor x1 is turned on, transistor x2 is also turned on, and the base current iss of transistor Q5 of amplifier A3 flows. In this case, if amplifiers A2 and A3, transistors x1 and x2, and resistors R1 and R2 are made the same, the base voltage of transistor Q5 of amplifier A3
) is the same as the base voltage ■3 of the transistor Q3 of the amplifier A2, and if the voltage at the output terminal 3 is v6, then V+''
=Vs”=Va. Constant current circuit Io+ of amplifier A2
Similarly, the constant current I of the constant current circuit I02 of the amplifier A3
If CC2 is set to a minute current, the base current ias of the transistor Qs will be a low current on the order of 10 (IIA to several nA), similar to the base current is3 of the transistor Q3 of the amplifier A2. The current flowing at the end is in the low current region and is flowing using the constant current characteristics of the transistor, so it is easy to ensure the input impedance of amplifier A3 to be 1000 MΩ or more, and the input capacitance is Can be set below F. That is, F
It is possible to configure an amplifier with high input impedance and small input capacity using only bipolar transistors without using ET, and it is possible to amplify the audio signal of the condenser microphone 1 that enters the base of the transistor Q5 and output it to the output terminal 3 in the same phase. .

本発明回路は、増幅器A+ 、A2における負帰還ルー
プで増幅器A1の入出力をバランスさせてV+ −Vz
 =V3 =V4 を得、増幅N A 2と全く同じ構
成の増幅器A3で電圧■1と等しくなるようにコンデン
サマイクロホ〉・1のバイアス電圧Vsを設定する。し
かも、前述のように定電流回路1ozを微小電流にする
ことによってバイポーラトランジスタのみで、又、IC
にした場合にコンデンサ等の外付は素子を全く用いずに
、高入力インピーダンス、小入力容量の増幅器を構成す
るものである。このように、バイポーラトランジスタ及
び抵抗のみで増幅器を構成しているので、FETを用い
たものに比して感度ばらつきがなく、又、信号損失も少
ない。この場合、もし増幅器A2を用いず、増幅器A1
及びA3のみを用いてトランジスタQ6のベースから負
帰還をかけるようなループを構成すると、音声信号が負
帰還されてしまうので入力インピーダンスを高くできず
、このように構成することは不可能である。
The circuit of the present invention balances the input and output of amplifier A1 with a negative feedback loop in amplifiers A+ and A2, so that V+ -Vz
=V3 =V4, and set the bias voltage Vs of the capacitor microho>.1 so that it is equal to the voltage 1 in the amplifier A3, which has exactly the same configuration as the amplifier N A 2. Moreover, as mentioned above, by making the 1oz constant current circuit a minute current, it is possible to use only bipolar transistors or ICs.
In this case, an amplifier with high input impedance and small input capacitance is constructed without using any external elements such as capacitors. In this way, since the amplifier is configured with only bipolar transistors and resistors, there is no variation in sensitivity and there is less signal loss compared to an amplifier using FETs. In this case, if amplifier A2 is not used and amplifier A1
If a loop is constructed in which negative feedback is applied from the base of transistor Q6 using only A3 and A3, the input impedance cannot be made high because the audio signal will be negatively fed back, and such a construction is impossible.

第3図本発明の他の実施例の要部の回路図を示し、同図
中、第1図、第2図と同一構成部分には同一符号を付す
。第3図において、増幅器A2のトランジスタQ3のベ
ースにトランジスタQ3’ によるバイアス電流1a3
0を加え、増幅器A3’のトランジスタQ5のベースに
トランジスタQs’ によるバイアス電流1B5111
を加えるようにしてもよい。この場合、動作及び効果は
第1図及び第2図に示す実施例と同様であるので、その
説明を省略する。
FIG. 3 shows a circuit diagram of a main part of another embodiment of the present invention, in which the same components as in FIGS. 1 and 2 are given the same reference numerals. In FIG. 3, a bias current 1a3 is applied to the base of transistor Q3 of amplifier A2 by transistor Q3'.
0 is added, and the bias current 1B5111 by the transistor Qs' is applied to the base of the transistor Q5 of the amplifier A3'.
You may also add In this case, the operation and effects are the same as those of the embodiment shown in FIGS. 1 and 2, so the explanation thereof will be omitted.

なお、上記各実施例とも図示のトランジスタの極性を逆
にしても同等の特性が得られることは勿論である。
It goes without saying that in each of the above embodiments, the same characteristics can be obtained even if the polarities of the illustrated transistors are reversed.

又、増幅器A2の利得は上記実施例のように1に限定さ
れるものではなく、1より大に設定してもよい。
Further, the gain of the amplifier A2 is not limited to 1 as in the above embodiment, but may be set to be greater than 1.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、バイポーラトランジスタ及び抵抗のみ
で構成できるので、FETを用いた従来の高入力インピ
ーダンス増幅器に比して感度ばらつきや信号損失の少な
い高入力インピーダンス増幅器を実現でき、しかも」ン
デンサを使用していないのでtC化し易い。
According to the present invention, since it can be configured with only bipolar transistors and resistors, it is possible to realize a high input impedance amplifier with less sensitivity variation and signal loss than conventional high input impedance amplifiers using FETs, and also uses a capacitor. Since it is not done, it is easy to convert to tC.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の回路図、第2図はその概略
回路図、第3図は本発明の他の実施例の要部の回路図、
第4図は従来の一例の回路図である。 1・・・コンデンサマイクロホン、3・・・出力端子、
5・・・バイアス部、6・・・増幅部、VCC・・・電
源、A1・・・演算増幅器、A2.A3・・・増幅器、
Q1〜Qs 、X+ 、X2−トランジスタ、lot。 1o  2 ・・・定電流源。
FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a schematic circuit diagram thereof, and FIG. 3 is a circuit diagram of a main part of another embodiment of the present invention.
FIG. 4 is a circuit diagram of a conventional example. 1... Condenser microphone, 3... Output terminal,
5... Bias section, 6... Amplification section, VCC... Power supply, A1... Operational amplifier, A2. A3...Amplifier,
Q1~Qs, X+, X2- transistors, lot. 1o 2 ... constant current source.

Claims (1)

【特許請求の範囲】 任意の電圧を一方の入力とする演算増幅器と、バイポー
ラトランジスタ及び抵抗のみで構成されており、微小電
流に設定された定電流源を設けられ、該演算増幅器の出
力にて低電流領域でかつ定電流特性を利用して動作し、
出力電圧を該演算増幅器の他方の入力に帰還させる第1
の増幅器と、バイポーラトランジスタ及び抵抗のみで構
成されており、微小電流に設定された定電流源を設けら
れ、上記演算増幅器の出力にて低電流領域でかつ定電流
特性を利用して動作し、入力端子に信号源を供給されて
これを増幅して取出す第2の増幅器と、 上記演算増幅器の出力端子にベースを共通に接続されて
おり、上記演算増幅器の出力でオンして上記第1及び第
2の増幅器の夫々の入力電流を流してこれらを夫々動作
させる第1及び第2のトランジスタとよりなり、 前記演算増幅器、第1の増幅器、第1のトランジスタで
構成される帰還ループで前記演算増幅器の2つの入力電
圧が等しくなるように制御し、前記第2のトランジスタ
と前記第2の増幅器の入力との接続によつて前記演算増
幅器の入力電圧が前記信号源のバイアス電圧となるよう
に構成したことを特徴とする高入力インピーダンス増幅
器。
[Claims] It is composed only of an operational amplifier that receives an arbitrary voltage as one input, a bipolar transistor, and a resistor, and is provided with a constant current source set to a minute current, and the output of the operational amplifier is Operates in the low current region and utilizes constant current characteristics,
a first feeding the output voltage back to the other input of the operational amplifier;
It is composed only of an amplifier, a bipolar transistor, and a resistor, and is equipped with a constant current source set to a minute current, and operates in a low current region using the constant current characteristics at the output of the operational amplifier, A second amplifier is supplied with a signal source to its input terminal and amplifies and extracts the signal, and a base is commonly connected to the output terminal of the operational amplifier, and is turned on by the output of the operational amplifier to output the signal from the first and second amplifiers. A feedback loop consisting of the operational amplifier, the first amplifier, and the first transistor operates the operational amplifier. Controlling two input voltages of the amplifier to be equal, and connecting the second transistor to the input of the second amplifier so that the input voltage of the operational amplifier becomes the bias voltage of the signal source. A high input impedance amplifier characterized by the following configuration.
JP1225828A 1989-08-31 1989-08-31 High input impedance amplifier Pending JPH0389608A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1225828A JPH0389608A (en) 1989-08-31 1989-08-31 High input impedance amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1225828A JPH0389608A (en) 1989-08-31 1989-08-31 High input impedance amplifier

Publications (1)

Publication Number Publication Date
JPH0389608A true JPH0389608A (en) 1991-04-15

Family

ID=16835443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1225828A Pending JPH0389608A (en) 1989-08-31 1989-08-31 High input impedance amplifier

Country Status (1)

Country Link
JP (1) JPH0389608A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05167358A (en) * 1991-12-12 1993-07-02 Nec Corp Amplifier circuit for ecm

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05167358A (en) * 1991-12-12 1993-07-02 Nec Corp Amplifier circuit for ecm

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