JPH03874Y2 - - Google Patents

Description

[Detailed description of the invention] "Industrial application field" This invention is a converter that makes it possible to control the output at a constant level without switching over a wide range of input voltage changes, such as from 100V to 200V AC. There is something about clamp control circuits.

"Prior Art" The applicant of this case has already proposed a circuit as shown in Fig. 3 as a clamp control circuit (Japanese Patent Application No. 61-
No. 183180). That is, the input power supply 11 includes the primary winding 13 of the transformer 12 and the MOS as the main switching element.
The secondary winding 15 of the transformer 12 includes a rectifier diode 16, a commutating diode 17, an inductor 18 and a capacitor 1.
9 through a smooth wave circuit consisting of an output terminal 20,
21, and these output terminals 20 and 21 are connected to an insulating photocoupler 23 and a shunt regulator 2.
4. The first FET 14 via the detection amplifier circuit 25
A so-called forward type converter is configured.

In the above-mentioned forward type converter,
A series circuit of a diode 26, a second FET 27 serving as an auxiliary switching element, and a capacitor 28 is coupled between the drain and source of the first FET 14, and an auxiliary winding having the same number of turns as the primary winding 13 is connected to the transformer 12. Winding the tertiary winding 29 as
One end of the next winding 29 is connected to the diode 26 and the second end.
The other end is connected to the connection point of the 2FET 27 and the positive side of the input power supply 11.

The transformer 12 is further provided with a quaternary winding 30, one end of which is coupled to the primary winding 13, and the other end coupled to the primary winding 13 via a resistor 31.
It is coupled to the gate of 2FET27. This first
Between the source and gate of 2FET27 is the 3rd FET32.
Combine the source and drain of this
A resistor 33 is connected between the source and drain of the 3FET 32. Further, a diode 3 is coupled between the drain and source of the second FET 27.

The detection amplifier circuit 25 consists of a power supply IC 35 commercially available as MB3759, a resistor, a diode, and a capacitor for slowing the rise of the first FET 14 and the second and third FETs 27 and 32 when they are on, and quickening their fall when they are off. The time constant circuit 36,3
7, gate circuits 38, 39, etc. are provided, one gate circuit 38 is coupled to the gate of the first FET 14 via a resistor 40, and the other gate circuit 39 is coupled to the second gate circuit 39 via an insulating pulse transformer 41. , No.
It is coupled to the gates of 3FETs 27 and 32. 4
2 is a DC power supply.

"The problem that the invention attempts to solve" The system shown in Figure 3 is the 1st FET 14, the capacitor 28
N-channel as the second FET 27 for charging and discharging.
MOSFET was used, but due to the following reasons, the 3rd FET32 and 4th FET3 were used as auxiliary switching elements.
9. Pulse transformer 41 etc. were required. In other words, the first FET 14 is surely turned on before the first FET 14 is turned on.
If the 2FET 27 is not cut off, the clamp capacitor 28 will connect the 2nd FET 27, the tertiary winding 29,
is discharged by a short circuit through the primary winding 13 and the first FET 14, resulting in operational failure and
There were problems such as destruction of the 2FETs 14, 27, etc. and a decrease in efficiency. Therefore, the turn-on of the first FET 14 due to the output of the power supply IC 35 is delayed appropriately by the time constant circuit 36, etc., and when the output of the IC 35 is output, the turn-on of the first FET 14 is
The second FET27 is rapidly moved to the first FET14 by 9 etc.
It was necessary to shut it off before turning it on. In addition, it is naturally necessary to disassemble the potential using a pulse transformer 41, etc., but the second and third FETs 27 and 32
There were some problems, such as the need for careful attention to the fluctuation of the source potential for smooth control.

"Means for solving the problem" This invention was made to solve the above-mentioned problem, and the input power supply is connected to the series circuit of the primary winding of the transformer and the first FET. , an output terminal is coupled to the secondary winding of the transformer via a rectifying wave circuit, and a conduction angle of the first FET is determined by an output from a detection amplifier circuit coupled to the output terminal via a power supply IC. In the forward type converter configured to control, a diode, a
A series circuit of a second FET of the P channel and a capacitor is coupled to one end of the primary winding of the transformer;
A tertiary winding having the same number of turns as the primary winding is connected between the connection point of the diode and the second FET, and a tertiary winding of the transformer is connected between the gate and source of the second FET. The gate voltage supply circuit is combined with the N-channel third FET,
A gate voltage supply circuit is connected between the gate and source of this third FET and the power supply IC.

"Operation" Since the source of the 1st FET and the source of the 2nd FET of the P channel are connected to the same point, there is no fluctuation in the source of the 2nd FET, and not only does the conventional pulse transformer and 4th FET become unnecessary. , stable control is performed.

“Embodiment” An embodiment of the present invention will be described below based on the drawings.

In FIG. 1, 11 is a DC input power source, and this input power source 11 is coupled to a series circuit of a primary winding 13 of a transformer 12 and a MOS type first FET 14 as a main switching element. The next winding 15 is coupled to output terminals 20 and 21 via a smooth wave circuit consisting of a rectifier diode 16, a commutation diode 17, an inductor 18, and a capacitor 19. It is coupled to the gate of the first FET 14 via a regulator 24 and a detection amplification circuit 25.

In the above-mentioned forward type converter,
A series circuit of a diode 26, a capacitor 28, and a P-channel MOS type second FET 27 as an auxiliary switching element is coupled between the drain and source of the first FET 14, and the transformer 12 has the same number of turns as the primary winding 13. A tertiary winding 29 is wound as an auxiliary winding, and one end of this tertiary winding 29 is connected to the connection point between the diode 26 and the capacitor 28.
The other end is coupled to the positive side of the input power source 11.

The transformer 12 is provided with a quaternary winding 30, and a gate voltage supply circuit consisting of the quaternary winding 30, a capacitor 43, and a resistor 44 is coupled between the gate and source of the second FET 27. Also, this
The source and drain of an N-channel MOS type third FET 32 are connected between the source and gate of the 2FET 27, and a resistor 33 is connected between the gate and source of this third FET 32. A gate voltage supply circuit consisting of a Zener diode 45 or a capacitor 46 is coupled between the output terminals of the .

The detection amplifier circuit 25 consists of a power supply IC 35 commercially available as MB3759, a resistor, a diode, and a capacitor for slowing the rise of the first FET 14 and the second and third FETs 27 and 32 when they are on, and quickening their fall when they are off. A time constant circuit 36 consisting of a gate circuit 38 consisting of a transistor, etc.
This gate circuit 38 is coupled to the gate of the first FET 14. The transformer 12 is further provided with a 5th winding 47, and a DC power source consisting of the 5th winding 47, diodes 48, 49, a resistor 50, and a capacitor 51 is coupled to the IC 35 and the transistor.

In the above circuit, the parts surrounded by chain lines are related to the present invention. The operation will now be explained with reference to FIG. In this figure 2, a is
The output voltage of IC35, 6 is the gate of the first FET14.
The source-to-source voltage Vgs,c is the gate-to-source voltage of the third FET32.
The source voltage Vgs, d is the drain-source voltage Vds of the third FET 32 and the gate-source voltage Vds of the second FET 27.
The source voltage Vgs, e is the drain voltage of the second FET27.
The source-to-source voltage Vds is shown. First, at T ₁ , when the IC 35 outputs as shown in a, the time constant circuit 36 operates as in the conventional case, causing the output to change from T ₁ .
The gate-source voltage Vgs of the first FET 14 is supplied as shown in b after a delay of T ₂ , and the first FET 14 is turned on at T ₂ . Then at T ₁ o'clock
When IC35 outputs, Zener diode 45
or through the capacitor 46 as shown in c.
A gate-source voltage Vgs is supplied to the 3FET 32. At this time, the drain-source voltage Vds of the third FET 32 becomes d, which causes the
The gate-source voltage Vgs of the 2FET 27 is controlled. Furthermore, it is obvious that the on/off state of the second FET 27 is controlled by the gate-source voltage Vgs as shown in e. As a result, the 1st FET1
2nd FET 27 is definitely activated before turn-on of 4.
is turned off and the above-mentioned failure does not occur.

By the way, when the IC35 is off, it is desirable that the second FET27 turns on a little later than _T3 , when the first FET14 turns off.
3, there is a slight delay between T ₃ and T ₄ , as shown in c.
The gate-source voltage Vgs of the 3FET 32 disappears, and as a result, the second FET 27 is also turned on with a delay.

``Effects of the invention'' Since the invention is constructed as described above, the number of parts is smaller than that of the conventional method, and control is performed within the same potential, making it possible to use a thick film IC for the entire control part, which allows operation. It is also stable and highly effective in practical use.

[Brief explanation of drawings]

Fig. 1 is an electric circuit diagram showing an embodiment of the clamp control circuit of the converter according to the present invention, Fig. 2 is an operating waveform diagram of the same as above, and Fig. 3 is a circuit diagram of a forward converter that has been previously filed by the present applicant. . 12...Transformer, 13...Primary winding, 14...
1st FET, 15... Secondary winding, 18... Inducer, 20, 21... Output terminal, 23... Insulating photocoupler, 24... Shun regulator, 25
...Detection amplifier circuit, 27...Second FET, 29...
Tertiary winding, 30... quaternary winding, 32...th
3FET, 35...Power IC, 36...Time constant circuit, 38...Gate circuit, 47...5th winding.

Claims (1)

[Scope of utility model registration request] The input power source is connected to a series circuit of the primary winding of the transformer and the first FET, and the output terminal is coupled to the secondary winding of the transformer via a rectified wave circuit, and the In the forward type converter, the conduction angle of the first FET is controlled by the output from the detection amplifier circuit via the power supply IC, and a series circuit including a diode, a P-channel second FET, and a capacitor is connected across the first FET. A tertiary winding having the same number of turns as the primary winding is coupled between one end of the primary winding of the transformer and a connection point of the diode and the second FET,
A gate voltage supply circuit formed by the quaternary winding of the transformer is connected between the gate and source of the 2FET, and an N-channel 3rd FET is connected between the gate and source of the 2FET.
1. A clamp control circuit for a converter, characterized in that a resistor is inserted between the gate and source of a 3rd FET, and a gate voltage supply circuit is coupled between the gate of the 3rd FET and the power supply IC.