JPH0385920A - Variable frequency division circuit - Google Patents

Abstract

PURPOSE:To frequency-divide a clock signal at a high frequency at a high speed by outputting a signal whose level is changed from a signal conversion circuit in the inside of a signal output stage and supplying the signal to an expansion section directly so as to decrease the number of gates in a feedback signal generating path, thereby quickening the circuit operating speed. CONSTITUTION:The same signal as a signal outputted from a reset output terminal theta of a master slave flip-flop 21 provided to a 1st stage of, e.g. a frequency division section 10 is outputted from a sub reset output terminal in the same timing while being level increased. The signal is directly fed to the expansion section 41 of an upper-stage DCFL(Direct Coupled FET Logic) circuit 2. Thus, a frequency division signal is delivered from a lower stage DCFL circuit 1 to the upper stage DCFL circuit 2. Then the number of gates of the feedback signal generating section is decreased to quicken the operation of the entire circuit and the clock signal with a high frequency is frequency-divided at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a variable frequency divider circuit that uses Schottky FETs to achieve lower power consumption and higher speed.

(Prior art) In a GaAs circuit, DCF L (Dltect
A type of circuit called "CoupledPET Logic" has attracted attention for its low power consumption, and is being actively researched.

FIG. 5 is a diagram showing an example of an inverter circuit constructed using the CFL method.

The circuit shown in this figure is composed of a plurality of FETs 10I having a Schottky gate structure. The high level V11 becomes a potential clamped by the Schottky forward voltage VP, as shown in the saturation characteristic diagram of FIG.

Therefore, even if a power supply voltage of VF or higher (for example, 0.7μ or higher), which is approximately equal to the Schottky voltage, is applied, there is no effect on the operation and it is not very effective in improving the operation speed.
Since it can be operated with a power supply voltage of about V, it is eagerly awaited as a logic circuit with low power consumption.

Incidentally, such a CFL circuit is rarely used to configure a system by itself, and is often used together with a circuit (silicon element circuit) configured using other silicon elements.

However, silicon element circuits such as C-MOS and ECL require a power supply voltage of about 3 to 5 mm, so when such silicon element circuits and DCFL circuits coexist, the voltage shown in FIG. As shown, a silicon element circuit 105
, the power supply voltage is directly supplied from the power supply 103, and the DC
For the FL circuit 1(]2, a resistor 104 is inserted between the DCFL circuit 102 and the power supply 103, and the power supply voltage is often lowered and supplied by this resistor 104.

However, such a power supply method is not preferable from the viewpoint of reducing power consumption because the power consumed by the resistor 104 increases the amount of power consumed by the entire system.

Therefore, as a method to solve such problems, the present applicant proposed a logic circuit that can reduce the power consumption of the entire system even when a DCFL circuit and a silicon element circuit are used together. Disclosed.

The operating principle of this logic circuit will be explained below with reference to FIGS. 8 to 13.

As shown in FIG. 8, this logic circuit includes a silicon element circuit 107 connected to a positive terminal 106a and a negative terminal 106b of a power source 106, and a DCFL series circuit connected to a positive terminal 106a and a negative terminal 106b of the power source 106. 10
8, and the silicon element circuit 107 and the DCFL series circuit 1 are connected by the power supply voltage output from the power supply 106.
08 directly.

The DCFL series circuit 108 has a positive terminal 109a connected to the positive terminal 06a of the power source 106, an upper DCFL circuit 09, a negative terminal 110b connected to the negative terminal 106b of the power source 106, and an in terminal 110.
a is connected to the negative terminal 109b of the upper DCFL circuit 109; and the power supply 106.
The current adjustment circuit 1]1 is connected to the positive terminal 106a and the negative terminal 106b of the circuit, and absorbs the difference in current consumption between the upper DCFL circuit 109 and the lower DCFL circuit 110 and supplies a stable intermediate potential. The upper side of the power supply voltage obtained by the power supply 106 drives the upper stage DCFL circuit 109, and the lower side of the power supply voltage drives the second stage DCFL circuit 110. In addition, in parallel with this operation, the current adjustment circuit 111
By absorbing the difference in current consumption between the FL circuit 109 and the lower DCFL circuit 110, the upper DCFL circuit 109 and the lower DCFL circuit 110
The operation of the FL circuit 110 is stabilized.

Upper DCFL circuit 109 and lower DCFL circuit 110
are circuits each composed of a Schottky gate, and due to the characteristics peculiar to the Schottky gate, it becomes a constant current circuit regardless of its operating state.

In other words, if the upper stage DCFL circuit 109 and the F stage DCFL circuit 1.10 are each constituted by an inverter made up of a plurality of Schottky FETs 112a to u12n and 113a to 113n as shown in FIG. Spiral Schottky FET
112a to 112n can be considered as a constant current load.

When the input level of the first-stage Schottky FET 113a is set to a low level, this Schottky FET 113
FET a becomes cut off, and current no longer flows between its source and drain, and its drain potential rises. Correspondingly, the gate potential of Schottky FET 113b at the next stage rises, making it conductive.

As a result, the gate of Schottky FET 113b
The forward voltage of the diode is approximately 0.7 V between the sources.
and Schottky FET112
The current 1a flowing through a is the Schottky FET 113b
Correspondingly, a current 1b flows between the source and the drain of this Schottky FET 113b.

That is, in the upper stage DCFL circuit 109 and the lower stage DCFL circuit 110, a constant current always flows through each Schottky FET 112a to 112n serving as a load, regardless of the operating state of the circuit.

In addition, the value of the current flowing through the upper DCFL circuit 109 and the lower DCFL circuit 110 is the current value ra of all the Schottky FETs 112a to 112n serving as loads.
It is the value obtained by adding ~In.

Therefore, the current adjustment circuit 111 shown in FIG. 8 only needs to adjust the difference between the current value IU of the upper stage DCFL circuit 109 and the current value 10 of the lower stage DCFL circuit 110 in a steady state.

For example, when current value IU>current value ID, current "IU-10" flows to ground through two diodes 114 provided in current adjustment circuit 111 as shown in FIG. A voltage "2VF" corresponding to the voltage drop is supplied to the lower stage DCFL circuit 110 as a stabilized voltage. Further, in this case, the diode 115 connected in the opposite direction has the role of a capacitor, and acts to absorb transient current and stabilize the voltage.

Further, in the case of current 10<current ID, as shown in FIG.
is generated, and a depletion type Schottky F connected as a source follower based on this reference potential "2VF@" is generated.
The potential "2VP-VGS" is obtained by subtracting the gate-source voltage "vGS" from the reference potential "2VF" by ET118.
is generated and supplied to the lower DCFL circuit 110. Also in this case, diode 1 connected in the opposite direction
19 has the role of a capacitor, and acts to absorb transient current and stabilize the voltage.

However, in this case, as the relational expression shown below stands out,
The gate widths of the depletion type Schottky FETs 112a to 112n, which generate the current IU and the current ID, and the gate width of the depletion type Schottky FET 118 are determined.

WQ-ΣWU-ΣWD However, WQ: Depression type Schottky FET1
18 gate width ΣWu: Gate width that is the sum of all the gate widths of the depletion type Schottky FETs 112a to 112n that create the current ID ΣWD: Added all the gate widths of the depletion type Schottky FETs 112a to 112n that create the current IU By satisfying the gate width and such conditions, the gate-source voltage VGS of the depletion type Schottky FET 118 becomes zero, and the stabilizing potential becomes 2VF.

In addition, since the Schottky FET 118 is a FET with the same structure as the depletion type Schottky FETs 112a to 112n that conduct current IU or current 10, even if the threshold value varies, Even if the value changes, the gate-source voltage VGS can be maintained at a constant value, and thereby a stable potential can always be provided to the lower DCFL circuit 110.

In this way, in the circuit shown in FIG. 8, the potential to the lower stage DCFL circuit 110 can be kept almost constant even if the power supply voltage VDD changes, so by placing important circuits on the lower stage side, , this can be operated stably.

Furthermore, in the circuit shown in FIG. 8, since there is a potential difference between the upper stage DCFL circuit 109 and the lower stage DCFL circuit 110, the upper stage DCFL circuit 109 and the F stage DCFL circuit
When transmitting and receiving signals between the L circuits 110, the level of the signal must be shifted.

Therefore, these 10 upper-stage DCFL circuits and lower-stage DCFL circuits
The FL circuit 110 includes an upper stage DCFL from the f-stage DCFL circuits 1 and 09, a level up circuit necessary for transmitting signals to the circuit 110, and a lower stage DC from the upper stage DCFL circuit 110.
A level down circuit necessary for transmitting signals to FL circuit 109 is provided.

FIG. 12 is a diagram showing an example of such a level-up circuit.

The level up circuit 120 shown in this figure has a source in the lower stage D.
Schottky FET1 in the CFL circuit 110
13a to 113n], 23, and the drain is connected to the upper DCF.
Schottky FETs 11 and 2 a in the L circuit 109
~112n, and a switching FET 124 whose gate and source are connected together, and level shift diodes 125 and 126 which connect the source of this switching FET 124 and the drain of the switching FET 123. .

Then, a signal is output from the signal output stage of the F-stage DCFL circuit 110, and if this is input to the gate of the switching FET 123, the switching FET 12
3 turns on/off, and this on/off content is passed through the diode 1.26.125 to the switching FET.
124, and this switching FET 124 is turned on/off. Then, the signal obtained by this on/off operation is input to the signal input stage of the upper stage DCFL circuit 109.

Further, as the level down circuit, for example, a circuit as shown in FIG. 13 is used.

The level down circuit 121 shown in this figure is a Schottky FETI 1 whose drain is inside the upper DCFL circuit 109.
A switching FET 127 whose source is connected to the drains of Schottky FETs 113a to 113n in the lower DCFL circuit 110 and a switching FET 128 whose gate and source are connected, E
T 1.28 drain and the switching FET 12
Level shift diode 1 connected to the source of 7
29.130.

Then, a signal is output from the upper stage DCFL and the No. 13 output stage of the circuit 109, and if this is input to the gate of the switching FET 127, the switching FET
127 turns on/off, and this on/off content is transmitted via the diodes 12Q and 130 to the switching FE.
The signal is transmitted to T128, and this switching FET 128 is turned on/off. The signal obtained by this on/off operation is input to the signal input stage of the lower DCFL circuit 10.

In this logic circuit, the upper DCFL circuit 109 and the lower DCFL circuit 110 are connected in series between the positive terminal 106a and the negative terminal 106b of the power supply 106, thereby making the voltage lower than the voltage of the power supply 106. Voltage is upper D
Since the voltage is applied to the CFL circuit 109 and the lower DCFL circuit 110, the power consumption can be reduced by not using a resistor for dropping the power supply voltage, and this reduces the power consumption of the entire logic circuit. The amount can be reduced.

Next, a conventional variable frequency divider circuit proposed based on the above-mentioned operating principle will be described.

FIG. 14 is a circuit diagram showing an example of a variable frequency divider circuit to which the above-described operating principle is applied.

The variable frequency divider circuit shown in this figure includes a double-stage DCFL circuit 135, an upper-stage DCFL circuit 136, and a level-up circuit 137.
and a level down circuit 138, and the signal input to the mode terminal 139 and the switch terminal 140 are provided.
The frequency division ratio is 1/94.1 depending on the signal input to the
/65.1/128.1/129, the clock signal input to the signal input terminal 141 is frequency-divided and output from the output terminal 142.

The lower DCFL circuit 135 includes a bias section 143 that generates a bias voltage, and two complementary clock signals from a clock signal input from a signal input terminal 141 using the bias voltage obtained by this bias section 143 as a threshold. an inverter 145 that inverts the signal (feedback signal) fed back via the level down circuit 138; and an inverter 145 that inverts the signal (feedback signal) fed back via the level down circuit 138;
and a variable frequency dividing section 146 that divides the clock signal output from the clock signal by a frequency division ratio of 1/4 or a frequency division ratio of 115,
When the feedback signal is not input through the level down circuit 138, the clock signal input through the signal input terminal 141 is divided by a frequency division ratio of 1/4, and the feedback signal is input. Sometimes, the signal input terminal 14
The clock signal input through 1 is divided by a division ratio of 115, and the signal obtained by this division operation (divided signal)
is supplied to the upper stage DCFL circuit 136 via the level up circuit 137.

The upper DCFL circuit 136 is connected to the level up circuit 137.
an inverter 147 that inverts and amplifies the frequency-divided signal input through the inverter 147, an extension section 148 that divides the output of the inverter 147 by 1716 or 1/32, and this extension section 1.
an output section 149 that outputs the frequency-divided signal obtained by the frequency division operation of 48 to the outside, and a switch section 1 that transmits the signal input through the switch terminal 140 to the extension section 148.
50, a feedback section 151 that generates a feedback signal based on each output of the extension section 148, and a mode section 15 that guides the signal input via the mode terminal 139 to the feedback section 151.
2.

Then, according to the signal input to the switch terminal 140, the frequency-divided signal input through the level-up circuit 137 is divided by a frequency division ratio of 1/16 or 1/32 and output. Output from terminal 142. At this time, if the signal input to the mode terminal 139 is "Lo", the frequency division signal input via the level up circuit 137 is divided at a repetition period of 1/16 or 1/32. Generates a feedback signal and sends it to the level down circuit 1
It is fed back to the lower stage DCFL circuit 135 via 38.

In this way, in this variable frequency divider circuit, the mode terminal 1
39 and the signal input to the switch terminal 140, the clock signal input to the signal input terminal 141 is set to 1/64.1/65.1/128.1/1.
The frequency is divided by one of 29 frequency division ratios and outputted from the output terminal 142.

(Problems to be Solved by the Invention) By the way, when the above-described variable frequency divider circuit is used as a synthesizer for a mobile radio or the like, it must be operated at about IGHz.

However, the conventional variable frequency divider circuit uses an inverter 147.153 or a NOR gate 154.15 in the feedback signal generation part.
Since there are a large number of gates such as 5, etc., there is a problem that it is difficult to operate at high speed and the entire circuit cannot be operated at high speed.

In order to solve this problem, a variable frequency divider circuit shown in FIG. 15 has been proposed. In this figure, parts corresponding to those in FIG. 14 are given the same reference numerals.

The variable frequency divider circuit shown in this figure is different from the circuit shown in FIG. By inputting this to the level up circuit 137, the inverter 147 for signal inversion is removed from between the level up circuit 137 and the extension section 148, and the set output of 15 flip-flops provided in the front stage of the extension section 148 is The signal output from the terminal Q is directly input to the level down circuit 138, and gates such as the inverters 153 and 145 are removed from between the flip-flop 159 and the frequency divider 146. In addition, in response to this, the connection of each of the flip flops 159 to 163 that connect the expansion part 148 to the tank bottom and the configuration of the return part 151 have been changed.

Thereby, this variable frequency divider circuit can be operated at higher speed than the variable frequency divider circuit shown in FIG.

However, even in this variable frequency divider circuit, since the level up circuit 137 is present in the feedback signal forming part,
Furthermore, there is a problem in that it is not possible to variably divide a clock signal of a higher frequency.

In view of the above circumstances, it is an object of the present invention to provide a variable frequency divider circuit that can divide a high frequency clock signal at high speed, thereby significantly improving the performance when integrated into an IC. There is.

[Structure of the invention]

(Means for solving the problem) In order to achieve the above object, the variable frequency divider circuit according to the present invention is constituted by a plurality of frequency divider circuits, and is inputted at a frequency division ratio according to the content of the input feedback signal. a variable frequency dividing section ε that divides the frequency of the input clock signal; an extension section that divides the signal output from the variable frequency dividing section at a frequency division ratio according to the input control signal to create an output signal; A DCFL vertical stack type variable frequency divider comprising a feedback section that controls the frequency division ratio of the variable frequency divider by creating a feedback signal at a repetition period according to the control signal from the frequency division operation signal of the extension section. The circuit is characterized in that a signal conversion circuit is provided inside the signal output stage in the variable frequency dividing section, and the signal output from this signal conversion circuit is directly supplied to the expansion section.

(Function) In the above configuration, by outputting a level-up or level-down signal from the signal conversion circuit provided inside the signal output stage and directly supplying it to the extension section, To increase the circuit operating speed by reducing the number of gates.

(Embodiment) FIG. 1 is a circuit diagram showing an embodiment of a variable frequency divider circuit according to the present invention.

The variable frequency divider circuit shown in this figure includes a lower DCFL circuit 1ε, an upper DCFL circuit 2ε, and a DCFL circuit 2 to lower DCFL circuit 2.
It is equipped with a level down circuit 3 that transmits a signal to the FL circuit 1, and sets a frequency division ratio of 1/1 according to the signal input to the mode terminal 4 and the signal input to the switch terminal 5.
64.1/65.1/128.1. /1.29, the clock signal input to the signal input terminal 6 is divided and outputted from the output terminal 7.

The T'ff1DCFL circuit 1 includes a bias section 8ε, a clock signal generation section 9, and a frequency division section 10, and is inputted from the signal input terminal 6 in accordance with the signal inputted via the level down circuit 3. The clock signal is frequency-divided by a frequency division ratio of 1/4 or 115, and the resulting frequency-divided signal is supplied to the upper stage DCFL circuit 2.

The bias section 8 includes an inverter 11 having an input terminal and an output terminal connected to each other, and a resistor 12 that serves as an output transmission path of the inverter 11. and supplies it to the clock signal generation section 9.

The clock signal generation section 9 includes inverters 13 and 14 that compare and amplify the clock signal input from the signal input terminal 6 while being biased by the bias voltage output from the bias section 8; inverters 15 and 16 that amplify the output of said inverter 15 and 16 to generate one clock signal; Inverter 1 amplifies the output of 18 and generates the other clock signal
9.20, and supplies each generated clock signal to the frequency dividing section 10.

The frequency dividing section 10 includes three master/slave type flip-flops 21 to 23 connected in cascade. The frequency of the output clock signal is divided into 1/4, and the signal obtained by this frequency division operation (divided signal) is supplied to the upper DCFL circuit 2, and a feedback signal is output from the upper DCFL circuit 2. At this time, the clock signal output from the clock signal generating section 9 in a compensatory manner is frequency-divided by 115, and the signal (frequency-divided signal) obtained by this frequency-dividing operation is supplied to the upper stage DCFL circuit 2.

The first stage mask slave type flip-flop 21 is the second stage mask slave type flip-flop 21.
As shown in the figure, there are two mask sections made up of four NOR gates 25 to 28, a slave section 34 made up of four NOR gates 30 to 33, and this slave section 3.
4, and a NOR gate 35 that takes the logical sum of the signals output from rIA1tFB, and when one clock signal is input to the master clock terminal CK, the 2
The mask unit 2 captures and holds the signals input to the two input terminals DI and D2, and when the other clock signal is input to the slave clock terminal CK.
9 and outputs it from the set output terminal Q1 and the reset output terminal Q while holding it. At this time, the NOR gate 35 extracts a signal from the middle stage of the slave section 34, raises the level of the same signal as the signal output from the reset output terminal Q, and outputs it from the sub-reset output terminal QU at the same timing.

In this case, the NOR gate 35 consists of two enhancement type FETs 36.3 connected in parallel as shown in FIG.
7, a depletion type FET 38 whose gate and source are connected, and each of the enhancement type FETs 36
．． It is equipped with diodes 39 and 40 that level shift the common output of 37 and supply it to the depletion type FET 38 and transmit it to the upper stage DCFL circuit 2, and the signal obtained by ORing the input signals. is leveled up and transmitted to the upper DCFL circuit 2.

In addition, the second stage mask slave type flip-flop 2
2 is a mask section composed of four Noah gates;
It is equipped with a slave section composed of four NOR gates, and when one clock signal is input to the master clock terminal CK, the signal input to the two input terminals D is captured and held, and the slave section When the other clock signal is input to the clock terminal CK, the signal held by the mask section is taken in and outputted from the set output terminal Q1 and the reset output terminal Q while holding this signal.

In addition, the final stage mask slave type flip-flop 2
3 is a mask section composed of four Noah gates,
It is equipped with a slave section composed of four NOR gates, and an operation mode switching section that switches the operation mode according to the signal input to the mode terminal M.
When the signal supplied to the mask clock terminal CK is "L", that is, when the feedback signal is supplied, the mask clock terminal CK
When one clock signal is input to the slave clock terminal CK, the signal input to the two input terminals D is captured and held, and when the other clock signal is input to the slave clock terminal CK, the mask is input to the slave clock terminal CK. The signal held by the unit is captured and outputted from the set output terminal Q1 and the reset output terminal Q while holding the signal. Also,
When the signal supplied to the mode terminal M is "H", that is, when the feedback signal is not supplied, the signal "L" is output from the set output terminal Q, and the signal "L" is output from the reset output terminal Q. Outputs “H”.

Further, the upper stage DCFL circuit 2 includes an extension section 41, a switch section 42, an output section 43, a feedback section 44, and a mode section 45. The frequency-divided signal output from the DCFL circuit 1 is divided by a frequency division ratio of 1/16 or 1/32 and outputted from an output terminal 7. Also at this time, mode terminal 4
If the signal input to the circuit is "L", a feedback signal is generated at a repeating period of 1/16 or 1/32 when dividing the frequency of the frequency-divided signal, and this signal is sent through the level-down circuit 3. It is fed back to the lower stage DCFL circuit 1.

The switch section 42 includes inverters 46 and 47,
A signal input via the switch terminal 5 is amplified and supplied to the extension section 41 .

The extension section 41 includes edge trigger type flip-flops 48 to 52 connected in cascade, and when the signal supplied from the switch section 42 is H'', the mask slave type flip-flops of the second stage DCFL circuit 1 are activated. The frequency-divided signal output from the flip-flop 21 is divided by a frequency division ratio of 1716 and supplied to the output section 43, and when the signal supplied from the switch section 42 is L'', the frequency-divided signal is output from the mask slave type flip-flop. The frequency divided signal output from 21 is 1
The frequency is divided by a frequency division ratio of 732 and supplied to the output section 43.

The output section 43 includes inverters 53 and 54, takes in the frequency-divided signal output from the expansion section 41, amplifies it, and outputs it to the outside.

The mode section 45 also includes inverters 55 and 56, which amplify the signal input via the mode terminal 4 and supply the amplified signal to the feedback section 44.

The return section 44 is a Nantes gate 57.58ε, a Noah gate 5
9, and when the signal supplied from the mode section 45 is "L", a feedback signal is generated at a repetition period of 1/16 or 1/32 based on each output of the expansion section 41. is generated and supplied to the level down circuit 3.

As shown in FIG. 4, the level down circuit 3 has two enhancement type FETs 60 and 61 connected in series, and the gate and source thereof are connected, and the connection point (common connection point) is the drain of the enhancement type FET 60. a depletion type FET 62 whose drain is connected to the positive terminal of the power supply, and a depletion type FET 63 whose drain is connected to the positive terminal of the power supply and whose gate is connected to the common connection point.
, a depletion type FET 64 whose gate and source are connected and whose connection point is grounded, and a level shift type FET 64 connected in series between the drain of this depletion type FET 64 and the source of the depletion type FET 63. It is provided with diodes 65 and 66, performs the logical product of the input signals, lowers the level of the signal obtained thereby, and transmits it to the dividing section 1 ( ) of the lower stage DCFL circuit 1 .

As described above, in this embodiment, the mask slave type flip-flop 21 provided at the first stage of the frequency dividing section 10
The same signal as that output from the reset output terminal Q of the upper 1DcFL is outputted from the sub-reset output terminal Q1.1 at the same timing and at a higher level.
Since the power is supplied directly to the extension section 41 of the circuit 2,
It is possible to transmit the frequency-divided signal from the r-stage DCFL circuit 1 side to the upper-stage DCFL circuit 2 side without installing a special level-up circuit between the frequency dividing section 10 and the expansion section 41.
This makes it possible to reduce the number of sheets in the feedback signal generation section and speed up the operation of the entire circuit.

〔Effect of the invention〕

As explained above, according to the present invention, a high frequency clock signal can be divided at high speed, and thereby K
The performance when converted to C can be significantly improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the variable frequency divider circuit according to the present invention, FIG. 2 is a circuit showing details of the first stage mask slave type flip-flop shown in FIG.
A circuit showing the details of the level-up Noah gate shown in the figure,
FIG. 4 is a detailed circuit diagram of the level down circuit shown in FIG. A schematic diagram showing an example of characteristics, Fig. 7 is a silicon element circuit and D
A block diagram showing an example of a logic circuit combined with a CFL circuit, FIG. 8 is a block diagram showing an example of a logic circuit of the DCFL method that has already been proposed, and FIG.
A schematic diagram for explaining the operation of the FL[11 path, FIG. 10 is a schematic diagram for explaining the operation of the current adjustment circuit shown in FIG. 8, and FIG. 11 is a schematic diagram for explaining the operation of the current adjustment circuit shown in FIG. 8. 12 is a circuit diagram showing an example of a level up circuit provided in the DCFL circuit of FIG. 8, and FIG. 13 is a schematic diagram for explaining the level up circuit provided in the DCFL circuit of FIG. 8. 11114 is a circuit diagram showing an example of a conventionally known variable frequency divider circuit; FIG. 15 is a circuit diagram showing another example of a conventionally known variable frequency divider circuit. It is a diagram. 1...Lower stage DCFL circuit 2...Upper stage DCFL circuit 3...Level down circuit 10...Variable frequency dividing section (frequency dividing section) 21... Frequency dividing circuit, signal output stage (mask slave type flip-flop)22.23・
...Frequency divider circuit (master ◆ slave type flip prozzo) 25~28.30~33...DCFL Noah gate 29
...Flip-flop circuit (mask section) 34...Flip-flop circuit (slave section) 35...Level conversion circuit (NOR gate) 36.37...Enhancement type Schottky ET 38...Depression type Schottky FET...
・Extension part 44...Return part

Claims (3)

[Claims] (1) A variable frequency divider that divides the input clock signal with a division ratio according to the content of the input feedback signal, which is composed of a plurality of frequency divider circuits, and a variable frequency divider that divides the input clock signal at a division ratio according to the contents of the input feedback signal, and an extension section that divides the signal output from the variable frequency division section at a frequency ratio to create an output signal; and a feedback signal that creates a feedback signal at a repetition period according to the control signal from the frequency division operation signal of the extension section. a feedback section that controls the frequency division ratio of the variable frequency division section, and a DCFL vertical stack type variable frequency division circuit comprising: a signal level conversion circuit provided inside a signal output stage in the variable frequency division section; . A variable frequency dividing circuit, characterized in that the signal output from the signal level conversion circuit is directly supplied to the extension section. (2) The signal output stage includes a master-slave type flip-flop circuit composed of eight DCFL NOR gates, and a level conversion circuit that generates a signal whose level is increased or decreased from the signal inside this flip-flop circuit. The variable frequency divider circuit according to claim 1, further comprising: (3) The variable level conversion circuit according to claim 2, wherein the level conversion circuit includes a switching circuit in which a plurality of enhancement type Schottky FETs are connected in parallel or in series, and a depletion type Schottky FET serving as a load of this switching circuit. Frequency divider circuit.