JPH0383463A - Superimposing device - Google Patents

Abstract

PURPOSE:To clearly display a second title picture even when the second title picture is superimposed on a first title picture by providing plural divided unit memory areas, deciding it for each unit picture signal according to a prescribed condition whether the signal is written into the correspondent unit memory area or not, superimposing the stored picture signal to a video signal and outputting the signal. CONSTITUTION:When a write deciding means 28 does not output a write designating signal, a data processing circuit 27 does nothing concerning character data for the characters and moves to processing for the data for the next one character. Accordingly, in the unit area of a memory 18 corresponding to this character, the first picture signal is held as it is. As a result, the character excepting for a space is written into the memory 18. In the other areas, the first title picture or graphic picture written into the memory 18 in a first write mode as it is. Thus, the graphic picture is removed from the background of the character and the clearly displayed picture can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a superimposing device, and particularly to a camera-integrated VTR (Video TapeRe-c).
A superimposing device 1 used in video equipment such as a video camera, etc., and superimposing information from the outside onto a video signal.
Regarding this.

[Prior Art] In video integrated VTRs and the like, a superimposing device is used to superimpose other information such as a title on a captured image. FIG. 4 is a block diagram showing a typical example of a conventional superimposing device of this type.

Referring to FIG. 4, a conventional superimposing device 40
is an A/R converter that receives a luminance signal (hereinafter referred to as Y signal) such as a video signal captured by a video camera or a reproduced video signal of a VTR from the terminal 12, and converts it into digital serial data by binarizing it based on the signal level. A D (analog/digital) converter 14 is connected to the A/D converter 14 and a terminal 42, and synchronizes with a clock signal supplied from the terminal 42 to mutually convert serial data and, for example, 8-bit parallel data. shift register 16 for converting
and a timing generator 2 connected to terminals 42, 44, and 46 for generating signals indicating the operation timing of each element included in this superimposing device 40.
0, shift register 16 and timing generator 2
0 and a memory 18 connected to the shift register 16, and a color synthesis system for outputting RGB color-specific component signals for displaying titles in color according to color information specified by a controller or the like (not shown). a circuit 32, a display circuit 38 for mixing each RGB component signal and a superimposed video signal input from a terminal 34 and outputting the mixture to an output terminal 36; a serial l1024 that receives character data (font data) for displaying characters in a dot pattern from;
A data processing circuit 26 is connected to the serial number 1024 and processes input character data and rearranges it on the memory 18. A data processing circuit 26 is connected to the data processing circuit 26 and the memory 18, and processes the input character data and rearranges it on the memory 18. It also includes a shift register 30 for converting into bit parallel data and writing it to a predetermined location in the memory 18.

The memory 18 stores the parallel data output from the shift register 16 and the shift register 30 at addresses determined by the address signal from the timing generator 20 and the address signal from the shift register 30, respectively, and This is for outputting the stored contents of the address determined by the signal to the shift register 16.

The color synthesis circuit 32 operates in response to a signal read from the memory 18 and converted into serial data by the shift register 16.

Among the signals generated by the timing generator 20, there is a write control signal WE for controlling the timing of writing data into the memory 18, and a write control signal WE for controlling the timing of successive output of data from the memory 18. control signal OE.

The display circuit 38 includes, for example, a matrix circuit that synthesizes a title Y signal and a color difference signal from component signals, and a blanking signal that indicates the timing to switch the title side Y signal and color signal with the superimposed video. and a switching circuit for switching between a title side signal and a video side signal at high speed in response to a blanking signal. None of these are shown.

Referring to FIG. 4, a conventional superimposing device 40
The operation of is described. This superimpose device 40
has three modes of operation.

The first operation mode is a first write mode in which a title image input manually from the terminal 12 is written into the memory 18.

The second mode is a second write mode in which character data prepared by an external device input manually from the terminal 22 is processed by the data processing circuit 26 and written into the memory 18. The third mode is a superimpose mode in which the image data stored in the memory 18 is superimposed on the video signal input from the terminal 34. Switching between these modes is performed by an operator using an operation panel (not shown).

In the first write mode, a Y signal of a video signal representing a title or a graphic image captured by a camera is input from the terminal 12.

The video signal is input by, for example, creating a title by hand on a blank piece of paper and photographing it with a video camera, or by creating a graphic image with a personal computer and manually outputting it to the terminal 12. A
The /D converter 14 compares the level of the Y signal with a predetermined reference signal level, outputs a value of "O" 1 depending on the magnitude of the Y signal level and the reference signal level, and converts it into digital data. do.

The converted digital data is input to the shift register 16. The shift register 16 has 8 bits of serial data.
The bits are sequentially shifted and stored and output to the memory 18 as 8-bit parallel data.

A horizontal synchronization signal Ho synchronized with the Y signal of the title is input to the terminal 44 . A vertical synchronization signal VD synchronized with the title Y signal is input to the terminal 46. This synchronization is performed, for example, by extracting and amplifying only the synchronization component from a video signal output from a video camera that is photographing the title.

The timing generator 20 responds to the clock signal, the horizontal synchronization signal HD1, and the vertical synchronization signal vo to
Outputs a signal indicating the vertical and horizontal position of the signal on the screen. This signal indicates the address at which data is to be stored in the memory 18.

When data is completely stored in the memory 18 for all title screens input from the terminal 12, the handwritten title image or graphic image is stored in the memory 18 as a binary image divided into a ground part and a title part. will be stored in.

The operation of the second write mode is described below.

In this case, there is no input signal from terminal 12.

The address of the memory 18 is determined by the timing generator 20.
It is specified by the shift register 30 rather than by the shift register 30.

Character data for expressing the title characters as a plurality of dots is input as serial data to the terminal 22 from an external device that stores title characters. This data is based on a so-called dot matrix that expresses a character as a set of dots by specifying whether each dot making up the image is on or off, and is a binary digital signal.

Character data is manually input to the data processing circuit 26 via serial data l1024. The data processing circuit 26 doubles the character data or converts it to increase the thickness of the line, and outputs the data. The output character data is input to a shift register 30 and converted into, for example, 8-bit parallel data. The converted character data is stored in the memory 1 according to the address specified by the shift register 30.
It is stored in 8.

At this time, the memory 18 has already stored a title image or a graphic image. If the output of the shift register 30 is written as is, the data will be erased.

Therefore, when the output of shift register 30 is written to memory 18, each bit of the contents of memory 18 and each bit of the output of shift register 30 are ORed. The first title image or graphic image input from the terminal 12 and the second title image input from the terminal 22 are stored in the memory 18 in a superimposed manner.

Next, the operation of this device when superimposing the title image stored in the memory 18 on the video signal input from the terminal 34 will be explained. From the terminal 34, for example, a video signal captured by a video camera or the like, or a video signal reproduced by a VTR is input.

A horizontal synchronizing signal Ho1 and a vertical synchronizing signal vo of the video signal input to the terminal 34 are input to the terminals 44 and 46, respectively. The timing generator 20 responds to the clock, the horizontal synchronizing signal Ho1, and the vertical synchronizing signal V to output an address signal representing the position on the screen and an OE scratch signal representing the timing of reading from the memory 18. The contents of the address specified by the address signal are stored in the shift register 16.
is output to.

The shift register 16 converts the parallel data read from the memory 18 into serial data by shifting it one bit at a time and outputting it. Color synthesis circuit 3
2 outputs ROB component signals in response to serial data from the shift register 16 in order to display the title in a color specified by the operator.

The display circuit 38 connects the above-mentioned component signals and the terminal 34.
It mixes the video signal from the video signal and outputs the mixed signal to the output terminal 36. At this time, the display circuit 38 switches these signals at high speed in response to the blanking signal so that the title side video is output for the portion where the title image exists, and the video signal is output for the other portions.

The signal output from the output terminal 36 is recorded, for example, on a videotape or the like and played back on a home television or the like.

[Problem to be solved by the invention] As described above, characters input manually from the terminal 22 are transferred to the memory 1.
8 makes it easier to create titles. Further, by storing the title image or graphic image input from the terminal 12 and the character image from the terminal 22 in the memory 18 in a superimposed manner, the degree of freedom in controlling the video is greatly increased. However, the above-described device still has the following improvements.

As mentioned above, the character data from the terminal 22 is stored in the memory 18.
When writing to a memory card, the stored data and the character data to be recorded are logically summed so as not to erase the graphic data etc. already stored there. As a result, for example, if a part of a graphic image overlaps with text, the text in that part may become difficult to see or may disappear.

The isA diagram is an example of a graphic image that is manually written from the terminal 12 into the memory 18 in advance. 5th B
The figure is a schematic diagram when the characters "ABCDE" input from the terminal 22 are superimposed on this graphic image, and the contents of the mesori 18 are reproduced as an image. Figure 5A,
As can be seen from Fig. 5B, the characters 'AB' that overlap the diagonal line part of the graphic image are embedded in the graphic image. In Fig. 5B, these characters are shown with dotted lines, On the actual playback image, the characters “AB”
” becomes completely illegible.

In this case, even if it is possible to superimpose text on a graphic image, it is not possible to obtain an image that satisfies the window when performing advanced title processing.

Therefore, an object of the present invention is to provide a superimposing device in which the second title image is clearly displayed even when the second title image is superimposed on the first title image.

[Means for Solving the Problems] A superimposing device according to the present invention includes a plurality of divided unit storage areas, an image storage means for storing a binary image signal, and a second image storage means. a first image signal writing means for writing an image signal of 1; write determination means, which is connected to receive a write designation signal and determines whether or not to write to the corresponding 111th storage area for each lit image signal according to predetermined conditions, and outputs a write designation signal; a second image signal writing means for writing a unit image signal into the unit storage area in response to the signal, regardless of the value of the binary image signal written in advance in the unit storage area; and a video signal. and video signal superimposing means for superimposing and outputting the image signal stored in the image storage means.

[Operation] The first image signal writing means writes the first image signal into the image storage means. The write determination means receives the second image signal, determines for each unit image signal whether or not to write to the corresponding unit storage area according to predetermined conditions, and in the case of writing, sends a write designation signal. Output. The second image writing means is
In response to the write designation signal, each unit image signal is written to the corresponding unit storage area. At this time, writing is performed in advance for the unit t.
It - Regardless of the contents stored in the storage area, (i
This is done by writing the position image signal as is. The image superimposition means superimposes the image signal stored by the image storage means on the video signal.

[Embodiment] FIG. 1 is a schematic block diagram of a superimposing apparatus according to an embodiment of the present invention. Apparatus 10 shown in FIG.
differs from the conventional device 40 shown in FIG. 4 in that it includes a shift register 31 instead of the shift register 30, a data processing circuit 27 instead of the data processing circuit 26, and Connected and serial! Write determination for determining whether or not to write each character of character data input from the terminal 22 via the terminal 1024 into the memory 18 as an example of an image storage means depending on whether or not it is blank. It further includes means 28.

In addition to the function of the shift register 30, the shift register 31 has a function of writing the value of character data as is into the memory 18, regardless of the storage contents of the memory 18. In addition to the functions of the data processing circuit 26, the data processing circuit 27 has a function of accumulating character data for one character and reconstructing the character, and in response to a write designation signal, transfers the character signal to the shift register 3.
11:: Has a function of selectively outputting each character.

Identical components are given the same names and reference numerals in FIGS. 1 and 4, and their functions are also the same. Therefore, detailed explanation thereof will be omitted here.

The operation of the superimposing device 10 of the present invention will be explained below. A/D converter 1 in first write mode
4 and shift register 16 cooperate to function as a first image signal writing means. shift register 16,
The color synthesis circuit 32 and the display circuit 38 work together in the superimpose mode to function as video signal superimposition means. Of these three modes, the first write mode and the superimpose mode are exactly the same as those in the conventional device 40, so their explanation will be omitted here.

The operation of this superimpose device 10 in the second superimpose mode is as follows. There is no human input signal from terminal 12. The address signal to be written into the memory 18 is sent to the timing generator 20.
rather, it is generated by the shift register 31.

A signal representing character data for expressing each title character as a collection of a plurality of dots is inputted to the terminal 22 from an external device that stores title characters. Each and every letter that makes up the title! The 11th place is image signal. This character data is based on a so-called dot matrix that expresses characters as a set of dots by specifying whether each dot making up the image is on or off. Referring to FIG. 2A, each character is assigned a rectangular area of, for example, 16×16 dots. Each dot is represented as a binary signal depending on whether it is on (dark dot) or off (bright dot).

These dot representations correspond to the dot representation of each character on the video to be played back. In addition, this dot matrix and each dot correspond to an area within the area of memory 18 that is allocated to each character and each bit within that area.

Character data is input to the data processing circuit 27 via the serial I1024. The data processing circuit 27 has an internal memory, for example, and divides input character data character by character and reconstructs it as characters on the memory. At the same time, the data processing circuit 27 sends data for one character being processed to the write determining means 28. The writing determination means 28
Examine all bits included in character data for a character,
If even one dot is on, a write designation signal is sent to the data processing circuit 27. If the character data consists entirely of bits representing off dots,
The write determination means 28 does not output a write designation signal.

When the data processing circuit 27 detects the write designation signal, it sequentially outputs the character data stored in the internal memory to the shift register 31 as a serial data. At this time, the data processing circuit 27 performs various processing on the character data. This is due to the following reasons.

As a device for supplying character data to the superimposing device 10, a device that can easily create data containing kanji characters, such as a so-called electronic notebook or a personal computer, is suitable.

For example, in general, in electronic notebooks, etc., the display area cannot be increased due to miniaturization, and the number of characters that can be displayed at one time is limited. Since there is no particular need to express characters in high definition, the number of dots that make up each character is not so large. - By way of example, with reference to Figure 2A, vertical 6
There are commercially available devices on which one character is represented by 16 x 16 dots on a 4-dot, 96-dot horizontal liquid crystal display.

In this electronic notebook, the line forming each character is formed with the thickness of one dot.

On the other hand, it is assumed that the superimposed video will be played back on a home television. For home televisions, the number of dots that can be displayed on the screen is
For example, 192X192 dots, or 256X25
It is thought to be about 6 dots.

Therefore, if the character data input from the terminal 22 is stored in the memory 18 as is and superimposed on the video signal, the display state of the title characters with respect to the reproduced image will be significantly unbalanced. The imbalance is caused by, for example, each character of the title being extremely small relative to the screen, the characters being close to each other, and the ratio of the title area to the narrow surface of the television becoming small.

Therefore, the data processing circuit 27 processes character data as follows. FIG. 3 is a schematic diagram of a title area showing the principle of this processing. Referring to Figure 3, 16X
A title area in which 16 dot characters are arranged in 4 rows and 6 columns is expanded by the data processing circuit 27 into an area of 192×192 dots.

At this time, in Figure 2A 1. Referring to FIG. 2B, each character undergoes so-called double-angle conversion from a 16x16 dot representation to a 32x32 dot representation. At the same time, a blank line having a width of 16 dots is formed between each line. The area within the memory 18 is also logically divided into a plurality of unit storage areas each having the above-mentioned 32×32 dot area as one unit. The title characters are output to the shift register 31 after undergoing such processing.

Conversion from an area of 64,896 dots to an area of 192×192 dots is possible by associating one dot of manually entered character data with four adjacent dots in the memory 18. This correspondence can be uniquely determined. By preparing a table of this correspondence and storing it in a ROM or the like in advance, and searching this table using a program, a desired conversion operation can be realized. In particular, in the data processing circuit 27, since the original characters are reconstructed once, this processing can be easily performed.

The data processing circuit 27 also further processes the double-width converted character data as shown in FIG. 2B, and turns on the right end or right side of each side of the displayed character by one dot, as shown in FIG. 2C. , it also performs transformations such as enlarging the vertical lines. This increases the thickness of each vertical line in the title text when it is played back on a television, etc., which compensates for the low color resolution in one direction of the water iV and ensures that the color of the title text is correctly expressed. This has the effect of making you feel more comfortable.

Character data output from the data processing circuit 27 is input to a shift register 31, and converted by the shift register 31 into, for example, 8-bit parallel data. The shift register 31 outputs a data storage address signal and stores the character data converted into parallel data in the memory 18.
Write to the specified address. At this time, writing is performed by writing the output contents of the shift register 31 as they are, regardless of the contents of the area specified by the address in the memory 18. By outputting character data in units of characters from the data processing circuit 27, one
The contents of the unit area corresponding to the character are replaced with character data.

That is, the data processing circuit 27 and the shift register 31 cooperate to function as a second writing means.

When the write determination means 28 does not output a write designation signal, the data processing circuit 27 does nothing with the character data of that character and moves on to processing the data for the next character. Therefore, the first image signal is in the unit area of the memory 18 corresponding to this character.

It will be retained as is.

The above-described process is repeated for all character data input manually from the terminal 22. As a result, characters other than blanks are written into the memory 18. In other areas, the first title picture or graphic image written in the memory 18 in the first write mode remains as is. Also,
For characters other than blanks, the values of the rectangular area of the dot matrix constituting the character are written into the memory 18 as they are. Therefore, no first title image or graphic image remains within this area. Therefore, as shown in FIG. 5C, the graphic image is removed from the background of the characters, resulting in clearly displayed characters.

In the embodiments described above, the graphic image was written to the memory 18 first, and then the character data was written to the memory 18. However, the invention is not limited thereto. For example, graphic images may be written to memory 18 after character data is written to memory 18. In that case, prior to writing the graphic image, the memory 18
What is necessary is to provide means for determining whether or not a character is written there for each character in the 01st position.

[Effects of the Invention] As described above, according to the present invention, for each unit image signal included in the second image signal, it is determined whether or not to write to the corresponding unit storage area according to predetermined conditions. A write determination means is provided for outputting a write designation signal. The unit image signal is written into the unit storage area regardless of the contents stored in the unit storage area in advance. That is, the value of the unit image signal is stored as is in the unit storage area.

As a result, in the image recording means, the first (2) image signal and the second image signal are stored separately for each unit storage area, and the two do not overlap. In the superimposed video, the second title image represented by the first image signal is separated from the title image represented by the first image signal at least within a rectangular area corresponding to the 111th storage area. , clearly displayed.

Therefore, it is possible to provide a superimposing device in which even if the second title image is superimposed on the first title image, the second title image is clearly displayed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a superimposing device according to the present invention, and FIG. 2 shows the correspondence between the display state of characters displayed by an external storage device and the display state when they are superimposed. FIG. 3A to FIG. 3C are schematic diagrams showing the representation of characters to be superimposed using a dot matrix; FIG. 4 is a block diagram of a conventional superimposing device; FIG. 5C is a schematic diagram of a display image when a first title image and a second title image are superimposed. In the figure, 10 is a superimposing device, 14 is an A/D converter, 16 is a shift register, 18 is a memory, 20 is a timing generator, 26.27 is a data processing circuit,
28 is a write determination means, 30.31 is a shift register, 3
2 is a color synthesis circuit, and 38 is a display circuit. In each figure, the same reference numerals indicate the same or equivalent parts. Figure 2 32 yen...

Claims (1)

[Claims] (1) An image storage means comprising a plurality of divided unit storage areas and for storing a binary image signal, and a first image storage means for writing a first image signal into the image storage means.
an image signal writing means connected to receive a second image signal that is different from the first image signal and includes a unit image signal that is associated with the unit storage area in advance, and that write determination means for determining whether or not to write to the corresponding unit storage area for each unit image signal and outputting a write designation signal; a second image signal writing means for writing the unit image signal into the unit storage area regardless of the value of the binary image signal written in advance; and a second image signal writing means for writing the unit image signal into the unit storage area; and a video signal superimposing means for superimposing and outputting an image signal.