JPH0382249A - Demodulation circuit for psk signal - Google Patents

Abstract

PURPOSE:To eliminate the need for a multiplier circuit and a low pass filter and to attain LSI by extracting a PCM signal Se (signal Se) from a QDPSK signal in digital processing. CONSTITUTION:A QDPSK signlal Sq from an amplifier 62 is fed to a waveform shaping circuit 101, where the signal is shaped to a level of '0' or '1' and the result is fed to a D input of D flip-flops 102A, 102B. Moreover, the signal Sq from the shaping circuit 101 is fed to a clock recovery circuit 103. The signal Se is demodulated from the QDPSK signal Sq, and in this case, the demodulation is realized by the digital processing entirely. Thus, a multiplier circuit and a low pass filter are not required and LSI is attained.

Description

[Detailed description of the invention] The explanation will be given in the following order.

A. Industrial application field B. Summary of the invention C Conventional technology D Problems to be solved by the invention E Means to solve the problem (Figure 1 F Effect G Example G1 First embodiment (Figure 1) G2 second embodiment (Figure 2) G3 third embodiment (Figures 3 to 5) G. Other embodiments Effect of H invention A. Industrial application field The present invention relates to a PSK signal demodulation circuit.

B. Summary of the Invention The present invention improves the error rate during reproduction by performing digital demodulation or feedback on the 1st and Q channel PSK signals in a PSK signal demodulation circuit.

C. Digital recording and reproduction of conventional technology audio signals;
A new VTR is being considered.

FIG. 6 shows an example of a recording system of such a VTR, and FIG. 7 shows an example of its reproducing system.

During recording, a color composite video signal of the NTSC system, for example, is supplied to a Y/C separation circuit (12) through a terminal (11) to separate a luminance signal sy and a carrier color signal Sc, and the signal sy is converted into an FM signal. Modulation circuit (13
) is converted into an FM signal Sf as shown in FIG. 8, and this FM luminance signal Sf is supplied to an adder circuit (14).

Further, the signal Sc from the separation circuit (12) is supplied to the frequency converter (15), and as shown in FIG.
The frequency is converted to a carrier color signal Sc whose phase is controlled so as to be interleaved with each other in the odd field period and the even field period, and this signal Sc is supplied to the adder circuit (14>). .

Therefore, from the adder circuit (16), the signals Sf and Sc
A summation signal Ss is taken out, but this signal Ss is
The signal is alternately supplied to the rotating magnetic heads (1^) and (IB) through the recording amplifier (17) and the switch circuit (18) every one field period.

In this case, the heads (LA) and (IB) have different slit angles (so-called azimuth angles), for example ±10"
For example, as shown in FIG. 9, they have a slit angle of 180° from each other, and are rotated at a frame frequency in synchronization with the signal Sy. A magnetic tape (5) is wound diagonally around the rotating peripheral surfaces of the heads (IA) and (1B) over an angular range of over 180 degrees, and is run at a predetermined speed.

In addition, the stereo left and right channel audio signals are sent to the A/D through terminals <2mL), (2mR).
For example, PCM with a sampling frequency of 48 kHz and 1 sample of 16 bits is supplied to the converter (22).
The PCM audio signal Sp is linearly quantized into a signal Sp, and this PCM audio signal Sp is supplied to an encoder (23) to perform encoding processing for error correction, and to generate a slight no-signal period at the beginning of each field period. The time-base compressed signal Se is extracted.The bit rate of the signal Se at this time is 16 x 48 XIO' x 2 channels + redundant bits = 2 Mbps.

Then, this signal Se is transmitted to the QDPSK modulation circuit (24)
is supplied to a QDPSK signal Sq whose carrier frequency is intermediate between the signals Sc and Sf, for example, 2.5 MHz, and this signal Sq is sent to a rotating magnetic head (2^) through a recording amplifier (27) and a switch circuit (28>). ), (2
B) are alternately supplied every one field period.

In this case, the heads (2A), (2B) have an angular spacing of 180° from each other, as shown in FIG. 9, and are rotated together with the heads (IA), (1B). Also, at this time, Heud (2A), (2B)
are preceded by head (IA) and (1B), respectively, and head (2A).

Each scanning locus of (2B) and the head (IA), (1B)
A step is given so that each scanning trajectory of the head (2A) and (2B) coincide with each other, and the slit angle of the head (2A) and (2B) is the same as that of the head (LA).

(IB) is in the opposite direction, for example, +:20°. Furthermore, during the field period when the signal Ss is supplied to the head <1^> or (18),
B> so that the signal Sq is supplied to the switch circuit vII.
(1B).

The phases of switching (28) are matched.

Furthermore, the audio signal at the terminal (2m) or <31) is supplied to the FM modulation circuit (32), and as shown in FIG.
This FM audio signal Sa is sent to a rotating magnetic head (3A) through a recording amplifier (37) and a switch circuit (38).
, (3B) are alternately supplied every one field period.

In this case, the heads (3^) and (3B) have an angular spacing of 180° from each other, as shown in FIG. 9, and are rotated together with the heads (IA) and (1B). Also, at this time, head (3^), (3B)
are preceded by heads (2A) and (2B), respectively, and head (3A).

Each scanning locus of (3B), head (1^), (1B
) are given a step so that they match each scanning locus. Also, the slit angle of heads (3A) and (3B) is head (IA).

(IB) in the same direction but at a larger angle, e.g. ±3
0゛. Furthermore, the head (1^) or
The switching phases of the switch circuits (18), (2g), and (38) are adjusted so that the signal Sa is supplied to the head (3^) or 3B> during the field period when the signal Ss is supplied to the head (3B). Can be matched.

Also, at this time, the head (
IA, IB), (2A, 2B), (3A, 3
B) If the recording currents flowing through are currents Is, Iq, and Ia, then Ia>Iq>Is.

Therefore, first, one field of the signal Sa is recorded as one diagonal magnetic track by the head (3A> or (3B), and the signal Sq is recorded by the head (2^> or 2B) overlapping the magnetic track. The l field of the recording signal Ss is recorded by the head (l^ or IB) overlapping the magnetic track. At this time, the recording currents Ia, Iq, Is Since the size of is set as described above, the signal Sa is mainly recorded in the deep layer of the magnetic layer of the tape (5), and the signal Sq is mainly recorded in the intermediate layer, as shown in FIG. The signal Ss is mainly recorded on the surface layer.

On the other hand, during reproduction, signals Ss are alternately reproduced from the tape (5) by the heads (IA) and (1B) every one field period, and this signal Ss is transmitted to the switch circuit (41).
) is supplied to a continuous signal Ss, and this signal Ss
is passed through the reproduction amplifier (42) to the bandpass filter (4).
3) and the signal Sf is taken out, and this signal Sf
is passed through the IJ transmitter (44) to the FM demodulation circuit (45).
The signal Sy is demodulated, and this signal Sy is supplied to the adder circuit (46).

Further, the signal Ss from the amplifier (42) is supplied to a bandpass filter (53) to extract the signal Sc, and this signal Sc is supplied to the frequency converter (55) through the ACC circuit (54) to be converted to the original carrier. The signal is frequency-converted to a carrier color signal Sc of the frequency, and is also subjected to phase processing and complementary phase processing during recording, resulting in a signal Sc having the original phase. This signal Sc is then supplied to the adder circuit (46) through the C-shaped comb filter (56).

Therefore, the original color composite video signal is obtained from the adder circuit (46), and this is taken out to the terminal (47).

Furthermore, the tape (
5), the signal Sq is alternately reproduced every field period, and this signal Sq is supplied to the switch circuit (61>) to form a continuous signal Sq. The chiaria signal is supplied to the circuit (63) and also to the chiaria signal reproducing circuit (64>) to regenerate the chiaria signal, and this chiaria signal is supplied to the demodulation circuit (63) to demodulate the signal Se from the signal Sq.

Then, this signal Se is supplied to the decoder (65>) to decode the signal Sp, error correction and correction are performed, and this signal Sp is sent to the D/A converter (65).
66) and is converted into the original left and right channel audio signals, which are sent to the terminals (67L) and (67
R) is taken out.

Also, the tape (5
) is alternately reproduced every field period, this signal Sa is supplied to a switch circuit (71) to form a continuous signal Sa, and this signal Sa is sent to a reproduction amplifier (72), a bandpass Filter (73) and limiter (
74) to the demodulation circuit (75) and the terminal <7
7), the audio signal is extracted.

As described above, video signals and audio signals are recorded and played back, but in this case, in the above-mentioned VTR, the audio signals are digitized and recorded and played back, so it is possible to obtain extremely high sound quality similar to that of digital audio equipment. I can do it. Furthermore, since the audio signal is also recorded and reproduced as the FM signal Sa, compatibility with conventional VTRs can be achieved.

Furthermore, since the PCM signal Se is converted into the QDPSK signal Sq, the occupied band can be narrowed.

By the way, if the bits obtained by integrally converting, for example, the odd-numbered bit "a" and the even-numbered bit b in the signal Se, are bits a, , b, then QDPS
The K signal Sq is: 3 q = cos (ωat + φ) ωc = 2πf f: carrier frequency (f = 2.5 MHz) φ = π
/4 a I= 0, b When I= 0, k=1a
When I=1, b t = Q, k=3a+=
1. When b+=1, k=5a l=O, b t
When = 1, k = 7.

Therefore, the demodulation circuit (63) can be configured as shown in FIG. 11, for example.

That is, the QDPSK signal S from the reproduction amplifier (62)
q, ■ and Q channel multiplication circuit (synchronous detection circuit)
(91A) and (91B), and is also supplied to the carrier regeneration circuit (64) to receive the carrier signal S7S.
The signal S7 is then supplied to a phase shift circuit (68) to generate the carrier signal S.

S e =s+n C1)ct are taken out, and these signals S,,S, are sent to the multiplier circuit (91
^), (91B) and the signal Sq is supplied to the signal S,.

S8 performs synchronous detection and extracts bits at, t)+(bit string of bits allbl).

Then, these bits a, , b are filtered by a low-pass filter (
92^), (92B) to remove unnecessary signal components, and then the waveform shaping circuit (93A), (93
B) The bit a l + bI that is supplied to the bit a l +bI and shaped to a level of "0" or "1" is taken out.

Although not shown in the drawings from now on, this bit a is
bi is converted into a signal Se and a signal Sp in order, and an audio signal is reproduced.

D. Problems to be Solved by the Invention However, in the demodulation circuit (63) as described above,
Multiplier circuits (9, lA), (91B) and low-pass filters (92^), (92B) are required,
Moreover, these circuits are analog circuits, which is inconvenient for LSI implementation.

Furthermore, the error rate of the reproduced PCM signal Sp is 1.
Bit a from filter (92A>, (92B)
,,b.

Since the signal-to-noise ratio is almost determined by the S/N of , it is disadvantageous to perform analog processing in the demodulation circuit (63) as described above.

This invention attempts to solve these problems.

E Means for Solving the Problems Therefore, in this invention, 2″ phase (m≧2) P
To demodulate m-bit data from the SK signal, the PSK signal is supplied to the D inputs of 2m D flip-flops, a reference phase signal is formed from the PSK signal, and the phase is determined from the reference phase signal. forms (m-1) signals every 2π/2m, and supplies the reference signal and the (m-1) signals to the clock inputs of the 2m D flip-flops, respectively. This is a PSK signal demodulation circuit which extracts the m-bit data from the outputs of D flip-flops.

Furthermore, in this invention, 2m phase (m≧2) PS
To demodulate m-bit data from the K signal, the PSK signal is supplied to 2m multiplier circuits, a reference phase signal is formed from the PSK signal, and the phase is 2π/2m from the reference phase signal. The reference signal and the (m-1) signals are respectively supplied to the 2'' multiplier circuits, and these 2
The above m-bit data is extracted from the m multiplication circuits as their multiplication output, and the error rate of this extracted data is detected, and based on this detection output, the above error rate is set to a minimum value or a value close to the minimum value. , a PSK signal demodulation circuit configured to control the phase of the reference signal.

The signal Se is extracted from the F-effect QDPSK signal by digital processing.

G Actual, Stream Side G1 First Embodiment FIG.
” or “1” level and then supplied to the D inputs of the D flip-flops (102A) and (102B).

Further, the signal Sq from the shaping circuit (101) is supplied to the clock recovery circuit (103). This reproducing circuit (103) includes, for example, a quadrupling circuit having two stages of double-wave rectifier circuits, a PLL to which the quadrupled output is supplied, and a frequency dividing circuit that divides the PLL output into 1/4. ,
Can be configured.

Then, a clock CK with a phase corresponding to the signal S7 is taken out from this reproduction circuit (103), and this clock CK is supplied to the clock input of the flip-flop (102^), and this clock CK is phase-shifted. The phase of the signal S is shifted by π/2 by the circuit (104).
The clock PSCK has a phase shift corresponding to 8, and this clock PSCK is supplied to the clock input of the flip-flop (102B).

Therefore, the signal Sq is the clock CK.

Flip-flop (102A), (1
02B), the signal Sq is clock C
K.

This means that PSCK is equivalently synchronously detected, and the Q of flip-flops (102^) and (102B)
The bits al+bl are obtained from the output.

These bits ai and b1 are supplied to the D input of the D flip-flop (IIIA) (111B), and are also supplied to the exclusive OR circuit (112^).
, (112B). In addition, a regeneration circuit (10
3) A clock BTCK with a phase synchronized with bits ai and bl is extracted from
It is supplied to the clock input of the flip-flop (IIIB) and also to the clock input of the flip-flop (IIIA) through the inverter (116). And flip-flop (111^), <1118)
The Q output of is an exclusive OR circuit (112A)
, (112B).

Therefore, an exclusive OR circuit (112^).

In (112B), delayed detection is performed using bits at, bt, and the bit delayed by one time slot, so these four exclusive OR circuits (112B)
For example, odd-numbered bits aj and even-numbered bits b of the signal Se are extracted from 2A) and (112B).

Then, these bits aj, bj are connected to an AND circuit (1
13A), (113B) l: Hey, clock B
TcK and its inverter output gate gates are pj)aj, bj located alternately on the time axis, and these pip)a4. J is supplied to an OR circuit (114) and J is converted into alternating serial data, ie, the original signal Se.

This signal Se is sent to the flip-flop (115)
is supplied to the D input of the reproducing circuit (113).
The clock is supplied from the flip-flop (11
3) A self-clocked signal Se is extracted from the Q output of the decoder (65).
and a D/A converter (66), and the original audio signal is extracted.

In this way, the signal Se can be demodulated from the QDPSK signal Sq. In this case, especially according to the present invention, the demodulation is realized entirely by digital processing, and the multiplication circuit (
91^), (91B) and low-pass filter (9
2A) and (92B) are not required, so it can be implemented as an LSI.

In addition, since bits a,,b, or a'',b'' are also digitally processed, playback PC
An increase in the error rate of the M signal Sp can be suppressed.

Furthermore, the regeneration circuit (1
03), and no dedicated formation circuit is required. In addition, when performing analog demodulation as described above, a self-clock D channel is used for the I channel of bit ait aJ and the Q channel of bits b, , b.
Each requires a flip-flop, which is also unnecessary.

G2 Second Embodiment In the example shown in FIG.
＾), (102B) is supplied to the 0-man power, and is also supplied to the delay circuit (12m) and delayed for one slot period, and the delayed output is sent to the flip-flop (102B).
A).

(102B) clock power is supplied.

Therefore, the flip-flop (102A), (10
The bits al;bt are obtained from the Q output of 2B).

Also, this bit b1 is set to the clock regeneration circuit (122
) to regenerate the clock, and this clock is supplied to the clock input of the 7-lip flop (115), and the frequency divider circuit (123>
The clock BTCK is divided into 72 frequencies, and the clock BTCK and its inverter output are supplied to the clock inputs of the flip-flops (111B) and (IIIA).

Therefore, similarly to the above example, the QDPSK signal Sq
The signal Se is demodulated from the signal Se, and the original audio signal is further extracted.

In this example as well, the demodulation is realized entirely by digital processing, and the multiplication circuits (91A), (91B)
Since low-pass filters (92^) and (92B) are not required, it can be implemented as an LSI.

In addition, since pits a, b, or aJ, bJ are also digitally processed, playback PC
An increase in the error rate of the M signal Sp can be suppressed.

G. Third Embodiment In the example shown in FIG. 3, the recording signal Sq is a QPSK signal, and bits a4 . bj
This is a case in which feedback is applied from the PCM decoder (65) so that the error rate is minimized when demodulating.

That is, the QPSK signal Sq from the amplifier (62) is
The signal S is supplied to the multiplier circuits (131^) and (131B), and is also supplied to the variable delay circuit (132) and delayed by approximately l slot period to form the signal S.

is supplied to the multiplication circuit (131^). Also, signal S.

is supplied to the phase shift circuit (133) and phase-shifted by π/2 to form a signal S, and this signal S8 is supplied to the multiplier circuit (133).
131B).

Therefore, the multiplication circuit (131A), (131B)
In , synchronous detection is performed and a4. bJ is taken out.

And these bits a4. J is supplied to a low-pass filter (134^), (134B) to remove unnecessary harmonic components, and then sent to a voltage comparison circuit (135A).
, (135B), and a DC component detection circuit (136A).

(136B) and extracts the DC component of the comparator circuit (135A), (
135B) and a comparison circuit (135A), (1
35B), bit a4. bj is retrieved.

Then, this waveform-shaped signal aJ, J is the D of the D flip-flop (137A), (137B).
P L L (138^),
(138B) to extract the clock,
This clock is a flip-flop (137^), (1
37B) is supplied to the clock input of the flip-flop (137^), and the D output of (137B) is a self-clocked pin) a), b).

is taken out.

The self-clocking bits a'', b
j is supplied to a register (parallel/serial conversion circuit) (138) and integrated into a signal Se, and this signal Se is sequentially supplied to a decoder (65) and a D/A converter (66) to extract an audio signal. .

Further, in the decoder (65), the signal Se is changed to the signal S.
When decoding p, the digital signal Sd that detects the error rate Ei is extracted, this signal Sd is supplied to the microcomputer (141), and the microcomputer (141) executes the routine (20 in FIG. 4, for example).
0) is executed and nine control voltages are output, and this voltage V1 is converted into an analog voltage by the D/A converter (142) and then supplied to the delay circuit (132) as its control signal.

Then, the routine (200), as shown in FIGS. 5A and 5B, controls the phase of the signal S7 to an appropriate value by a so-called hill-climbing method.

That is, in the routine (200), the processing of the microcomputer (141) starts from step (201), and in the following step (202), the voltage V
, is set to the initial value V0, and then step (203)
In step (204), the error rate E0 when Vt=Va is detected by the signal Sd.
At this point, the loop counter N is reset to "0".

Next, in step (2m1), the counter N is
l”, followed by a step (2m2
), the voltage V, is increased by a predetermined amount ΔV,
Next, in step (2m3), the error rate El at this time is detected, and then in step (2m4), it is checked whether El>Eo.

Now, when steps (202) and (203) are executed, if the coordinates of voltage vq<=va> and error rate E1 (=E0) are point P0 in FIG. 5A, then the current The coordinates of are point Pt, and E + <
E a .

And El<E. If so, the process takes steps (2m4
), the process proceeds to step (2m5), and in this step (2m5) E o =E is established, and then the process returns to step (2m1). therefore,
After that, steps (2m1) to (2m5) are repeated,
In the case of FIG. 5A, the coordinates of voltage V7 and error rate El move from point P to point P2 to point P.

Then, when El > Eo, that is, in the case of A in Figure 5, move to point P3 and make El > Ea.
Then, this is determined by step (2m4),
Processing is from step (2m4) to step (2m6)
Proceeding to step (2m6), the voltage V, is reduced by the value ΔV. Therefore, Fig. 5A
In this case, the coordinates of the voltage V and the error rate Ei have returned from the point P to the point P2, and at this time, the error rate Ei has become a minimum value or a value close to the minimum value.

Next, the process proceeds to step (22m), and in this step (22m), it is checked whether or not it is N22. In this case, since it is N22, the process continues from step (22m) through step (227) to step (228). ) and ends the process for voltage V (step (227) is a non-executive step). Therefore, at this time, voltage V causes signal S.

The error rate Ei in the decoder (65) is minimized by controlling the phase of the decoder (65).

On the other hand, when steps (202>, (203)) are executed, voltage vt (=vo) and error rate Ei (
=Eo) is the point P0 in FIG. 5B, the coordinates when step (2m4) is executed for the first time are the point P1, and El>Eo.

Therefore, in this case, the process takes steps (2m4)
Proceed from step (2m6) and step (2m6).
m5) is not executed. Also, step (2m6)
The voltage V, is reduced by the value ΔV and becomes v,=V,
Therefore, the coordinates have returned to point Pa. moreover,
N=1.

Then, in the next step (22m), it is checked whether it is N22, but in this case, N=1, so
Processing is from step (22m) to step (222)
In this step (222), the voltage V,
(=VO) is reduced by the value ΔV, and then step (2
23), the error rate E2 at this time is detected, and then in step (224), Ea>Eo
is checked.

And in this case, steps (222), (223)
Therefore, the coordinates have moved from point P0 to point P2, but in the case of FIG. 5B, Ea<Ea at point P2.

If EO<Eo, the process proceeds to step (224
), the process proceeds to step (225), where E,=E is set, and then the process returns to step (222). Therefore, steps (222) to (225) are repeated thereafter, and in the case of FIG. 5B, the coordinates of voltage V'r and error rate Ei move from point P2 to point P3 to point P. To go.

When Ea>EO, that is, in the case of FIG. 5B, when Ea>Eo after moving to point P,
This is determined in step (224)', and the process proceeds from step (224) to step (226), where the voltage V is set to the value Δ
V is increased. Therefore, in the case of FIG. 5B, the coordinates of voltage V and error rate Ei are point P,
This means that the process has returned to point P3, and at this time, the error rate El has become the minimum value or a value close to the minimum value.

Thereafter, the process proceeds to step (228) through step (227), and this routine (200)
end.

Therefore, at this time, the voltage V7. V8 causes signal S
, the error rate Ei in the decoder (65>) is minimized.

Furthermore, if the coordinates are point P2 in Figure 5A when steps (202) and (203) are executed, then
In step (22m), N=1, so the process goes from step (22m) to step (222).
However, steps (222) and (226) are executed only once each, so there is no problem.

As described above, the audio signal is reproduced from the QPSK signal Sq on the tape (5), but in this case, the signal S7
When adjusting the PCM signal Se from the QPSK signal Sq, the phase of the signal S7 is controlled so that the error rate at the decoder (65) is minimized.
An audio signal can be obtained from the PCM signal Sp with the minimum error rate.

G4 Other Embodiments Note that in the above, the reproduced signal QDPSK signal Sq1
That is, in the case of a 4-phase PSK signal, 2m phase (m
≧2) When demodulating m-bit data from a PSK signal, a 2m1 channel demodulation system is constructed in the same manner as described above, and the phase shift formed from the PSK signal is 2π/2m.
It is sufficient to supply m clocks (carrier signals) for each.

In addition, in the circuit shown in FIG. 3, when the signal Sq is a QDPSK signal, the multiplication circuits (131A), (131B)
The latter part can be digitized in the same way as in FIG. 1 or FIG. 2.

Effects of the invention H According to this invention, the demodulation is realized entirely by digital processing, and the multiplication circuits (91^), (91B) and low-pass filters (92A), (92B) are unnecessary, so it can be implemented in an LSI. .

In addition, since ain bi or aj, J is also digitally processed, it is possible to suppress an increase in the error rate of the reproduced PCMjN number Sp due to a decrease in S/N.

Furthermore, the regeneration circuit (1
03), and a dedicated formation circuit is not required. Also, when performing analog demodulation as described above, the ■ channel of bit al+aJ and the bit b
,,bj Q channel and D for self clock
Each requires a flip-flop, which is also unnecessary.

[Brief explanation of drawings]

Figures 1 to 3 are system diagrams of a part of this invention;
Figures 1 to 11 are diagrams for explaining the same. (5) is a magnetic tape, (65> is a decoder, (66) is a D/°A converter, (102A), (102B),
(IIIA), (111B). (115), (137A), (137B) are D
Flip-flop, (103), (122n is a black γ error reproduction circuit, (12m> is a delay circuit, (132)
is a variable delay circuit, (133) is a phase shift circuit, (1
38) is a register. Agent Hidemori Matsukuma Part 5 Illustrated training series m-(2)

Claims (1)

[Claims] In demodulating m-bit data from a 1, 2^m phase (m≧2) PSK signal, the PSK signal is demodulated by the D of 2^m D flip-flops.
A reference phase signal is formed from the PSK signal, and (m-1) signals with a phase of 2π/2^m are formed from the reference phase signal, and the above reference signal and the above (m-1) signals in the above 2^
are supplied to the clock inputs of m D flip-flops, and from the outputs of these 2^m D flip-flops the m
A PSK signal demodulation circuit that extracts bit data. To demodulate m-bit data from a 2,2^m phase (m≧2) PSK signal, the above PSK signal is supplied to each of the 2^m multiplier circuits, and a reference phase signal is obtained from the above PSK signal. From this reference phase signal, (m-1) signals with a phase of every 2π/2^m are formed, and the reference signal and the (m-1) signals are combined with the above 2^
The above m-bit data is extracted from these 2^m multiplication circuits as their multiplication output, and the error rate of this extracted data is detected. Based on this detection output, the above A PSK signal demodulation circuit that controls the phase of the reference signal so that the error rate is at a minimum or a value close to the minimum.