JPH0379949U - - Google Patents
Info
- Publication number
- JPH0379949U JPH0379949U JP14180189U JP14180189U JPH0379949U JP H0379949 U JPH0379949 U JP H0379949U JP 14180189 U JP14180189 U JP 14180189U JP 14180189 U JP14180189 U JP 14180189U JP H0379949 U JPH0379949 U JP H0379949U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- scanning direction
- address
- generates
- sub
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案のブロツク図、第２図は縦横変
換処理しない時のタイミングチヤート、第３図は
縦横変換処理時のタイミングチヤート、第４図は
実施例におけるメモリマツプ図、第５図は縦横変
換処理時の読み出し順序の説明図、第６図は従来
の縦横変換処理のブロツク図である。
１……ＣＰＵ、２，３，６……ラツチ、４……
マルチプレクサ、５，８……加算器、７……カウ
ンタ、９……セレクタ、１０……メモリ、２１…
…マルチプレクサ、２２……ドツトカウンタ、２
３……ラインカウンタ、２４……画像メモリ。
Fig. 1 is a block diagram of the present invention, Fig. 2 is a timing chart when no vertical/horizontal conversion processing is performed, Fig. 3 is a timing chart during vertical/horizontal conversion processing, Fig. 4 is a memory map diagram in the embodiment, and Fig. 5 is a timing chart when vertical/horizontal conversion processing is not performed. FIG. 6, which is an explanatory diagram of the readout order during conversion processing, is a block diagram of conventional vertical/horizontal conversion processing. 1... CPU, 2, 3, 6... Latch, 4...
Multiplexer, 5, 8...Adder, 7...Counter, 9...Selector, 10...Memory, 21...
...Multiplexer, 22...Dot counter, 2
3... Line counter, 24... Image memory.
Claims (1)
て主走査方向のメモリ読み出しアドレスを発生す
るカウンタ回路と、加算器とラツチ回路から構成
された副走査方向の各ラインの読み出し先頭アド
レスを発生する回路と、該主走査方向のアドレス
と該副走査方向の先頭アドレスを加算してメモリ
の読み出しアドレスを発生する回路からなり、縦
横変換処理することを特徴とした画像メモリ制御
回路。 In an image memory control circuit of a color printer or the like, a counter circuit that generates a memory read address in the main scanning direction, a circuit that generates a read start address of each line in the sub-scanning direction, which is composed of an adder and a latch circuit, and the main An image memory control circuit comprising a circuit that generates a memory read address by adding an address in a scanning direction and a start address in the sub-scanning direction, and performs vertical/horizontal conversion processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14180189U JPH0379949U (en) | 1989-12-06 | 1989-12-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14180189U JPH0379949U (en) | 1989-12-06 | 1989-12-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0379949U true JPH0379949U (en) | 1991-08-15 |
Family
ID=31688662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14180189U Pending JPH0379949U (en) | 1989-12-06 | 1989-12-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0379949U (en) |
-
1989
- 1989-12-06 JP JP14180189U patent/JPH0379949U/ja active Pending