JPH0378593B2 - - Google Patents

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention is an echo detection device that emits wave pulses such as radio waves or ultrasonic waves, such as radar or sonar, and performs detection by receiving the reflected waves. , especially converting the received signal into a digital signal and storing it in memory,
The present invention relates to an echo detection device that reads out the memory in synchronization with the scanning of a scanning display and supplies the read signal to the scanning display for display.

"Prior Art" For example, in a radar, as shown in FIG. 4, the antenna 12 is
A pulse radio wave is emitted from the antenna in the directional direction, the reflected wave is received by the antenna 12, and the receiver 13 amplifies and detects the wave. The output of the receiver 13 is sent to the AD converter 14
and is sampled at a constant cycle in the AD converter 14 by a clock pulse given from a clock source 25. For details, sampling is performed at a sampling frequency according to the detection range. Each sample value is converted into a digital signal of one bit or a fixed number of bits, and the converted digital signals are sequentially stored in the buffer memory 15. The detection signal stored in the buffer memory 15, that is, the received signal, is read out during, for example, a blanking section of the scanning display 16 and transferred to the main memory 17. The main memory 17 can store picture elements at addresses corresponding to each position represented by orthogonal coordinates on the display surface of the scanning display 16, and the main memory 17 can store picture elements in synchronization with the scanning of the scanning display 16. 17 is read out, and the read output is converted into a color signal by a color converter 18, for example, and supplied to the color display 16 as a display signal for displaying a color according to the value of the digital signal.

Horizontal and vertical scanning is generally used to scan the display surface of the scanning display 16.
Since the received signal output from the receiver 13 is a signal to be displayed in polar coordinates, the main memory 17
Coordinate transformation is performed when writing the received signal to A. This coordinate transformation can be performed, for example, in Utility Application No. 59-135361
61-050284) "Coordinate transformation display device". In other words, in the case of radar, the directional direction of the antenna 12 is the direction of the motor 19.
The angle pulse generator 21 generates an angular pulse every certain angle, and this pulse is supplied to the coordinate conversion address generator 22A. The write address for data transfer from the buffer memory 15 to the main memory 17 is transferred from the coordinate conversion address generator 22A to the main memory 1 through the selector 23.
7 is given.

A read address generator 24 is provided for the coordinate conversion address generator 22A. The read address generator 24 receives the scanning signal of the scanning display 16, and
A read address signal is generated in synchronization with this scanning signal, and the display 16 performs horizontal and vertical scanning based on the scanning signal. Along with this, the read address generator 2
The address from 4 is supplied to the main memory 17 through the selector 23, and the main memory 17 is read out in synchronization with the scanning of the scanning display 16.

On the other hand, 26 indicates a mark signal generator. This mark signal generator 26 generates a mark signal for displaying dot-shaped marks M at, for example, 5° intervals along a circle having an arbitrary radius R as shown in FIG. 5 on the display surface of the display 16. do.

The configuration for this includes, for example, a preset counter 27, a setting device 28 for setting the radius R of the circle drawn by the mark M, and a coordinate exchange address generator 22B.
, a selector 29 for selecting the write address output from the coordinate exchange address generator 22B and the read address output from the read address generator 24, and a sub-memory 31 for storing the mark signal output from the preset counter 27. It can be configured by

Preset counter 27 counts clock pulses applied from clock source 25, and when the counted value matches the value set in setter 28, outputs a mark signal. This mark signal is the sub memory 3
1 and writes a mark signal at the address determined by the coordinate exchange address generator 22B. The mark signal is written to the sub memory 31 when an instruction to display the mark M is given or when the radius R of the circle is given.
When the mark M is changed, the mark M is written for one revolution of the circle, and the process ends.

The mark signal read from the sub-memory 31 is converted into, for example, a white signal by the color converter 18B and is applied to the display 16 through the gate 32.
The gate 32 is structured to prevent passage of the received image signal outputted from the main memory 17 every time a mark signal is outputted from the mark signal generator 26, and to display the mark M even at a position where a received signal is present.

``Problems to be Solved by the Invention'' The structure of the conventional mark signal generator 26 described above has the drawback that the mark M is missing in some places. Since gaps occur where the display should normally be displayed at 5° intervals, there is an inconvenience that the distance to the target object cannot be accurately measured in the vicinity where the gaps occur.

The reason why the mark M is missing will be explained below.

Coordinate conversion address generator 22B (same as 22A)
For example, as shown in FIG.
An X address counter 34A and a Y address counter 34B that add and subtract angle data read from A and 33B, and an angle data memory 33
It can be constituted by address counters 35A and 35B that provide read address signals to the angle data memories 33A and 33B, and an angle area designator 36 that specifies the angle data area stored in the angle data memories 33A and 33B.

The angle data memories 33A and 33B can be constructed from ROM. Angle data memory 3
For example, cosine data for the azimuth angle θ is stored in 3A, and sine data is stored in angle data memory 33B.

That is, the angle data memories 33A and 33B are provided with storage areas A ₁ , A ₂ , A _{3 .} . . for each angle necessary to draw the mark M, as shown in FIG. These storage areas A ₁ , A ₂ , A ₃ ... are from the angle designator 10.
The output of the angle area designator 36 is updated with the angle data output every 5 degrees, and the memory 33A, 33B
The storage areas A ₁ , A ₂ , A ₃ . . . are selected. When an area is specified, address counters 35A and 35B
starts reading from the first address of each area A ₁ , A ₂ , A _{3 .} . . .

For example, when 90° is selected, the angle data memory 33A outputs logic "1" every time the clock pulse Pa is applied to the address counters 35A and 35B as shown in FIG.
All "0" logic is output from the angle data memory 33B. In other words, when θ=90°, only the X address counter 34A receives a cross pulse, as is clear from the schematic diagram of the addresses of the sub memory 31 shown in FIG.
Each time Pa is supplied, the Y address counter 34B increments as x ₁ , x ₂ , x ₃ . . . x ₁₂ , and the Y address counter 34B does not increment at all.

On the other hand, when θ=0°, the X address counter 34A does not increment at all, but the Y address counter 34B increments y ₁ , y ₂ , y every time the clock pulse Pa is supplied.
Step like y ₃ ...y ₁₂ .

Note that the X address counter 34A and the Y address counter 34B are up-down counters that can be preset, and the angle data memories 33A, 3
The initial value is preset at the time when reading starts from the first address of each area A ₁ , A ₂ , A _{3 .} . . of 3B.
This initial value makes the upper left corner of the display 16 correspond to the top address, and presets the value of the address corresponding to the center point K of the display 16.

Therefore, in the first quadrant, the X address counter 34A
is controlled to operate as an up counter, and Y address counter 34B is controlled to operate as a down counter.
In the second quadrant, the X address counter 34A and the Y address counter 34B are controlled to operate as down counters, thus generating XY addresses corresponding to each coordinate in the first to fourth quadrants.

For example, when θ=45° is selected, the memory address corresponding to the position of radius R is x ₉ , y ₉ in the example shown in the figure. That is, when θ=0° or θ=90°, the address corresponding to the position of radius R is (x ₁₂ , y ₁₂ ) when θ=0°. Moreover, when θ=90°, it becomes (x ₁₂ , y ₁₂ ). Therefore this address (x ₁₂ ,
When y ₁₂ ) and (x ₁₂ , y ₁₂ ) are accessed, a mark signal is output from the preset counter 27, and the mark signal is written to these addresses.

As is clear from this, 12 addresses are allocated when θ=0° and θ=90°, but θ=
In the case of 45 degrees, 9 addresses will not be allocated.

Assuming that the distance of the radius R is sampled 12 times as in this example and the data is written to the secondary memory 31, if θ = 45°, the increment of the X and Y addresses is temporarily stopped at an intermediate address and the same data is written. A condition must be created to write data to the address twice.

This situation will be specifically explained below. FIG. 10 shows the state in which each sample point (indicated by 1 to 12) in the 45° direction is projected in the 0° direction (Y-axis) and the 90° direction (X-axis), respectively. For example, the third sample point and the fourth sample point are
It is projected within the unit distance between the second sample point and the third sample point in the 90° direction (on the X axis). For this reason, the address in the X direction is prevented from incrementing at the fourth sample point. In other words, the content of 45° in the angle data memory 33A (Fig. 6) is the 10th
As shown in the figure, when two sample points are projected within a unit distance in the 90° direction, the content of the corresponding memory cell is set to "0" for the latter sample point, and one sample point is projected within a unit distance. For sample points on which only sample points are projected, the contents of the corresponding memory cells are set to "1". In this way, in the 45° direction, when 12 sample pulses have elapsed since the pulse was transmitted, the value of the X address counter 34A becomes 9.
Therefore, the X-axis address becomes _X9 .

Assume that in order to display a circular marker with a radius of 7, 7 is set on the distance setting device 28 (FIG. 6). At this time, the state of writing to the sub memory 31 in the 45° direction is shown in FIG. 11. That is, the write address changes sequentially as (X ₁ , Y ₁ ), (X ₂ , Y ₂ )... by the count pulse Pc,
Sampling pulse delayed by count pulse Pc
Pa is counted by a preset counter 27. 1
At the th count pulse Pc, the address is (X ₁ ,
Y ₁ ), the next second count pulse Pc
Then, the output "0" of the preset counter 27 is written to the address (X ₁ , Y ₁ ) of the sub memory 31. When the preset counter 27 counts 7, its output becomes "1". Therefore, "1" is written to the address (X ₆ , Y ₆ ) at the eighth count pulse Pc. However, at the next 8th counting pulse Pc, the outputs of the angle data memories 33A and 33B are "0" and the addresses remain (X ₆ , Y ₆ ), so at the next 8th sampling pulse Pa The output of the preset counter 27 becomes "0",
At the next 9th count pulse Pc, “0” is written to the address (X ₆ , Y ₆ ), and the previously written “1”
will be deleted. If an attempt is made to display a circular marker with a radius of 7 in this manner, the mark M will be missing at 45°, resulting in omission.

Similarly, θ=0°, θ=90°, θ=180°, θ=
At angles other than 270°, a situation occurs in which data from the preset counter 27 is written to the same address in the submemory 31 at least twice.

As a result, a situation occurs in which data is written twice to the same address, so that when a mark signal for displaying mark M is written to a certain address in the sub memory 31, the next data is written to this address. This will result in a phenomenon in which this happens. When this phenomenon occurs, the mark signal just written is erased by the next data, and the mark M is missing.

Even when displaying an image of a thin dotted line drawn in a direction intersecting the radiation direction by the received signal other than the mark M, this phenomenon also causes a problem in that part of the dotted line is missing and the image quality is degraded.

One possible method for solving this problem is to configure the image data to be written into the memory only when image data is generated during coordinate transformation and writing into the memory.

However, with this configuration, the image data previously written in the memory will not be erased. In other words, for example, the display radius R of cursor M
If you change the cursor, there will be an inconvenience that the original cursor will not disappear.

"Means for Solving Problems" This invention includes non-stepping detection means for detecting that the address of the coordinate conversion address generator constituting the coordinate conversion means has not stepped, and a non-stepping detection means for writing image data into a memory. writing detection means for detecting whether or not the
The apparatus is provided with means for inhibiting the operation of writing the next image data into the memory when these detection means simultaneously detect the respective conditions.

By providing each of these means, when image data is written into the memory, writing the next data to the address where the data was written is prohibited.

As a result, for example, when marks M to be displayed at equal angular intervals along a circle are written in the memory and then read out and displayed, the marks M will not be erased by the next data. Therefore, accidents such as part of the mark M missing will not occur.

Further, even when any curve expressed by a dotted line of minute dots other than the mark M is taken into the memory as image data and displayed, a part of the dotted line will not be displayed as missing.

Therefore, according to the present invention, a high quality image can be displayed.

"Embodiment" FIG. 1 shows an embodiment of the main part of the present invention. In the figure, parts corresponding to those in FIG. 6 are designated by the same reference numerals.

In this example, the present invention is applied to display a mark M at a position within an arbitrary radius R from the preset counter 27.

In other words, the angle data read from the angle data memories 33A and 33B are counted by the X address counter 34A and the Y address counter 34B, this counted value is given as a write address to the sub memory 31 through the selector 29, and the mark M is placed in the sub memory 31. The structure for writing data is the same as the conventional example explained in FIGS. 4 and 6.

In this invention, a non-step detection means 41 detects that the write address to the sub memory 31 has not changed, and a non-step detecting means 41 detects that the write address has not changed. It is characterized by a structure that includes a write detecting means 42 for detecting, and a means 43 for prohibiting writing to the secondary memory 31 when the non-step detecting means 41 and the write detecting means 42 detect their respective conditions simultaneously. It is something to do.

The non-stepping detection means 41 is, for example, a Noah gate 41A.
and a D-type flip-flop 41B. The readout outputs of the angle data memories 33A and 33B are applied to both input terminals of the NOR gate 41A. The output of the NOR gate 41A is applied to the clock terminal CK of the D-type flip-flop 41B.

The cathode signal output from the preset counter 27 is branched and inputted to the data input terminal D of the D-type flip-flop 41B.

The write detection circuit 42 can be constituted by, for example, one D-type flip-flop 42A.
A mark signal P _M (FIG. 2B) output from the preset counter 27 is applied to the data input terminal D of this D-type flip-flop 42A, and a non-step detection circuit 41 is configured to the clear terminal CLR of the D-type flip-flop 42A. flip-flop 41
Connect the output terminal of B. Further, a count pulse Pc shown in FIG. 2C is applied to the clock terminal CK of the D-type flip-flop 42A. At the rising edge of this count pulse Pc, the D-type flip-flop 42A reads the state of the output of the preset counter 27, that is, the presence or absence of image data.

The output terminal of this D-type flip-flop 42A is connected to one input terminal of a gate constituting write inhibiting means 43. A count pulse Pc is applied to the other input terminal of this gate via an inverter 44 as necessary. The output terminal of the write inhibit means 43 is connected to the write enable terminal of the sub memory 31.

₍ Operation Description) Signals _P When either of these angle data signals P _X or P _Y is output, these angle data signals
D-type flip-flop 41B reads the state of the output of preset counter 27 at each rising edge _{of P}

As shown in FIG. 2B, the output state of the preset counter 27 continues to output logic "0" until the mark signal P _M is output. Therefore, the output terminal of the D-type flip-flop 41B is
It continues to output "1" logic as shown in .

While the output terminal of the D-type flip-flop 41B continues to output the logic "1", the D-type flip-flop 42A constituting the write detection means 42 is maintained in an operating state. Yotsute count pulse Pc
The D-type flip-flop 42A reads the state of the output of the preset counter 27 at each rising edge. In other words, in order to continue reading the "0" logic state, the state of the output terminal of the D-type flip-flop 42A is the second state.
There is no change as shown in Figure G.

By the way, due to the rise of the angle data signals P _{X and} P _Y , the X and Y address counters 34A and 34
B increments the address, but the timing of incrementing the address is delayed from the timing of writing to the sub memory 31. Therefore, when the X and Y coordinate addresses obtained by outputting the angle data signals P _X and P _Y are written into the sub memory 31, the mark signal at that point in time is written at the rising edge of the next count pulse Pc.

Here, as shown at timing _T1 , the mark signal P _M is output from the preset counter 27, and the mark signal P _M is written in the sub memory 31 by _Ph1 (H in FIG. 2) output from the inhibiting means 43. Let's say it's loaded. At this time, if both angle data P _X and P _Y are not output, the X address counter 34A and Y
The address counter 34B does not increment at all, and the D-type flip-flop 4 constituting the non-increment detection means 41
The output terminal of 1B maintains the "1" logic, and the D-type flip-flop 42A constituting the write detection means 42
reads the mark signal P _M at the rising edge of the count pulse Pc at timing _T2 , so its output terminal falls to logic "0" as shown in FIG. 2G.

As a result, the gate constituting the write inhibiting means 43 is controlled to be closed, and writing to the sub memory 31 is inhibited at the rising edge of the count pulse Pc at the next timing _T3 , and the "1" logic is set at the previous timing _T2. This prevents a "0" logic signal from being written to the address where the "0" logic signal is written.

On the other hand, suppose that both the angle data signals P _X and P _Y are not output when the output of the preset counter 27 is in the logic "0" state as shown at timing T ₅ in FIG. In this case as well, the secondary memory 31
The write address of is not incremented. In other words, the angle data signals P _X , P _Y output at timing T ₄
The state remains stopped at the address incremented by .

At this time, "0" logic is written to the sub memory ₃₁ at timing T ₅ , and _{Ph 2 ( second}
At the rising edge of FIG. H), logic "1" is written to the same address in the sub memory 31.

At this timing _T7 , the angle data signal _PX ,
The mark signal P _M is detected by the non-step detection means 41 by P _Y.
B, and the output terminal becomes "0" logic.
As a result, the write detection means 42A is reset, its output terminal maintains the logic "1", and writing to the sub memory 31 is not inhibited, and the angle data signals P _X and P _Y output at timing _T7 A logic "0" is written to the incremented coordinate address at the rising edge of timing _T8 . Timing like this
In the state of _T8 , the mark signal P _M written at timing _T7 is incremented from the address where "1" logic was written at the previous timing _T7 to the next address.
will never be deleted.

Although the case where the mark signal P _M is written has been described above, the receiving signal system output from the receiver 13 may also be configured to perform similar processing. If the received signal is subjected to similar processing, there will be no omission of various lines represented by dotted lines on the screen. As a result, a high quality image can be projected.

In short, when image data is AD converted and loaded into memory at a cycle shorter than the address step cycle, by providing the structure according to the present invention, it is possible to prevent image data that only exists for a period shorter than the address step cycle from being omitted. It can be loaded into memory.

"Modified Embodiment" FIG. 3 shows another embodiment of the present invention. This example shows a case in which a write prohibition means 43 constituted by an OR gate is provided in the supply path of the mark signal P _M so that logic "1" is forcibly written during non-stepping.

In other words, in this example, even if "0" logic data is input next to "1" logic data, instead of writing that "0" logic data, it is taken into the write detection means 42 at the previous timing. This is a case where data of logic "1" is written and data of logic "0" is prohibited from being written to that address.

For this purpose, the output of the output terminal Q of the D-type flip-flop 42A constituting the write detecting means 42 is applied to one input terminal of the OR gate constituting the write inhibiting means 43. This write inhibit means 43 has a second
A signal whose polarity is opposite to that shown in FIG. G is applied.
When the mark signal P _M is written, if the X and Y addresses that generate the next coordinate address do not increment, the output terminal Q of the write detection means 42A
``1'' logic is output, and at the next timing, ``1'' logic is written to the same address. This makes it possible to prohibit the mark signal P _M from being erased even if the address is not incremented.

"Effects of the Invention" As explained above, according to the present invention, when converting from polar coordinates to orthogonal coordinates, writing is performed two or more times to the same address in the memory where image data converted to orthogonal coordinates is written. Even if this phenomenon occurs, if image data is written during the first writing, the next writing will be prohibited. Therefore, the image data once written will not be erased.

Therefore, according to the present invention, when a mark M representing a distance is drawn on the display surface, for example, a part of the mark M will not be missing. Furthermore, when a similar signal processing function is added to the receiving signal system, images that should be drawn as dotted lines will not be missing in some places. Therefore, an advantage is obtained that high-quality images can be obtained no matter which system it is applied to.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining an example of the main part of this invention, FIG. 2 is a waveform diagram for explaining the operation of this invention, and FIG. 3 is a block diagram showing another embodiment of this invention. , FIG. 4 is a block diagram for explaining the overall configuration of a radar equipped with conventional coordinate conversion means, FIG. 5 is a front view for explaining the cursor displayed on the radar display, and FIG. 6 is a front view for explaining the cursor displayed on the radar display. 7 is a block diagram for explaining the structure of a conventional cursor signal generator, FIG. 7 is a diagram for explaining the storage area in the angle data memory, and FIG. 8 is a diagram for explaining the storage area in the angle data memory. Figure 9 is a waveform diagram to explain an example, Figure 9 is a schematic diagram to explain the writing operation to the memory that stores image data after coordinate transformation, Figure 10 is a sample point in the 45° direction, and 0°.
Figure 11 shows the contents of the memories 33A and 33B projected at 45 degrees and the contents of the memories 33A and 33B projected at 90 degrees. This is a time chart. 11... Transmitter, 12... Antenna, 13...
Receiver, 14...AD converter, 15...Buffer memory, 16...Scanning display, 17...Main memory, 17B...Sub memory, 18A, 18B...Color converter, 19...Motor, 21 ... Angle pulse generator, 22A, 22B ... Coordinate conversion address generator, 23, 29 ... Address selector, 24
... Read address generator, 25 ... Clock source, 26 ... Cursor signal generator, 27 ... Preset counter, 28 ... Distance setter, 31 ...
Secondary memory, 32... Gate, 33A, 33B...
Angle data memory, 34A, 34B...X and Y
Address generator, 35A, 35B...Address counter, 36...Angle indicator, 41...Non-step detection means, 42...Writing detection means, 43...Writing inhibiting means.

Claims (1)

[Claims] 1A A coordinate conversion address generator that emits a wave pulse, receives its reflected wave, converts this received signal into a digital signal with an AD converter, and converts the digital signal into a coordinate conversion means. an echo that stores in a memory according to an address signal from the above, reads out the memory in synchronization with the scanning of the scanning display, and supplies the read signal as a display signal to the scanning display to display it as an image. In the detection device, B non-step detection means detects that the address of the coordinate conversion address generator does not step; C. when the non-step detection means detects that there is no change in the address, the address write detection means for detecting that image data has been written to D; an echo detection device comprising: means for prohibiting writing of next image data into memory in a state where both conditions of detecting the echo are matched;