JPH0377905A - Multipoint synchronous optical writing device - Google Patents

Abstract

PURPOSE:To obtain images having good dot position accuracy without being affected by a change in environmental temp. in spite of such change by detecting change component of the phase error of the writing start signal in a main scanning direction and a picture element clock, forming the reference pulse varied in duty ratio according to this change component and supplying the pulse to a PLL circuit, thereby compensating the change component of the phase error. CONSTITUTION:A phase error detecting circuit 16 which detects the change component of the phase error of the writing start signal in the main scanning directing and the picture element clock is provided and a reference pulse forming circuit 17 which forms the reference pulse varied in the duty ratio according to this change component of the detected phase error is provided. The reference pulse varied in the duty ratio is formed and is applied to the phase comparator in the PLL circuit to operate the PLL circuit 11 so as to compensate the change component of the phase error between the reference pulse and the picture element clock. The images having the good dot position accuracy are obtd. in this way without being influenced by the change in the environmental temp. in spite of such change.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multi-point synchronous optical writing device used in high-quality laser printers and the like.

2. Description of the Related Art Generally, in an optical writing device such as a laser printer, a laser light source is modulated according to image information and scanned by a deflector such as a polygon mirror to perform optical writing on a photoreceptor or the like. At this time, it is difficult to drive a polygon mirror or the like to rotate it at a constant speed, and in reality, speed variations occur, resulting in deviations in the writing dot positions. Therefore,
In order to perform good optical writing with a constant writing dot interval, a multi-point synchronous optical writing device using a linear encoder having a large number of slits is proposed, for example, in U.S. Pat.
It is known from the specification of No. 389,403.

Japanese Patent Laid-Open No. 54-97050 discloses a linear encoder that has been improved to facilitate manufacturing of the linear encoder. In this system, a photoelectric pulse signal obtained from a linear encoder is multiplied by n to obtain a video clock (pixel clock). Specifically, the photoelectric pulse obtained by the linear encoder is
The phase comparator of the L circuit compares it with the reference pulse, and the voltage control m oscillator is feedback-controlled so that the two match, and the P
The LL circuit outputs a clock signal, which is synchronized with the photoelectric pulse and multiplied by n, as a pixel clock, which is a synchronization signal for modulating the semiconductor laser.

By the way, since the PLL circuit has a substantially constant response delay depending on the circuit configuration, etc., even if a photoelectric pulse is generated, its phase does not immediately align with the phase of the reference pulse. Therefore, in the above publication, the gate is opened and a write start signal is output after the time required for the photoelectric pulse and the reference pulse to align in phase (=lock-up time) has elapsed and the phases have aligned. Therefore, the pixel clock is set as the pixel clock. By modulating the semiconductor laser in synchronization with such a pixel clock, it is possible to record at the correct position where the starting point of the effective scanning line (ie, the first dot position) is aligned in the vertical direction. Here, the shorter the lock-up time, the longer the effective scanning line becomes, which is convenient for obtaining high resolution. In this regard, in the above publication, the frequency divider is reset by the first photoelectric pulse of the scanning line, and the phases of the photoelectric pulse and the reference pulse are forcibly matched to reduce the amount of phase correction, thereby preventing lock-up. I'm trying to save time.

Problem to be Solved by the Invention However, according to the method disclosed in the above publication, dots can always be recorded at the correct position only under a constant temperature.

Generally, when the environmental temperature of a PLL circuit changes, even when locked, the phase error between the reference pulse that is its input and its feedback signal PLII, a clock obtained by dividing the Q output, also changes. Therefore, even if you adjust the phase difference between the write start signal (synchronized with the reference clock) and the write clock (pixel clock) at room temperature, a phase shift will occur as the temperature changes, and in the worst case, the image This appears as a misaligned recording dot on the top. In other words, in the past, no measures have been taken against changes in phase error due to temperature changes.

Means for Solving the Problem A synchronous beam is used in addition to the writing beam, and a PLL circuit generates a pixel clock that is phase-synchronized with a reference pulse generated over the entire main scanning direction based on the synchronous beam. In a multi-point synchronous optical writing device that performs optical writing by modulating a laser light source for a writing beam using image information synchronized with image information, a change in phase error between a writing start signal in a main scanning direction and the pixel clock is detected. A phase error detection circuit was provided, and a reference pulse generation circuit was provided for generating a reference pulse with a variable duty ratio according to a change in the detected phase error.

When a change occurs in the phase error between the write start signal and the pixel clock due to a change in operating environment temperature, the change is detected by the phase error detection circuit.

The reference pulse generation circuit generates a reference pulse with a variable duty ratio corresponding to the change in the phase error detected in this way, and supplies it to the phase comparator in the PLL circuit.
A PLL circuit operates to compensate for changes in phase error between the reference pulse and the pixel clock. Here, the write start signal is synchronized with the reference pulse, and the above compensation operation also compensates for a change in phase error between the write start signal and the pixel clock. Therefore, even if the environmental temperature changes, it will not be affected, and an image with good dot position accuracy can be obtained.

Example An embodiment of the present invention will be described based on the drawings.

First, an outline of a laser printer to which the present invention is applied will be explained with reference to FIG. This is, for example, JP-A-60-109
As shown in Japanese Patent No. 667, etc., this is a multi-point synchronization system in which a pixel clock is generated using a grating (also referred to as a slit, grid, or scale).

A semiconductor laser (laser light source) for writing is provided which emits a writing beam P modulated by image information. This writing beam P is deflected by one surface of a rotating polygon mirror 2, passes through an fθ lens 3, is reflected by a mirror 4, and is imaged on a photoreceptor 5, and is subjected to recording scanning as shown by a scanning line 6. will be carried out. On the other hand, a semiconductor laser 7 for generating a pixel clock is also provided in addition to the semiconductor laser 1 for writing. The synchronized beam P3 emitted from the semiconductor laser 7 is incident on the same reflective surface of the polygon mirror 2 at a position separated from the writing beam P by a certain distance (the same position in the main scanning direction), and is similar to the writing beam P. is incident on the fθ lens 3.

After passing through the fθ lens 3, the synchronized beam P passes over a mirror 4 due to the difference in its upper and lower positions, and scans a grating 8 positioned at an optically equivalent position to the photoreceptor 5. The synchronizing beam P transmitted through the transparent portion of the grating 8 is sequentially condensed and imaged by a lens array 9 onto a plurality of, for example, four, light receiving elements 10a to 10d, and the charge obtained from these light receiving elements 10a to 10d is sequentially focused. The reference pulse Sr made by converting the conversion output into a binary pulse is a PLL circuit! ■
Occurs against. More specifically, the light-receiving signals received by the light-receiving element 10 and subjected to photoelectric conversion are each amplified, then subjected to addition processing by an adder circuit, and then binarized using a predetermined threshold voltage. This results in a pulse train signal that spans the entire scan length in the main scanning direction according to the bright and dark arrangement of the grating 8, and after waveform shaping as necessary, the PLL circuit 11 generates and outputs the pixel clock WcLK obtained by multiplying the reference pulse Sr by n. be done.

As is well known, the PLL circuit 11 includes a phase comparator (
A PD) 12, a low pass filter (LPF) 13, a voltage controlled oscillator (VCO) 14, and a 1/N frequency divider 15 are connected in a loop. That is, the phase comparator 12 outputs a pulse corresponding to the phase difference between the reference pulse Sr and the feedback pulse sb which is fed back by multiplying the feedback output of the voltage controlled oscillator 14 by N by the 1/N frequency divider 15. 3), the pulse is smoothed by a low-pass filter 13, and the voltage-controlled oscillator 1
The control voltage υ of 4 is assumed to be υ. The voltage controlled oscillator 14 controls the feedback pulse sb obtained by frequency-dividing its output by N to be in phase synchronization with the reference pulse Sr, and outputs the pixel clock WcLK to the drive circuit of the semiconductor laser l.

That is, in the PLL circuit 11, as shown in FIG. 3, when the phase error between the reference pulse Sr and the feedback pulse sb changes, the control voltage for the voltage controlled oscillator 14 also changes.
Operates to suppress changes in phase error. Therefore, in this embodiment, by adding phase error change compensation as described below, changes in the phase error between the write start signal and the pixel clock WCLK due to environmental temperature changes can be compensated for by using the reference pulse Sr.
In other words, changing the duty ratio of phase comparator 1
By changing the output pulse width of 2, the control voltage applied to the voltage controlled oscillator 14 is changed and suppressed.

Therefore, the phase error change compensation circuit added to the PLL circuit 11 will be explained. This circuit roughly consists of a phase error detection circuit 16 and a reference pulse generation circuit 17. The phase error detection circuit 16 uses a write start signal L Gate in the main scanning direction synchronized with the reference pulse Sr and a pixel clock Wc.
This is to detect the change in phase error with respect to LK. First, a counter 18 is provided which is cleared when the write start signal L Gate falls. Also, a pixel clock W from the voltage controlled oscillator 14. Gate is input to the clock terminal and the write start signal L is input to the D terminal.
A flip-flop 19 is provided. The Q output of this D flip-flop 19 is the write start signal L Gate.
This signal is also input to the AND gate 20, and the counter 18 is enabled for a period corresponding to the phase difference between the write start signal LGate and the rising edge of the pixel clock wcLK. This counter 18 counts and holds the number of oscillation pulses input from the oscillator 21 while in the enabled state. A D/A converter 22 that converts the counted value into an analog value is connected to the output side of the counter 18. On the output side of the D/A converter 22, there is a current-voltage conversion circuit (1) that generates an analog value, that is, a voltage corresponding to the phase difference between the write start signal L Gate and the rising edge of the pixel clock Wc, as a control voltage υp.
-V) 23 is connected. These counters 18,
Flip-flop 19, AND gate 20, oscillator 21
, a phase error detection circuit 16 that detects a change in phase error using the D/A converter 22 and the current-voltage conversion circuit 23.
is configured.

Further, on the output side of this current-voltage conversion circuit 23, there is an integrating circuit 24 for smoothing the control voltage υp into a control voltage υ.
is connected. This integration circuit 24 outputs the write start signal L_Crate for a time T. It has a longer time constant than the blanking time T1 corresponding to
(see figure). Next, the reference pulse generating circuit 17 connected to the integrating circuit 24 generates a reference pulse Sr with a variable duty ratio corresponding to the control voltage υ from the photoelectric conversion output obtained from the light receiving element 10 side. This signal is input to the phase comparator 12 in the PLL circuit 11. More specifically, the threshold voltage T for binary pulse generation of the reference pulse generation circuit 24 is determined according to the control voltage υ1.
This is to make h variable.

In such a configuration, first, when the PLL circuit 11 is locked at room temperature, the phase difference between the write start signal L Gat6 and the rising edge of the pixel clock WcLK is 180' (=pixel clock Wc, The gain and threshold voltage Th of the PLL circuit 11 are adjusted so that the output voltage is a half clock). Specifically, the pulse width of the enable signal at this time is We + the threshold voltage is Th, and the reference pulse is Sr.

Then, in the actual write operation, the write start signal L
The counter 18, which is cleared by the falling edge of Gate, is enabled by the rising edge of the write start signal L Gate, and counts the number of oscillation pulses of the oscillator 21.

This counting operation is performed immediately after the pixel clock W. Stop at the rising edge of LK and write the count value to start signal L Gate.
Hold until falls.

Therefore, the count value in the counter 18 is the write start signal L Gate and the pixel clock W. This corresponds to the phase difference with the rising edge of LK, and after being converted into an analog value by the D/A converter 22, the current-voltage conversion circuit 23 generates the control voltage υp. This control voltage υp is smoothed by the integrating circuit 24 and the control voltage υ1
becomes. The threshold voltage Th of the reference pulse generation circuit 17 is varied according to this control voltage υ1. If the pulse width of the enable signal remains W, the threshold voltage Th also remains Th, and the reference pulse becomes Sr, as shown in FIG.

In such an operation, the write start signal LG ate
and pixel clock W. The phase difference with the rising edge of LK becomes larger than that at room temperature (180') due to environmental temperature changes, and as shown in FIG. 4, the enable period (phase difference) becomes W,
When (W, > W,), the count value of the counter 18 becomes large, and the generated control voltage υp also becomes larger than at room temperature. This control voltage υp is the write start signal L
When Gate falls, it is cleared to 0 as shown in FIG. It is maintained until the rise of . Therefore, the threshold voltage Th of the reference pulse generation circuit 17 is varied from Th to Th, (Th, )Th, ) based on this control voltage υ1.

As a result, the reference pulse Sr input to the PLL circuit 11
becomes like Sr shown in FIG. 5, and has a different duty ratio from the reference pulse Sr at room temperature. Therefore, the PLL circuit 11 operates based on the principle explained based on FIG. 3 etc. so that the phases of the reference pulse Sr and the feedback pulse sb are aligned. Here, write start signal L Gat
e is synchronized with the reference pulse Sr, and the pixel clock W
CLK corresponds in phase to the feedback pulse sb, and the pulse width W corresponding to the phase error is returned to W by the operation of the PLL circuit 11, thereby suppressing changes in the phase error. On the other hand, the phase difference between the write start signal L Gate and the rise of the pixel clock WCL is smaller than that at room temperature, and as shown in FIG.
When becomes like Wl, the count value of the counter 18 becomes small, and the generated control voltage υp also becomes smaller than at room temperature. Therefore, the threshold voltage Th of the reference pulse generation circuit 17 is varied from Th to Th, (Th,<Th,) based on the control voltage υ1 obtained by integrating this. As a result, the reference pulse Sr input to the PLL circuit 11 becomes like Sr shown in FIG. 5, which also has a different duty ratio from the reference pulse Sr at room temperature. Therefore, as in the above case, the PLL circuit 11
It operates to return the pulse width W, which corresponds to the phase error, to W, thereby suppressing changes in the phase error.

In such a compensation operation, the width of change in the duty ratio of the reference pulse Sr is extremely small, and the threshold voltage Th also changes gradually, so that the PLL circuit 11 does not come out of the locked state. Furthermore, since the reference pulse Sr corresponds to the pixel clock WcLK divided by N, even if the duty ratio of the reference pulse Sr changes very slightly, the phase fluctuation width of the pixel clock WcLK can be increased.

Further, the method of varying the duty ratio of the reference pulse Sr input to the phase comparator 12 is not limited to varying the threshold voltage Th, and for example, the ° control signal υp
may be fed back to the drive circuit of the semiconductor laser 7 that generates the synchronous beam P, and the emission power of the semiconductor laser 7 may be varied in accordance with the control signal υp. The luminous power at the initial stage at room temperature is PW, and this is PW.
,, When PWl is changed as shown in FIG.
When converted into a binary pulse by h, the reference pulse Sr becomes Sr, , Sr, , Sr shown in FIG. 5, and the duty ratio changes.

Effects of the Invention As described above, the present invention includes a phase error detection circuit that detects a change in phase error between a write start signal in the main scanning direction and a pixel clock, and detects a reference pulse according to the change in phase error. Since the generation circuit generates a reference pulse with a variable duty ratio, even if the phase error between the write start signal and the pixel clock changes due to changes in the environmental temperature, the PLL circuit will still be able to generate the reference pulse with a variable duty ratio. Since it operates to compensate for the change in the phase error between the pixel clock and the write start signal synchronized with the reference pulse, the change in the phase error between the pixel clock and the write start signal synchronized with the reference pulse is also compensated. Therefore, even if the environmental temperature changes, it will not be affected, and an image with good dot position accuracy can be obtained.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention; Fig. 1 is a block diagram, Fig. 2 is a perspective view showing an example of a laser printer, Fig. 3 is a timing chart showing the operation of a phase comparator, and Fig. 4 is a diagram. FIG. 5 is a timing chart showing reference pulse generation, and FIG. 6 is a waveform chart showing a modified example. 1... Laser light source, 11... PLL circuit, 16...
- Phase error detection circuit, 17... reference pulse generation circuit,
Pl...Writing beam, P,...Synchronization beam, Sr
...Reference pulse, L Gate...Write start signal, WcL...Pixel clock! CLK, % is missing 3 Figure

Claims (1)

[Claims] A synchronized beam is used in addition to the writing beam, and a PLL circuit generates a pixel clock that is phase-synchronized with a reference pulse generated over the entire main scanning direction based on this synchronized beam, and image information synchronized with this pixel clock is used for writing. In a multi-point synchronous optical writing device that performs optical writing by modulating a beam laser light source, a phase error detection circuit is provided to detect a change in phase error between a write start signal in a main scanning direction and the pixel clock, A multi-point synchronous optical writing device comprising a reference pulse generation circuit that generates a reference pulse whose duty ratio is varied according to a change in a detected phase error.