JPH0376612B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to code error control suitable for coded teletext broadcasting in which character and graphic information coded as digital signals are multiplexed transmitted during the vertical retrace period of a TV signal, and in particular to code error control that occurs in a transmission path. This relates to an error correction decoding system that attempts to recover as much as possible by correcting bit errors. Conventionally, this type of service using TV transmission channels has an error correction function using Hamming encoding of important codes such as program numbers in European and American teletexts,
The error detection function was limited to the parity bit of the character code. In addition, some Japanese character code broadcasting experimental systems that have already been announced,
Two extended Hamming codes H that correct 1-bit error in 1 block (8 bits or 16 bits)
(8,4)H(16,11) is often used. Such a system is suitable for a line with excellent transmission characteristics with few bit errors, but it is suitable for lines with a lot of impulse noise and bit errors of several bits in one block, or with poor transmission path characteristics and a high bit error rate. For those with only about 10 ^-2 , there was a drawback that they could not perform a sufficient error correction function. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an error correction decoding system that can eliminate the above-mentioned drawbacks and exhibit a sufficient error correction function. Another object of the invention is to eliminate the above-mentioned drawbacks and
The (273, 191) majority vote code was selected as an error correction code suitable for error control in coded teletext broadcasting, in which character and graphic information encoded as digital signals are multiplexed and transmitted during the vertical retrace period of a TV signal. The object of the present invention is to provide an error correction decoding system capable of correcting errors of multiple bits by appropriately decoding a majority code. In order to achieve this object, the present invention extracts 27 data bits from the majority difference set cyclic code.
3. Using a signal with 191 information bits and 82 parity bits, subtract 1 bit from this signal so that one packet consists of 272 bits to form a data signal with 272 data bits, 190 information bits, and 82 parity bits. transmit,
All predetermined columns are 1 in the transmitted data signal.
By multiplying by the matrix of , the error correction probability is increased and the information can be decoded. The present invention will be described in detail below with reference to the drawings. First, we will discuss the nature of error bits in the TV transmission path. FIG. 1 shows the average value of the distribution of the number of error bits in error bytes (8 bits) at a point where there is a relatively large amount of impulse noise when a data signal is actually transmitted and received in a field experiment. 1
The bit error is 82%, and H(8,4) is capable of correcting 1 bit error out of 8 bits and detecting 2 bit errors.
It can be seen that with the extended Hamming code, the correction effect does not reach up to one digit. Furthermore, FIG. 2 shows the same distribution when the transmitted signal is in an interleaved arrangement and the received signal is in a deinterleaved arrangement, and the 1-bit error is about 97.1%. In this case, the correction effect does not reach two digits. Moreover, the efficiency is low in both the standard arrangement and the interleaved arrangement.
There is a drawback that it only accounts for 50%. Of course, for the H(16,11) extended Hamming code, which can correct one bit out of 16 bits and detect two errors, the efficiency is 68.7%, which is improved compared to H(8,4).
There is no improvement in block error rate. Next, when we look at the distribution of the number of error bits in one packet, as shown in Figure 3, in the impulse region, errors of 1 to 8 bits account for 99.1%, and in the waveform distortion region shown in Figure 4, errors of 1 to 8 bits account for 99.1%. Then everything is 1~
There is an 8-bit error. In addition, the distribution of the error burst length (meaning the bit length from the start to the end of an error, regardless of whether the intermediate bits are correct or incorrect) in one packet is shown in Figures 5 and 5 for the impulse region and waveform distortion region, respectively. It is shown in FIG. Even if a code capable of correcting 68-bit burst errors is used, in the impulse region, the improvement is about 92% by one order of magnitude (Figure 5), and in the waveform distortion region, the improvement is about 92% (Figure 5).
75% of cases do not reach a single-digit improvement (Figure 6). Therefore, many effects cannot be expected from simple burst error correction codes such as interleaving of shortened cyclic codes. Figures 7 and 8 show b/n in typical impulse region and waveform distortion region, respectively.
This figure shows the cumulative distribution of the frequency ratio of error blocks with respect to (n: length of 1 block, b: number of error bits in 1 block). It can be seen from both figures that it is more advantageous to make the correction by increasing the block length. That is, in FIG. 7, the block length is n
= 8, in order to correct all error blocks, b/n = 0.7, or 6 out of 8 bits.
Errors up to the bit must be corrected. It is simply impossible to achieve this while maintaining a certain degree of efficiency. However, block length n
=272 (the length of one packet of character code broadcasting), all errors can be corrected with b/n = approximately 0.04. From Figure 8, n=
272, all errors can be corrected with b/n=0.03. From the above, it can be seen that correcting one packet as one block by making the block length as long as possible is advantageous in terms of correction ability, and is also practical. Typical error correction codes were evaluated for their correction ability, efficiency, ease of algorithm, simultaneous error correction and detection function, suitability for packet signals, etc., taking into account the characteristics of bit errors in TV transmission channels as described above. 4
A comparison of types is shown in Table 1 below.

[Table] ○: Good △: Average ×: Bad As can be seen from Table 1, the majority voting code obtained an average score with few defects across all codes, and is most suitable for error control in character code broadcasting. . Many majority voting codes have been discovered so far, but considering compatibility with pattern-based teletext broadcasting, (1 packet = 272 bits) the (273, 191) code, which is a difference set cyclic code, has been shortened by 1 bit. (272, 190) bits is optimal for Japanese character code broadcasting. The efficiency of this code is R = 190/270 = 0.70, and the error correction ability can correct 8 bits of random errors in one packet, and from Figures 3 and 4, in the impulse area, it is 99.1%, 100% error correction effect can be expected in waveform distortion areas.
Therefore, in the present invention, such symbols are used. The principle of this code will be explained below. First, the majority code will be explained. As the simplest example, consider an M-sequence code with a code length of 7 and a number of information points of 3. The parity check matrix H of this code is given by [1011000 1110100 H=1100010 0110001]. If the vector e representing noise is e=(e ₀ , e ₁ . . . e ₆ ) and the syndrome S is S=(S ₀ , S ₁ , S ₂ , S ₃ ), then S=He ^t . Here, t represents transposition. Determining the composite parity check A ₁ , A ₂ , _{A 3 consisting} of S ₁ , S ₂ and S ₁ +S 3, A ₁ = S ₀ = e ₀ + e ₂ + e ₃ A ₂ = S ₃ = e ₀ + e ₁ + e ₅ A ₃ = S ₁ + S ₂ = e ₀ + e ₄ + e ₆ are obtained. Here, e ₀ is included in all of A ₁ , A ₂ , and A ₃ , and only one of the other e ₁ to e ₆ is included in A ₁ , A ₂ , and A ₃ . At this time, A ₁ , A ₂ , A ₃ are
They are said to be orthogonal with respect to e ₀ . Among e ₀ to e ₆ ,
If there is an error in e ₀ , A ₁ =A ₂ =A ₃ =1.
If there is an error in other e ₀ to e ₆ , A ₁ , A ₂ ,
Any one of A ₃ is 1. Therefore,
By setting the threshold value to 2 among A ₁ , A ₂ , and A ₃ , the output of the majority circuit can correct the error bit e ₀ . Since the M-sequence code is a cyclic code, if the above operation is repeated seven times, it is possible to correct a one-bit error out of seven bits. FIG. 9 shows an actual hardware configuration of an error correction circuit that performs error correction in the above example. Here, 100
is a 7-bit input signal. All initial values of the syndrome register 101 are set to "0". 102 is a buffer register for temporarily storing input data 100. input signal 10
The same data 100 is also loaded into the syndrome register 101 until all zeros are completely in the buffer register 102. Until this time, the majority circuit 109 is not operating. 103-107 is 2
It is an adder modulo . When all 7 bits of data have completely entered registers 101 and 102, error correction operation begins. That is, the majority circuit 10
9 starts operating. When two or 32 of the three inputs 111, 112, and 113 to the majority circuit 109 are "1", the majority output is 1.
14 becomes "1", and the adder 107 corrects the error bit. At the same time, in order to eliminate the influence of the error bit on the syndrome, the syndrome register 101 is modified by the majority output 114. This operation determines whether error correction has been performed completely correctly. That is, if error correction has been performed correctly at the end of the correction operation for all bits, all of the syndrome registers 101 should have become "0". At this time, syndrome register 10
If all bits of 1 are not "0", it may be determined that correct error correction has not been performed.
The generating polynomial in this example is G(x)=x ⁴ +x ² +x+1, which corresponds to bit x ⁷ at the time when an error occurs in the first bit of buffer register 102 and a correction operation is performed. Therefore, the influence of x ⁷ on the syndrome register 101 is {x ⁷ /G(x)}=1, and a syndrome correction bit based on the majority output 114 is required. However, the above formula { } represents the coset. Next, an example of actually transmitting data will be described. Since the generation matrix is [1001011 G=0101110 0010111], the code c for 3-bit information 001 is c=(001)G=0010111. If this code is transmitted without error,
The syndrome on the receiving side will be 0000. If we follow the changes in the bits in the syndrome register 101, the syndrome register 101 becomes 0000: 0100 Load 4 bits from the beginning 1010 Load 5 bits from the beginning 1101 Load 6 bits from the beginning 0000 Load 7 bits from the beginning , all information is output from the output terminal 110 without errors. Next, let's examine the case where there is an error in the second bit. In this case, the received data is 0110111
becomes. Therefore, the syndrome S(x) is as follows: S(x)={x ⁵ +x ⁴ +x ² +x+1/G(x)} =x ³ +x ² +x. The contents of the syndrome register 101 are 0111. When we consider the corrective action,

[Table], and the error in the second bit can be corrected. Next, the basis for selecting the (273, 191) majority code in the present invention will be described. Majority codes known so far include maximum length sequence codes, Hamming codes, Euclidean geometry codes, finite projective geometry codes, and difference set cyclic codes. Among these, maximum length sequence codes, Hamming codes, and Euclidean geometric codes all have a code length n of 2 ^m −1,
To make one packet one block, m=9, n
= 511, and this code is 239 until n = 272.
It must be shortened by one bit. However, due to the shortening, the transmission efficiency is extremely reduced. Also,
The finite projective geometry code is n=(2 ^ms −1)/(2 ^s −
1), but by shortening the code, it is possible to correct errors of up to 8 bits in one packet, and the efficiency is 190/272.
There is nothing more to be gained. (273, 191) The majority code is obtained from the difference set cyclic code, and is 0, 18, 24, 46, 50, 64,
103, 112, 115, 126, 128, 159, 166, 167, 186,
It takes advantage of the fact that the differences between all the integers 196 and 201 are different from each other, and that they appear only once in all numbers 1 to 272, modulo n=273. The generating polynomial of this code is G(x)=x ⁸² +x ⁷⁷ +x ⁷⁶ +x ⁷¹ +x ⁶⁷ +x ⁶⁶ +x ⁵⁶ +
x ⁵² +x ⁴⁸ +x ⁴⁰ +x ³⁶ +x ³⁴ +x ²⁴ +x ²² +x ¹⁸ +x ¹⁰ +x ⁴ +1
...(1) Also, the input A ₁ to the majority circuit
A ₁₇ is A ₁ = S ₁₀ + S ₅ A ₂ = S ₆₄ A ₃ = S ₇₆ + S ₅₈ A ₄ = S ₆₀ + S ₅₄ + S ₃₆ A ₅ = S ₇₈ + S ₅₆ + S ₅₀ + S ₃₂ A ₆ = S ₆₅ + S ₆₁ +S ₃₉ +S ₃₃ +S ₁₅ A ₇ =S ₄₆ +S ₂₉ +S ₂₅ +S ₃ A ₈ =S ₇₃ +S ₃₇ +S ₂₀ +S ₁₆ A ₉ =S ₇₉ +S ₇₀ +S ₃₄ +S ₁₇ +S ₁₃ A ₁₀ =S ₇₁ +S ₆₈ +S ₅₉ +S ₂₃ +S ₆ +S ₂ A ₁₁ =S ₈₀ +S ₆₉ +S ₆₆ +S ₅₇ +S ₂₁ +S ₄ +S ₀ A ₁₂ =S ₅₁ +S ₄₉ +S ₃₈ +S ₃₅ +S ₂₆ A ₁₃ =S ₇₅ +S ₄₄ +S ₄₂ +S ₃₁ + S ₂₈ +S ₁₉ A ₁₄ =S ₈₁ +S ₇₄ +S ₄₃ +S ₄₁ +S ₃₀ +S ₂₇ +S ₁₈ A ₁₅ =S ₆₃ +S ₆₂ +S ₅₅ +S ₂₄ +S ₂₂ +S ₁₁ +S ₈ A ₁₆ =S ₇₂ +S ₅₃ +S ₅₂ +S ₄₅ + S ₁₄ + S ₁₂ +S ₁ A ₁₇ = S ₇₇ + S ₆₇ + S ₄₈ + S ₄₇ + S ₄₀ + S ₉ + S ₇ . Next, in carrying out the present invention, a signal sending circuit on the sending side is shown in FIG. Here 200 is
Represents 190 bits. That is, this information bit 200 is shortened by one bit from the original code, so that the information part becomes 190 bits. The initial value of all 82 bits of parity register 201 is "0". Switches 202, 203 and 2
04 is initially at the position on the solid line side. The information bit 200 passes through the switch 204 and becomes the outgoing packet signal 205 as it is. At the same time, this information bit 200 passes through switches 203 and 202 and further through adder 206 to generate a parity bit. The generation method is based on G(x) in equation (1). All information bit 2
Parity register 201 after 00 is sent out
The content of is the parity bit to be added to the previous information. Therefore, from that point on, switch 20
2, 203, and 204 are switched to the positions on the broken line side, and the signal in the parity register 201 is output as the sending packet signal 205. In this way, one packet of signals 272, 190 is output in the order of information bits and parity bits. Next, FIG. 11 shows an example of a decoding circuit according to the present invention for signals sent out in this manner. Here, 300 is the input signal to be error corrected, which is the received signal, but there is "0" at the beginning of the data.
1 bit is added and shortened on the sending side. Therefore, the total is 273 bits. The rest of the configuration is basically the same as the example explained in FIG. 9. A data register 301 stores data to be corrected, and 273 bits are reserved. 302 is a syndrome register consisting of an 82-bit shift register.
Further, 303 to 323 are adders modulo 2, which generate input signals to the majority circuit 341.
The numbers input to adders 307-323 represent the output of the register number of syndrome register 302. For example, inputs 5, 10 of adder 307
is the register stage of the syndrome register 302
Represents the output of S ₅ and S ₁₀ . Adder 3 modulo 2
The outputs 324 to 340 of 07 to 323 are supplied to a majority circuit 341, and the majority outputs, that is, the correction signal 342 and the output of the register 301, are supplied to a modulo-2 adder 343. The initial values of the syndrome register 302 are all
Let S ₀ =0,..., S ₈₁ =0. Majority circuit 341 does not operate until all bits of signal 300 have been written to data register 301. When all the data has entered the data register 301, the first row is set by the register stages _S0 to _S81 , and the majority circuit 341 operates at a threshold value of 9.
Starts error correction of the first bit. Each time the syndrome calculation advances by 1 bit, error correction is performed and the data register 301 is incremented by 1 bit, and the adder 343 corrects the output of the register 301 with a correction signal 342, and outputs error-corrected data 344. . The decoding circuit described above has a general configuration showing the decoding procedure, but the first example shows a specific circuit configuration when used in an actual character code broadcasting receiver.
Shown in Figure 2. Here, 400 is the CPU bus line,
401 is a 16-bit output port from the CPU (not shown), 402 is a 16-bit input port from the CPU,
403 is an 82-bit syndrome register with a feedback function, 404 is a data register,
405 is a majority decision circuit including 17 majority decision input circuits, 406 is a 16-bit parallel-serial conversion circuit for output, 407 is a 16-bit serial-parallel conversion circuit for input, 408 is a 16-bit pulse generation circuit, and 409 is a load/collect gate. A generation circuit, 410 a gate circuit, 411 a ready signal generation circuit, 412
is an error status register, 413 is 16-bit parallel input data, 414 is 16-bit parallel output data, 415 is a start signal, 416 is a load signal, 417 is a collect signal, 418 is a load/end signal, 419 is a clock signal, 420
is input serial data, 421 is output serial data, 422 is 16-bit clock signal, 423 is
82-bit syndrome data, 424 an error correction signal, 425 an error status signal, 426 a ready signal, 427 a 16-bit carry signal, etc. First, the CPU sends a start signal 415,
Clear all syndrome registers 403,
The load/collect gate generation circuit 409 is controlled to generate a load gate signal 428. Due to this signal, the input signal 420 to the syndrome register 403 is sequentially loaded into the syndrome register 403. Next, the CPU writes 16-bit data to the data register in the output port 401 and outputs a load signal 416. The load signal 416 outputs a 16-bit clock signal for stepping from the 16-bit pulse generation circuit 408, and
The data in the serial conversion circuit 406 is read, and the data in the syndrome register 403 and the data register 4 are read out.
Load data to 04. The source of the 16-bit clock signal is the clock signal 419,
If the signal is 5 MHz or higher, one packet error can be corrected in a processing time of several H or less. Further, the ready signal generation circuit 41 is activated by this load signal.
1 and make it busy. When the sending of the 16-bit increment clock is completed, a 16-bit carry signal 427 is generated to put the ready signal generation circuit 411 into a ready state. The ready signal 426 prompts the CPU to issue the next command.
The above operation is repeated for each packet of 272 bits. Therefore, data set and load commands are output 272/16=17 times. When all the data is set in the parallel-to-serial conversion circuit 406 and the load instruction is finished, the CPU
outputs the load end signal 418 and increments the syndrome register 403 by one bit. This is a one-bit reduction, and after that, correction can begin from the first bit. Error correction is 16
This is done bit by bit, and the CPU reads the 16-bit data after error correction each time. Collect signal 41
7 is an error correction instruction from the CPU, and this one instruction causes the 16 at the beginning of the data register 404 to
Errors in bit data are corrected. The 16-bit pulse generation circuit 40 is activated by the collect signal 417 in the same way as the load command by the load signal 416.
An 8 to 16 bit clock signal is output and shifts registers 403 and 404 by 16 bits each. If it is determined that there is an error based on the error correction signal 424, the bits at the beginning of the data register 404 are inverted and sequentially loaded into the serial-parallel conversion circuit 407. The error correction signal 424 is the output of the majority circuit 405 and is controlled by the output signal of the load/collect gate generation circuit 409 which is controlled by the collect signal 417. As with data loading, when the 16-bit error correction is completed, the ready signal 426 sends the CPU the 16-bit error correction, and the data is loaded into the register 407 as a serial-parallel conversion circuit. let them know that you are By repeating this operation 17 times, 272-bit data including parity can be restored after error correction. Reference numeral 412 denotes an error status register consisting of an AND gate that receives each bit 423 of the 82 bits of the syndrome register 403, and checks whether the contents of the syndrome register 403 are all "0". This state is
If the CPU reads the error status signal 425,
It is possible to determine whether or not the correction has been made correctly. That is, it is determined that error correction has been correctly performed only when all syndrome registers are "0". Above, data is loaded every 16 bits,
In addition, the data after error correction is sent to the CPU every 16 bits.
was the method to read it, but of course every 8 bits,
The principle is the same for every 34 bits, every 68 bits, every 136 bits, etc. Considering the scale of hardware currently being considered, around 16 bits would be appropriate. If the number of bits per instruction is increased, the circuit configurations of portions 401, 402, 406, 407, etc. will become larger. In majority voting codes, the number of logic circuits actually used increases exponentially as the number of majority voting elements increases. Therefore, a code in which the majority input is 17 as in the present invention is not actually used. The number of OR inputs in the logic formula to realize the logic circuit is MOR = ₁₇ 〓 ⁱ⁼⁹ ₁₇ Ci, and the number of OR input elements is on the order of 10 ⁴ , which makes it difficult to use as an error correction method for actual home receivers. becomes inappropriate. Also, 17-bit input
If you try to realize it with ROM, 2 ¹⁷ -bit ROM
Therefore, a special large-scale ROM is required, making it inappropriate as an error correction system for home receivers. Accordingly, in the present invention, a 17-input majority input logic can be realized using the simplest conventional logic elements, for example, by using the circuit shown in FIG. In FIG. 13, 500 and 501 each represent eight majority inputs. 502
represents one remaining majority input. 5
03 and 504 are 4×256-bit ROMs, and 505 and 506 are ROMs, respectively.
The four bit outputs from 503 and 504 are represented. 507 is a normal adder, and 508 represents its addition output. 509 is a comparator, 510 is the B side input of the comparator 509, 511
represents the A>B output of the comparator 509. First, the 8-bit input 500 outputs the number 1 as a 4-bit output 505 by the ROM 503. For example, M0=1, M1=M2=M3=
When M4=M5=M6=M7=0, output 505
displays 1, such as “1000”. Similarly, for the other 8-bit input 501, the ROM 50
4 outputs an output 506 as the number of 1s. Adder 507 outputs 505 and 50
The binary number 6 and the 17th majority input M16 as a carry are added, and an output 508 is output.
In the comparator 509, the B-side input 510 is fixed at 8, and only when the A-side input 508 is larger than the input 510, "1" is output to the A>B output 511. Such a circuit configuration makes it possible to detect a majority vote when nine or more of the 17 inputs are 1. The principle of the (272, 190) majority code suitable for error correction in character code broadcasting according to the present invention and the actual reception logic circuit configuration method have been explained above.
During actual signal transmission, a system should be used in which only 82 bits of the parity signal or only 190 bits of the information signal are inverted and transmitted, and restored to their original state on the receiving side. This is to prevent the signal from becoming a code word when all the signals in the packet are "0". In addition, in the above example, once the packet signal is
I/O for error control of data imported into RAM
The conventional method was to output the error-corrected data to the CPU and re-read the error-corrected data, but it is also possible to perform error-correction processing before loading the data into the CPU's RAM. In that case, since the error correction processing time requires the same time as the loading time to the shift register, two or more error correction circuits having substantially the same configuration as described above are required. The error correction method suitable for the bit error characteristics of the TV signal VBL transmission path has been described above, and according to this method, a strong error correction effect can be exhibited. In addition, since it can be implemented using a simpler decoding circuit than any other error correction method that processes 272 bits at once, it is suitable for error correction circuits in home receiver terminals that require inexpensive hardware configurations. ing. Furthermore, since it has an error detection function as well as an error correction operation, it is suitable for an error correction system for broadcasting where typographical errors are not allowed. This method is the same as the method already reported by the Radio Technology Council as pattern-based teletext broadcasting.
Since it is a method that transmits a 272-bit digital signal per scanning line of a TV signal, in the future, in addition to character code broadcasting, it will also be possible to use digital facsimile for facsimile, software broadcasting for transmitting computer software, and for visually impaired people. Even when implementing other code broadcasts such as Braille broadcasts for broadcasting, if the bit rate is the same, error correction can be performed using the same method. In this way, the (272, 190) majority code can correct all errors of 8 bits or less that occur at any position in one packet, but errors of 9 bits or more cannot be corrected. Although there are only a few error patterns, most error patterns are uncorrectable. Therefore, in the following, another example of the present invention will be described which is capable of correcting errors of about 9, 10, 11, and 12 bits at a considerable rate. In the example below, all errors in 9 bits can be corrected, and the page error rate can be greatly improved. First, the principle of this example will be described. As mentioned above, the generator polynomial G(x) of (273, 191) is: G(x)=x ⁸² +x ⁷⁷ +x ⁷⁶ +x ⁷¹ +x ⁶⁷ +x ⁶⁶ +x ⁵⁶ +
x ⁵² + x ⁴⁸ + x ⁴⁰ + x ³⁶ + x ³⁴ + x ²⁴ + x ²² + x ¹⁸ + x ¹⁰ + x ⁴ + 1, and in matrix display However, I is a 191×191 unit matrix, P
represents an 82×191 matrix. In addition, Check Matrix H is It is becoming. By linear combination of vectors in 82 rows of matrix H, it is possible to construct a decoding check matrix that is orthogonal on each leading bit. If we extract only the first part of these 17 decryption check formulas, we get the following formula. The reception vector r can be expressed as r=c+e. However, c is a code signal and e is an error signal. Therefore, the equation after applying the decoding check is r.H ₁ 〓=(c+e).H ₁ 〓=eH ₁ 〓, so it is only necessary to consider the error. In the following explanation, eH ₁ will be considered. Here, _H1 is a composite matrix obtained from the check matrix H by linear transformation.

[Table] 〓1
…… 〓
Now, let us consider the case where there is an error of 9 bits or more. Note that all errors of 8 bits or less can of course be corrected from the principle of codes. (1) When all the first 9 bits are errors, the error vector e is e=(1, 1, 1, 1, 1, 1, 1, 1, 1,
0,0,0,...,0), so eH ₁ = (1,0,1,0,1,1,1,0,
0,1,0,1,1,0,1,0,1,0,
1), and the number of 1's is 11, so the threshold value of 9 is exceeded and the 1st bit is corrected. Since all of the remaining 8 bits can of course be corrected, this 9-bit error can be corrected after all. Therefore, in the case of a 9-bit error, if the first error is found and corrected before a correction operation is performed by mistake, it is possible to correct the remaining 8 bits, so all 9-bit errors can be corrected. Correction becomes possible. From this, error correction is performed once, and if the error cannot be corrected, the data itself is corrected by 1 bit or
By cyclically shifting a plurality of bits and performing error correction again, the first error bit will eventually be hit and all nine bits of data will be able to be corrected. (2) Consider the following 10-bit error case. e=(1, 1, 1, 1, 1, 1, 1, 1, 1,
1,0,0,0,0,…,0) eH ₁ 〓=(1,0,1,0,1,1,0,0,
1, 0, 1, 1, 0, 1, 1, 0, 1), and the number of 1's is 10, so the first bit is corrected. The remaining nine errors can all be corrected as described in section (1), so the 10
Individual errors can be corrected. (3) Next, if the first 11 bits are all errors, e = (1, 1, 1, 1, 1, 1, 1, 1, 1,
1,1,0,0,0,...,0) eH ₁ 〓=(1,0,1,0,1,1,0,0,
1, 0, 1, 1, 0, 1, 0, 0, 1), and the number of 1's is 9, so the leading bit can be corrected. The remaining 10 errors can all be corrected as described in section (2). Therefore, all error bits can be corrected for the error pattern described above. (4) Similarly, if the first 12 bits are all errors, e = (1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 0, ..., 0) eH ₁ = (1, 0, 1, 0, 1, 1, 0, 0,
0, 0, 1, 1, 0, 1, 0, 0, 1), and the number of 1's is 8, so no error correction is performed even though there is an error in the first bit. Correct correction is impossible. (5) Next, let us consider the case where even if the same 11 bits are consecutively erroneous, the errors continue from the second bit onwards. e=(0,1,1,1,1,1,1,1,1,
1, 1, 1, 0, 0, ..., 0) eH ₁ = (0, 1, 0, 1, 0, 0, 1, 1,
1, 1, 0, 0, 1, 0, 1, 1, 0) Since there are nine 1's, the first bit is corrected even though it is correct.
Therefore, even if the error is corrected to the last bit,
Not corrected correctly. If it is not corrected correctly, the contents of the syndrome register will be all “0”.
This can be determined from the fact that the condition does not occur. At this time, the data is cyclically shifted by one bit. As a result, the erroneous data has the same form as described in section (3), so it can now be corrected. Here, the composite matrix _H1 is constructed so that the first bit of the 273 bits is orthogonal, but it is also possible to construct a matrix that is orthogonal at the second bit based on the principle of difference set. In this case, the load end instruction (1-bit shift corresponding to the shortened bit) explained in the previous actual circuit example is not necessary.
Error correction operation can be started from the beginning of 2 bits. Therefore, there is an advantage that the circuit configuration becomes simple. In this way, if the first bit of a group of error bits is corrected as early as possible, the remaining error bits can be corrected with a high probability. Therefore, as mentioned in section (1), once a correction operation is performed and it is found that error correction cannot be completed, the received data is converted into one bit by using the cyclic nature of the cyclic code. By shifting and correcting the bits, the possibility of correcting errors of 9 bits or more increases. The flow of the error correction operation is as shown in FIG. FIG. 15 shows an example of an actual hardware configuration for implementing this example. Here, 600 is the CPU
bus line (not shown), 601 is a CPU output port, 602 is a CPU input port, 603 is a parallel-serial conversion circuit, 604 is a serial-parallel conversion circuit,
605 and 606 are gate circuits, 607 and 637 are modulo-2 adders, 608 is a data register, 609 is a syndrome register, 610
611 is a timing generator, 611 is an error status register, and 612 is a majority circuit. 6
13 is a start command signal, 614 is a clear signal,
615 is a load command signal, 616 is a load gate signal, 617 is a load clock signal, 618 is a collect gate signal, 619 is a collect clock signal, 620 is an error status signal, 621 is 82
Bit syndrome signal, 622 error correction signal, 623 correction end signal, 624 fetch command signal, 625 fetch ready signal, 626
is a fetch clock signal, 627 is load data, 628 is fetch data, 629 is load serial data, 630 is circulated load data,
631 is load data for finding syndromes or data rearrangement, 632
is a data register for holding the original data value in a shifted form, 633 is data after error correction, 634 is data rearranged by shifting one bit, 635 is a data shift clock signal, 636
represents a parallel load signal. Next, the circuit operation of this example will be described. The circuit operation will be explained in three modes: (1) Load mode in which initial data is loaded from the CPU, (2) Collect mode in which error correction is applied, and (3) Fetch mode in which the CPU reads data after error correction. (1) Load mode When the CPU takes in 11 packets of 272-bit signals, it generates a start command 613 and sets all register stages of the 82-stage syndrome register 609 to "0" by a reset signal 614. Next, the CPU sets the data to be loaded into the output port and generates a load command signal 615. Parallel data 627 is loaded into register 603. Load control signal 616 controls gate circuits 605 and 606, and input signal 629 is sequentially loaded into syndrome register 609 and data register 632. The signal for one packet is 272 bits, but the shortened first bit is set as "0" data. The parallel data to the parallel-serial converter 603 is
Supplied in units of 8, 16 bits, etc. Therefore, this load operation will be performed 35, 18 times, etc. After loading the syndrome register 609 and load data register 632, all data in the register 632 is copied to the data register 608 at the timing of the parallel load signal 636. Naturally, at this stage, the collect gate signal 618
Therefore, the error correction signal 622 is not yet output. (2) Collect mode When the load operation from the CPU is completed, the error correction mode is entered. The collect clock signal 619 is
273 bits are output continuously. However, since the first bit is shortened, the collect gate signal 618 has a period of 272 bits excluding the first bit. When the error correction signal 622 is output from the majority circuit 612, the data in the data register 608 and the syndrome in the syndrome register 609 are corrected by the error correction signal 622 by the same operation as explained in FIG. In this way, error correction is completed in the bit order in which the packet signal is received. Unless the error status register 611 detects that all 82 bits of the syndrome register 609 are “0”,
The circuit advances to the next stage. This is initiated by the error status register signal 620. First, the original data string 632 is cyclically shifted by one bit. The shift clock signal 635 is
The total of the 1-bit shift and the shift for finding the syndrome is 274 bits. This output signal is sequentially loaded from gate circuits 605 and 606 into syndrome register 609 to generate a syndrome. Clock signal 6 at that time
19 is 273 bits excluding 1 bit for bit position conversion. In this way, after completing the shift over 274 bits in data register 632 to generate the syndrome, the 273 bits in load data register 632 are loaded into data register 608 by parallel load signal 636. . After that, everything is the same as the previous error correction operation. However, the last 1-bit reduction is not corrected. (3) Fetch mode This series of operations is automatically repeated unless the error status signal 620 indicates no error. After the operation of slipping one bit at a time and applying error correction is performed 273 times, the operation is the same as the first one, so a correction end signal 623 is generated to notify the CPU. The CPU reads the error status signal 620, and if all errors have not been correctly corrected, it determines that the error could not be corrected, and an error is detected. If the correction is correct, the CPU generates a fetch command signal 624 and registers the data register 6.
08 signal is used. Of course, since the first bit is not required, only the latter 272 bits of the 273 bits may be fetched. Data is sequentially loaded from data register 608 to serial-to-parallel converter circuit 604 . The CPU sees the fetch ready signal 625, takes in the signal from the serial-to-parallel conversion circuit 604, and generates the next fetch command 624. By repeating this process, one packet worth of signals is restored in the CPU. The example described above is an example of the operation at the final stage when the last bit comes first, but in most cases, correctable errors are caused by the error status signal 620 in the syndrome register 609 during the cycle. Informs that the contents are all “0”. After the error status signal 620 indicates that all error corrections have been made, the collect clock signal 619 takes another action. That is, the data in data register 608 must be restored to its original bit arrangement. Error status signal 6
The number of shifts at the time when the bit in 20 is set is n, and the number of times the leading bit is cyclically rearranged bit by bit is N (that is, the mode in which the Nth bit from the beginning is stored in the syndrome register 609 as the leading bit). ), then by performing 273-n+273-N shifts in the data register 608, the original leading bit is arranged at the leading bit position. At this point, a correction end signal 623 is set to notify the CPU. If the CPU reads this data using the fetch instruction described above, the correct data with the original bit arrangement can be obtained. Although the above-mentioned operation is an embodiment performed by hardware, it is of course possible to implement the operation by using software and the circuit shown in FIG. 12, with the data register 404 having 273 bits. That is, data may be shifted within the CPU and this data may be loaded into the circuit shown in FIG. 12. However, this case has the disadvantage that the processing time is slightly longer. In the explanation so far, all error correction operations have been stopped for the shortened one bit, but in order to simplify the circuit, it is treated like other bits and all bits are corrected. You can also apply it. At that time, the influence of errors due to shortened bits is 1/273. Note that in the above example, data was cyclically shifted by one bit when one-time error correction was impossible, but multiple bits may also be shifted to simplify the circuit or speed up processing. Conceivable. For example, if the number of bits to be shifted is 2 bits, there is an advantage that the processing time can be halved. When using the above-mentioned (272, 190) majority code, burst-like errors of 9 or more bits in one packet, or uncorrectable 2 or more bits that occur in the framing signal section for frame synchronization. If an error occurs, one packet worth of signal is lost. Incidentally, the framing signal consists of 8 bits, and an error in 1 bit among the 8 bits can be corrected. FIG. 16 shows a packet signal of character code broadcasting. Here, 700 represents a horizontal synchronization signal, 701 a color burst, 702 a clock line in for clock synchronization, 703 a framing signal for frame synchronization, and 704 a 34-byte packet signal. FIG. 17 represents a packet signal sent out according to the present invention. The signal for one packet sent out in the normal arrangement is decomposed into 8 bits each and distributed into each packet as shown by the x in the figure, and the signal for one packet marked by the x is sent out using 34 packets. The receiving side has a buffer similar in size to that shown in FIG. 17, and upon decoding, it sequentially takes in the 8 bits marked with an x, converts them into a standard arrangement signal, and then performs error correction for each packet. In this way, by performing interleaving between packets of every 8 bits (between fields), it is possible to correct errors caused by noise mixed into packets in bursts. In other words, even if all of one packet signal is an error (in reality, this rarely happens; even if there are errors in the entire packet, the average error is 272/2 = 136 bits). , the error is divided into 8 bits and distributed evenly over 34 packets, so any 8-bit error randomly occurring in one packet (272 bits) can be corrected using (272, 190) error correction. All can be corrected by the code. This shows that even if a framing error occurs and all data for one packet is lost, as long as it is known that the signal has arrived, it is sufficient to correct the error by assuming that the received signal is a constant value. ing. Also, assuming that the received signal is a constant value, the average number of error bits is 272/2=
It is 136 bits, 4 bits per 8 bits, so
On average, even two framing errors can be corrected. By transmitting a packet signal using such a bit arrangement, it is possible to sufficiently cope with urban noise generated in bursts from automobiles and the like, impulse noise from home appliances, and the like. Regarding noise that naturally occurs randomly,
There is no difference from the standard array. Next, the logic on the receiving side will be explained.
On the receiving side, 34×34=1158 as shown in Figure 17
Prepare a byte buffer on RAM. Assuming that the first address is A0, the first packet signal received is accommodated in addresses A0 to A0+33. The next received packet is accommodated in addresses A0+34 to A0+67. In other words, the latest packet at address n is A0
+34(n-1) to A0+34(n-1)+33. When n reaches 34 for the first time, the 1156-byte buffer becomes full and the packet signal error correction operation begins. The data input to the error correction circuit is the data marked with an x in Figure 17, and the address is
A0, A0+35, A0+70, A0+105,..., A0+
It is 1155. The n=35th packet signal is again
Accommodate within addresses A0 to A0+33. Therefore, the general formula for the address accommodating the nth arriving packet signal is A0+34×({n/34}-1) to A0+34{n/34}-1, where { } represents the remainder. becomes. The packets to be decoded when n=35 correspond to the circles in FIG. That is, A0+34,
A0+69, A0+104, ..., A0+33. The general formula is A0+34×{n/34}~A0+33×34{n/34} A0+33-({n/34}-1)~A0+33+34×({n/34}-1). Similarly, when n=36, Δ is taken out, and when n=37, the ● marks are taken out in sequence and loaded into the decoding circuit to correct one packet error. In the embodiment of FIG. 17, the received packet signal is
The method used was to collect 34 bytes of data from discrete addresses and decode one packet by sequentially writing it into the CPU's RAM and passing it through the error correction decoder, but in contrast to this in Figure 18,
When writing data to the packet buffer, data is written sequentially to predetermined addresses, and when reading data, 34 bytes are read from consecutive addresses to directly obtain data for one packet. The numbers in the figure represent transfer packet numbers. The general formula for writing is A0+34(n-1), A0+34(n-1)-33,...A0
+34(n-1)-33(n-1) and A0+34×33+{n/34}, A0+34×33+{n/34}-33... A0+34×33+{n/34}~33 (33-{n/ 34}). However, A0 is the starting address, n is the nth packet, and { } is the remainder. If data is written 8 bits at a time according to the address in the above formula, one packet of data can be extracted by reading 34 bytes of data continuously. The starting address at that time will be A0+34(n-1). In the above explanation using FIGS. 17 and 18,
It was a method in which 1 byte data was sent sequentially with a delay of 1 packet during 34 packets, and the data for 1 packet was restored only after 34 packets. However, it is theoretically possible to randomly arrange each byte (8 bits), and it can be used as a kind of scrambled transmission for Pay TV. In order to explain the principle of scramble transmission of each byte between packets, FIG. 19 is a diagram in which only the second and third bytes of the transmission method of FIG. 17 are replaced. On the receiver side, prepare a packet buffer as shown in Figure 19, and when the 34th packet is received, read the bytes indicated by the x mark, compose one packet of data, and decode it. . Similarly, the packet signals are sequentially restored by marking ◯ when receiving 35 packets, marking △ when receiving receiving 36 packets, and marking ● when receiving receiving 37 packets. Of course, 35 packets, 36 packets, 37 packets, etc. are A0, A0 + 34, respectively.
Start writing from address A0+68. Note that A0 indicates the starting address of the packet buffer. Assuming that the first byte of each packet is transferred in the order of transfer, the number of possible patterns is 33! ≒8.68×10 ³⁵ ways. On the other hand, the total number of packets per day that can be transmitted using 1H of the vertical blanking period of the TV signal is 60 x 60 x 60 x 24 = 5.18 x ¹⁰⁶ . Therefore, if the scrambling principle according to the present invention is known but the scramble transmission pattern is not known, even if the receiver side searches for a randomly generated pattern, it will take 10 ^{to 29} days to decipher. It's impossible. Furthermore, if we add information for inverting the signal of each of the 33 bytes to this example, there are ²⁵³ patterns, resulting in a total of ²³³ × ¹⁰²⁹ days, which is an astronomical number. FIG. 20 shows ROM information for solving the scramble explained above. The number of bits in the ROM is 34 x (5 + 1) bits = 204 bits. In FIG. 20, the address indicates the packet number corresponding to the byte number required to restore the first packet. Since it is sufficient to indicate 0 to 33, 5 bits is sufficient. Further, the inversion information indicates whether the information of each byte of one restored packet is inverted and transmitted. Therefore,
One bit is sufficient for this purpose. On the broadcasting station side, each time the scramble address and inversion information are changed, the receiver is notified as shown in Figure 20.
If you issue the ROM, there is no need to worry about it being eavesdropped on. Of course, either one of the scrambling methods described in the above example can be used to achieve sufficient functionality. Furthermore, it goes without saying that the inversion information and the scramble address may be specified in units of multiple bits, such as 16, 34, and 68, respectively. As described above, in the embodiment in which each byte constituting one packet of character code broadcasting is transmitted in a separate packet, the error correction capability for bit errors occurring in bursts is enhanced. In the 8-bit error correction method using (272, 190) in the present invention, even if one packet's worth of information is lost, all of it can be restored. That is, even if there is a framing error, if there are no errors in the other 33 packets, all errors can be corrected. In the embodiment shown in Figure 17, the receiving side has a 34 x 34 byte packet buffer, and arriving packet signals are cyclically written to the packet buffer.
By reading each byte diagonally, it is possible to construct a signal for one packet. In the embodiment shown in Fig. 18, on the other hand, the arriving packet signal is written diagonally according to a certain rule, so when reading, it is possible to obtain a signal for one packet by reading only 34 bytes continuously. can. In the embodiment shown in FIG. 19, since the transfer packets of each byte are randomly arranged during signal transmission, it can also be used for confidential communication while maintaining the same error correction ability as the embodiment described above. On the broadcasting station side, it is quite conceivable that it could be used in a pay TV style. In the embodiment shown in FIG. 20, in addition to the embodiment shown in FIG. 19, inversion information of each byte information is also added, which has the advantage of making it even more difficult for the receiver to view and listen to the data in secret. As described above, in the present invention, when errors cannot be corrected, by shifting the bit position and applying correction, the correction ability can be increased even for errors of 9 bits or more, which cannot be corrected in the first place. However, it has the advantage of not reducing error detection ability, and the present invention is effective in correcting errors in character code broadcasting, and is extremely effective in significantly expanding the service area of character code broadcasting. Furthermore, digital signals that encode information are
In the above example, it was inserted in the vertical retrace period of the TV signal, but
Of course, such a digital signal can be used in various other forms, inserted into other signals in a transmission system, or used alone. Further, in the above explanation, the threshold value has been set to 9, but it goes without saying that even if the threshold value is 10, it will still have error correction ability of 8 bits or less based on the principle of codes that can be decoded by majority logic circuits.

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of the average value of the distribution of the number of error bits of received data in a field experiment, and Figure 2 is a diagram showing the average distribution of the number of error bits of received data when transmitting and receiving signals are interleaved in a field experiment. Figure 3 is a diagram showing the distribution of the number of error bits in one packet. Figure 4 is a diagram showing the distribution of the number of error bits in one packet in the waveform distortion area. Figure 5 is a diagram showing the distribution of the number of error bits in one packet. 6 and 6 are diagrams showing the distribution of error burst lengths in one packet in the impulse region and the waveform distortion region, respectively. FIG. 9 is a block diagram showing an example of the configuration of an error correction decoding circuit. FIG. 11 is a block diagram showing another example of the error correction decoding circuit according to the present invention, and FIG. 12 is a block diagram showing another example of the error correction decoding circuit according to the present invention. FIG. 12 is a block diagram showing an example of the present invention applied to an actual character code broadcasting receiver FIG. 13 is a block diagram showing an example of the configuration of the majority circuit according to the present invention. FIG. 14 is a flowchart showing the flow of error correction operation according to the present invention. 16 is a block diagram showing yet another configuration example of a circuit for implementing the present invention, FIG. 16 is a diagram showing an example of a packet signal used in character code broadcasting, and FIG. 17 is a diagram showing an example of a packet signal used in character code broadcasting. FIG. 18 is a line diagram showing the first example of the packet signal, FIG. 19 is a line diagram showing the third example of the packet signal in the present invention, and FIG. FIG. 7 is a diagram showing an example of a scramble decoding ROM in a fourth example of a packet signal obtained by adding inverted information of each byte to the signal shown in the figure; 100...7-bit input signal, 101...Syndrome register, 102...Buffer register, 103-107...Adder, 109...Majority circuit, 111-113...Majority circuit input, 1
14...Majority circuit output, 200...Information bit, 201...Parity register, 202-20
4... Switch circuit, 205... Sending packet signal, 206... Adder, 300... Input signal, 3
01...Data register, 302...Syndrome register, 303-323...Adder, 324
~340...majority circuit input, 341...majority circuit, 342...correction signal, 343...adder,
344... Data output after correction, 400... Bus line, 401... Output port, 402... Input port, 403... Syndrome register, 40
4...Data register, 405...Majority circuit,
406...Parallel-serial conversion circuit, 407...Series-parallel conversion circuit, 408...16-bit pulse generation circuit, 409...Load/collect gate generation circuit, 410...Gate circuit, 411...Ready signal generation circuit, 412...Error status register, 413...16-bit parallel input data,
414...16-bit parallel output data, 415
...Start signal, 416...Load signal, 41
7...Collect signal, 418...Load end signal, 419...Clock signal, 420...Input serial data, 421...Output serial data,
422...16 bit clock signal, 423...82
Bit syndrome data, 424...Error correction signal, 425...Error status signal, 426
... Ready signal, 427 ... 16-bit carry signal, 428 ... Load gate signal, 501 to 5
02...Majority input, 503,504...
ROM, 505, 506...ROM output, 507
... Adder, 508 ... Adder output, 509 ...
Comparator, 510...Comparator input, 511...Majority output, 600...Bus line, 601...Output port, 602...Input port, 603...Parallel-serial conversion circuit, 604...Serial-parallel conversion Circuit, 605-606... Gate circuit, 607, 6
37...Adder, 608...Data register, 6
09...Syndrome register, 610...Timing generator, 611...Error status register, 612...Majority circuit, 613...
Start command signal, 614... Clear signal, 61
5...Load command signal, 616...Load gate signal, 617...Load clock signal, 618...
...Collect gate signal, 619...Collect clock signal, 620...Error status signal, 6
21...32 bit syndrome signal, 622...
Error correction signal, 623...Correction end signal, 624
...Fetch command signal, 625...Fetch ready signal, 626...Fetch clock signal, 6
27...Load data, 628...Fetch data, 629-631...Load data, 632...
...Load data register, 633...Data after error correction, 634...Parallel data, 635...Data shift clock signal, 636...Parallel load signal.

Claims (1)

[Claims] 1. Using a signal of 273 data bits, 191 information bits, and 82 parity bits from the majority difference set cyclic code, one bit is decreased from this signal to configure one packet with 272 bits,
A data signal of 272 data bits, 190 information bits, and 82 parity bits is formed and transmitted, correction is performed according to the output state of the syndrome register of the transmitted data signal, and when the correction is completed, the syndrome register is all zero. An error correction decoding system characterized in that the probability of correcting errors of 9 bits or more per packet is increased by shifting the leading bit and performing error correction again only when the error is not corrected. 2. In the error correction decoding system according to claim 1, a syndrome register to which the information bits are input, a data register to which the information bits are input, and a majority circuit that takes a majority vote among the outputs of the syndrome registers. syndrome correction means for supplying the majority decision output of the majority decision circuit to the syndrome register to correct the syndrome; and addition means for adding the majority decision output to the output from the data register, and decoding from the addition means. An error correction decoding method characterized by extracting encoded information. 3. An error correction decoding system according to claim 1, characterized in that information for one packet is divided into multiple bits and each bit is transmitted as a separate packet. 4. The error correction decoding system according to claim 3 has a memory for 34 packets, and accesses the memory according to a certain algorithm when writing or reading packet signals to read packet signals in a standard arrangement. An error correction decoding method characterized in that it obtains the following error correction decoding method.