JPH0376469A - Decoding circuit for variable length code - Google Patents

Abstract

PURPOSE:To quicken the decoding without increasing the circuit scale by providing a shortest code group decoding logic circuit decoding a code group with high appearance frequency and short code length through the combination of AND and OR. CONSTITUTION:A shortest code group decoding section has a function of receiving 7 kinds of code groups whose designated code length is 4 or below, for example, and of outputting a decoded data, that is, a fixed length data (EXD1) and a code length (CDS1) and consists of a logic circuit comprising the combination of AND and OR circuits only and has a faster decoding speed than that of a decoding table employing a ROM. For example, the decoding speed of the shortest code group decoding section 2 using the logic circuit is 50ns, which is faster than the access speed of 200ns of the decode table employing a ROM. Thus, when a code data whose code length is less than the designated length is decoded, multiplexers 4, 5 select the decoding result of the shortest code group decoding section 2 and the decoding data (EXD1) is outputted to a latch 7 and the code length (CDS1) is outputted to a code data input section 1.

Description

Detailed Description of the Invention [Summary] The present invention relates to a variable length code decoding circuit that obtains original fixed length data by inputting a variable length code in which a shorter code is assigned to data that appears more frequently. The purpose of this is to speed up decoding without increasing the code length by ANDing a group of codes with short code lengths that appear frequently.

A logic circuit for decoding the shortest code group that decodes by a combination of ORs is provided, and the overall decoding speed is improved with a simple circuit by high-speed decoding by the logic circuit for the shortest code group.

[Industrial Field of Application] The present invention relates to a variable length code decoding circuit in which a shorter code is assigned to data that appears more frequently.

In order to accumulate image data, which has an order of magnitude larger amount of information than numerical data, especially halftone and color image data, or to transmit it at high speed and high quality, it is necessary to increase the gradation value of each pixel. It is necessary to encode it efficiently.

As a highly efficient compression method for image data, there is, for example, a multi-gradation adaptive block coding method (Preliminary Draft 6 of the National Conference of the Institute of Image Electronics Engineers, 1988).

Multi-gradation adaptive block coding method (Generalir
ed Block Truncation Cod
ing (hereinafter abbreviated as rG B T CJ)
This will be explained next.

GBTC divides an image into blocks consisting of NXN pixels, and quantizes each pixel (Xij) at the 2° (n=o, 1.2°...) level of the maximum and minimum pixel levels within the block. At the same time, the quantization level of each pixel is expressed in a bit plane format, and gradation information and bit plane information (referred to as resolution components) are encoded.

Next, N=4. The case where n=2 will be described in detail.

FIG. 5 shows the GBTC algorithm. Each block is determined by the difference (LmaI-Lwin) between the maximum pixel level (Lmax) and the minimum pixel level (Lmin) within the block.
) and the ossification parameters TI, T2 (TI < T
2), the following three encoding modes A, B,
Classified as C.

Mode A: If Lmax-Lmin≦T, the pixels within the block are quantized to one level (po).

Mode B: If T, <Lmax-Lmin≦T2, the pixels in the block are quantized to two levels (PI, P2).

Mode C: When T2<Lmax-Lmin, pixels within a block are quantized into four equally spaced levels (Q, to Q4).

The quantization level is the reference level La of the block.

Level interval Ld and level designation signal for each pixel (φILI
+(φ2)1. It is described in

If the average value processing is AVE(), each value necessary for encoding is calculated as follows.

Mode A: Pa = AVE (Xii) = L a (φI), = O
, (φ2)11=0 (for all IT J) Mode B: P ,=AV E (X i j≧(Lmax+I
, m1n)/2) P2 =AVE (Xij< (Lm
ax + Lmin) / 2) La = (Pi + P2) / 2 L d = P 1P 2 (φ, ), = 0 (If Xii≧(Lmax+Lmin)/2) (φI
), I=1 (if Xij< (Lmax+Lmin)/2) (φ
2), =O (for all i, j) Mode C: Ql =AVE (Xi j≧ (3Lmax+L
min)/4)Q4 =AVE (Xij< (
Lmax+31. m1n)/4)L a= (Ql
+04) /2Ld=2 (Ql -Q4)/
3 Q2 = L a + L d/4 Q, = La - L d/4 (φ+), +=0. (φ2),,=0 (when Xij≧La+Ld/2) (φ+), +=0. (φ2), = 1(La+Ld/
2>Xij≧La) (φz)z=1. (φ2),
, = 0 (when L a >Xij≧La-Ld/2) (φ+)
,=1. (φ2),,=i (when L a−L d/2>Xij) Resolution component (φ
1. φ2) is connected between blocks and converted into two bitmaps, each of which is encoded using the MMR encoding method, which is a standard encoding method for binary images. The level interval Ld is variable length encoded after nonlinear quantization, and the reference level La is DP
The prefix difference (ΔLa) is nonlinearly quantized using CM encoding and then variable length encoded. These variable length codes are then transmitted via a transmission line.

The GBTC method uses a Huffman code as a variable length code. In Huffman codes, short codes are assigned to target data that appear frequently, and long codes are assigned to data that appear less frequently. The procedure for creating a basic Huffman code is shown below.

■ Arrange the appearance frequencies of the data obtained in advance in ascending order.

■Extract two pieces of data starting from the one with the lowest frequency of appearance.

■Assign “0” as the end of the code to the smallest one, and
Assign “1” to the th data.

■The total of the above two appearance frequencies is used as new data, and the two data extracted in (■) are deleted.

■Perform operation ■ with the remaining data. This operation is then repeated until there is no more data.

■After processing all data, rearrange the order within each code word (because it was determined from the end of the code) 1
0For example, create a code table as shown in Figure 6.

Figure 6(a) shows variable length encoded data (output) for fixed length data values (input) a to f, and Figure 6(b)
) indicates the code length of variable length encoded data for fixed length data values (input) a to f.

The variable length code data length is variable, and the delimiter between data cannot be detected without decoding.

Therefore, at the time of decoding, a format is adopted in which code data for the maximum code length is read and a decoding table is referred to. When the maximum code length is 4, there are 16 (=24) types of code data to be read when referring to the decoding table. The decoding table is shown in Figure 7 (a
) As shown in (b), the configuration is such that each of the fixed length data value and code length is determined for 16 types of variable length encoded data (input).

[Prior Art] FIG. 8 shows a configuration diagram of a conventional variable length code decoding circuit.
The input variable length encoded data is decoded into the original fixed length data by the next processing operation.

Code data inputted from the terminal 10 is inputted to the code data input section 1. The code data input unit 1 sequentially inputs effective data (CO
DE) and output it to the decoding table 3. The decoding table 3 is configured as shown in FIG. 7, and converts input code data (CODE) to fixed length data (EXD).
At the same time, the code length (CDS) is output.

Here, assuming that the maximum code length is 16 bits and the fixed length data to be decoded is 8 bits, the decoding table 3 is composed of two ROMs of 64 bits x 8 bits.

The decoded data (EXD) from the decode table 3 is output to the latch 7. On the other hand, the code length (CDS) is output to the code data input section 1.

The timing control unit 20 configures the decoding table 2.
The OM access time is calculated, and a data latch signal is generated in the latch 7 after the calculated access time. This latch signal causes the decoded data to be latched into the latch 7, and the terminal 11
It is output from

When the decoding of one piece of code data is completed, the timing control section 20 instructs the code data input section 1 to prepare the next code data. The code data input unit 1 shifts and discards code data corresponding to the code length (CDS) that has already been decoded from the previous code data, and decodes the data of the maximum code length from the beginning of the remaining code data for the next decoding. The data is cut out as data for use and the same decoding process is performed.

[Problem to be solved by the invention] However, in such a conventional decoding circuit,
In order to perform high-speed decoding, a decoding table is configured using memory such as ROM, but the capacity of the decoding table is generally large, and the decoding speed is determined by the access speed of the memory, so it is difficult to increase the speed. There was a point.

The present invention has been made in view of these conventional problems, and it is an object of the present invention to provide a variable length code decoding circuit that can speed up decoding without increasing the circuit scale.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

First, the present invention is directed to a variable-length code decoding circuit that receives a variable-length code of maximum M bits, in which a shorter code is assigned to data that appears more frequently, and obtains original fixed-length data.

In the present invention, for such a decoding circuit, a code data input means 1 for temporarily holding variable length data and a code data input means 1 for temporarily holding variable length data, and a code data input means 1 for temporarily holding variable length data; a shortest code group decoding means 2 for outputting the code length of the code and the original fixed length data corresponding to the code; for all codes, the code pattern is used as an address to output the code length of the code and the original fixed length data corresponding to the code; a decoding table 3 configured to output original fixed length data; a decoding table 3 configured to select one of the fixed length data outputted by the shortest code group decoding means 2 and the fixed length data outputted by the decoding table 3; 1 switching means 4; a second switching means 5 for selecting one of the code length output by the shortest code group decoding means 2 and the code length output by the decoding table; timing control means 6 for determining the latch timing of the decoded data depending on whether or not it has been decoded by the shortest code group decoding means 2 and outputting a latch signal; a latch means 7 for latching by the latch signal outputted by the means 6; and instructs the second switching means 4.5 to select the output of the shortest code group decoding means 2, and sets the latch timing of the decoded data to an earlier timing based on the processing time of the shortest code group decoding means 2. Configure it to do so.

[Operation] In the variable-length code decoding circuit according to the present invention having such a configuration, only variable-length codes with short code lengths can be decoded using logical sum and logical product that can be processed at high speed. , codes that appear frequently can be decoded at high speed, and the average decoding speed can be improved with a simple circuit.

For example, when using the code table for the reference level La component of the GBTC system shown in FIG. 9, 76% of all codes have a code length of 4 bits or less, and the ROM access speed is 200 ns.
Decoding by logic circuit using AND and OR takes 50ns
Then, the average value of decoding speed is 86ns, which is 2.3
You can achieve twice the speed.

[Embodiment] FIG. 1 is a block diagram of an embodiment of a variable length code decoding circuit according to the present invention.

In FIG. 1, first, code data is sequentially input to the code data input section 1 from the terminal 10. The code data input section 1 inputs the code data into the maximum code long hand effective data (COD E).
Cut out and output all at once.

The extracted code data (CODE) of the longest code length hand is input to each of the decoding table 3 and the shortest code group decoding unit 2. The shortest code group decoder 2 and the decoding table 3 decode the input code data in parallel and output them to the multiplexer 4 and the multiplexer 5, respectively.

Here, as shown in the conventional circuit, the decoding table 3 shows the code length of each code and the original fixed length data corresponding to each code using the code pattern as an address for all codes. For example, as shown in FIG. The decoding table is stored in ROM. On the other hand, the shortest code group decoding unit 2 inputs, for example, seven types of code groups shown in the frame of FIG. CD
It has a function of outputting SL) and is composed of a logic circuit consisting only of a combination of an AND circuit and an OR circuit, and has a faster decoding speed than a decoding table using a ROM. For example, R
Decoding table access speed using OM: 200ns
On the other hand, the decoding speed of the shortest code group decoder 2 using a logic circuit is as fast as 50 ns.

Therefore, when code data with a pre-specified code length or less is decoded, the decoded result of the shortest code group decoder 2 is selected in the multiplexer 4 and the multiplexer 5, and the decoded data (EXDI) is output to the latch 7. and the code length (
CDSI) is output to the code data input section 1. On the other hand, when code data with a specified length or more is decoded, multiplexers 4 and 5 select the decoding result of the decoding table 3, the decoded data (EXD2) is output to the latch 7, and the code length (CDS2) is Output to data input section 1. The latch 7 latches the input decoded data (EXDI or 2) according to the latch signal from the timing control section 6 and outputs it to the terminal 11.

When the decoding of one piece of code data is completed, the timing control section 6 instructs the code data input section 1 to prepare the next code data. The code data input unit 1 receives the code data from the previous code data.
The code length (CD
The code data for SI or 2) is shifted and truncated, the data of the maximum code long hand is cut out, and the data for the next decoding signal (C
OD E) and decodes the next signal.

Next, the method of selecting a decoded signal and the timing of latch signal generation by the timing control section 6 will be specifically explained using the timing chart shown in FIG. Here, one clock in the timing chart is 50n
Let it be s.

First, when decoding code data of a specified length or less, the shortest code group decoding unit 2 converts each bit of the input code data into
It is decoded using logical product and logical sum, and the decoded data (EXDI
) and code length (CDSL), and outputs a coincidence detection signal E indicating that decoding has been effectively performed. When the timing control section 6 receives the coincidence detection signal E, it instructs the multiplexer 4 and the multiplexer 5 to select the output signal of the shortest code group decoding section 2. The decoded data (EXDl) selected by the multiplexer 4 is input to the latch 7 as the decoded data (EXD) to be decoded, is latched by the latch 7 by a latch signal from the timing control section 6, and is output from the terminal 11. Further, the code length (CDSI) selected by the multiplexer 5 is input to the code data input unit 1 as the code length (CDS) to be decoded.

A portion (nl) in the timing chart of FIG. 3 indicates the timing of generation of a latch signal from the timing control section 6 when decoding code data of a specified length or less. That is, after code data is input and decoding is started, a coincidence detection signal E is outputted from the shortest code group decoder 2 within one clock, and according to this coincidence detection signal E, after decoding is started, 1
Generate a latch signal using the clock (50ns),
One round of decoding is completed.

On the other hand, when decoding code data having a specified length or more, decoding is performed using the decoding table 3 as in the prior art. The decoding table 3 extracts decoded data (E
XD2) and code length (CDS2) are output. Since the timing control section 6 does not receive the match detection signal E, it instructs the multiplexers 4 and 5 to select the output signal of the decoding table 3. The signal data (EXD2) selected by the multiplexer 4 is input to the latch 7 as the decoded data (EXD) to be decoded, is latched by the latch 7 according to the latch signal from the timing control unit 6, and is output from the terminal 11. . Further, the code length (CDS2) selected by the multiplexer 5 is inputted to the code data input unit 1 as the code length (CDS) to be decoded, and the code data is shifted as in the conventional technology.
Cut out the next signal.

The timing at which the latch signal is generated from the timing control unit 6 when such a decoding table 3 is selected is at part (n2) in the timing chart shown in FIG. That is,
After the code data is input and decoding starts, the timing control unit 6 does not receive the coincidence detection signal E, so the timing control unit 6
2 after the start of decoding.
A latch signal is generated in 00 ns, and one decoding is completed in 200 ns.

In this way, the code data input unit 1 collects the code data into effective data (CODE) of the maximum code length, and decoding of the code data of the specified length or less is performed by the shortest code group decoding unit 2, and the code data of the specified length or more is decoded. The data is decoded using the decoding table 3, whereby coded data for one screen is decoded.

FIG. 4 is a block diagram of a specific embodiment of the shortest unlucky group decoder 2 shown in FIG. I'm keeping it.

In the case of the decoding table in Fig. 9, the maximum code length is 15, but the
For the shortest code group decoder 2 shown in the figure, the code pip whose specified code length is 4 minutes from the beginning) (ro r.

12 I3) is input.

The shortest code group decoding unit 2 includes a code decoding logic circuit 12 for decoding plus and minus polarity codes, and a code length (CDSI)
) for decoding the code length decoding logic circuit 14 and decoding value decoding logic circuit 16 for decoding the decoded data value (EXDI).
Consists of.

The logical formula of the code decoding logic circuit 12 is given by the following formula.

5=Io11 I2 13 +1. I, 12 I, +1. I, I2 The logical formula of the code length decoding logic circuit is given by the following formula.

Furthermore, the logical formula of the decoded value decoding logic circuit 16 is given by the following formula.

Vo”IoIt V1=IOII V2 =Io 11 I2 Vi ”Io II I2 As is clear from these logical formulas, the logic circuit 12.1
4 is a combination of AND circuit and OR circuit, logic circuit 16 is A
It can be configured with only ND circuits, and as a result, 50n
A decoding speed as high as s can be achieved.

Although the above embodiment takes as an example the decoding circuit for encoded data of the GBTC reference level La shown in FIG. 5, it can be applied as is to decoding appropriate encoded data.

Further, the specified length for determining the code group to be decoded by the shortest code group decoding unit 2 implemented by a logic circuit can be appropriately determined as necessary, as long as the overall decoding speed can be improved.

[Effects of the Invention] As explained above, according to the present invention, a decoding circuit using logical sum and logical product that can perform high-speed decoding is used for codes that appear frequently, so that average decoding is possible. The speed can be improved, and this can greatly contribute to improving the performance of the decoding circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention; FIG. 2 is a configuration diagram of an embodiment of a variable length code decoding circuit according to the present invention; FIG. 3 is a timing chart of decoding processing in the embodiment in FIG. 2; The figure is a diagram of an embodiment of the shortest code group decoding unit in Figure 2; Figure 5 is an explanatory diagram of the GBTC algorithm; Figure 6 is an explanatory diagram of the configuration of the code table; Figure 7 is an explanatory diagram of the configuration of the decoding table; FIG. 8 is a block diagram of a conventional decoding circuit; FIG. 9 is an explanatory diagram of an actual variable length code decoding table. In the figure, 1: code data input means 2: shortest code group decoding means 3: decoding table 4: first switching means (multiplexer) 5: second switching means (multiplexer) 6: timing control means 7: latch means 10.11 : Terminal 12: Logic circuit for code decoding 14: Logic circuit for code length decoding 16: Logic circuit for decoding decoded value Today's date and month's M temporary code eyebrows -? @Koji 1 da under Todoroki 9 [Yokohachi 4th figure 368-

Claims (1)

[Claims] (1) A shorter code is assigned to data that appears more frequently, and the variable length code decoding circuit inputs the assigned variable length code of maximum M bits to obtain the original fixed length data. Temporarily held code data input means (
1) and; Shortest code group decoding means (2) which outputs the code length of the code and the original fixed length data corresponding to the code by logical sum and logical product for the shortest code of N bits (N≦M) or less; ); and a decoding table (3) configured to output the code length of each code and the original fixed length data corresponding to the code using the code pattern as an address for each code; and the shortest code group. a first switching means (4) for selecting either the fixed length data outputted by the decoding means (2) or the fixed length data outputted by the decoding table (3); by the shortest code group decoding means (2); a second switching means (5) for selecting one of the output code length and the code length output from the decoding table (3); the input variable length code is selected by the shortest code group decoding means (2); )
a timing control means (6) that determines the latch timing of the decoded data depending on whether the data has been decoded by the decoded data and outputs a latch signal; ); and a latch means (7) for latching by a latch signal outputted by the timing control means (6), when the input variable length code is decoded by the shortest code group decoding means (2). Only the first and second switching means (4) (5
) to select the output of the shortest code group decoding means (2), and setting the latch timing for the latch means (7) to an earlier timing based on the processing time of the shortest code group decoding means (2). A variable length code decoding circuit characterized by: