JPH0375808A - Software timer control system - Google Patents

Software timer control system

Info

Publication number
JPH0375808A
JPH0375808A JP1212237A JP21223789A JPH0375808A JP H0375808 A JPH0375808 A JP H0375808A JP 1212237 A JP1212237 A JP 1212237A JP 21223789 A JP21223789 A JP 21223789A JP H0375808 A JPH0375808 A JP H0375808A
Authority
JP
Japan
Prior art keywords
timer
processor
main processor
control
software
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1212237A
Other languages
Japanese (ja)
Inventor
Maki Uematsu
上松 真樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1212237A priority Critical patent/JPH0375808A/en
Publication of JPH0375808A publication Critical patent/JPH0375808A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the load of a main processor owing to timer interruption by controlling a software timer by means of an independent and private processor. CONSTITUTION:When a timer processing request is generated by software in the middle of operation on the main processor, the main processor 1 gives the timer processing request with the time out value of the timer and a task ID in the middle of operation to the timer control processor 2. It generates one corresponding control block with the given time out value and the task ID by the timer processing request and registers it to a timer control queue. The timer control processor 2 reduces the time out values of respective control blocks whenever timer interruption occurs. When the value comes to '0', the control blocks are removed from the timer control queue, and the task ID which is timed out is reported to the main processor 1. Thus, the main processor 1 is released from the simple interruption operation of prescribed time intervals.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はリアルタイムシステムのタイマ管理に関し、特
にソフトウェアタイマの管理方式Gこ関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to timer management for real-time systems, and particularly to a software timer management method.

〔従来の技術〕[Conventional technology]

従来、この種のリアルタイムシステムにおけるタイマ管
理は、単一プロセッサがハードウェアタイマによる一定
間隔の割り込み信号を割り込みハンドラで受け、タイマ
値を伴った管理ブロックとして待ち行列による登録・削
除管理を行うことにより、見かけ上、複数のタイマがあ
るかのようにソフトウェアにより管理していた。
Conventionally, timer management in this type of real-time system is performed by a single processor receiving interrupt signals at regular intervals from a hardware timer using an interrupt handler, and managing registration and deletion using a queue as a management block with timer values. However, it appears that there are multiple timers, which are managed by software.

〔発明か解決しようとする課題〕[Invention or problem to be solved]

上述した従来のタイマ管理方式は、単一プロセッサが直
接ラフ1へウェアタイマの管理を割り込みハンドラによ
り行っていたのて、タイマを短い間隔に設定した場合に
は、タイマ割り込み回数が増加し相対して割り込み処理
時間が長くかかつてしまう。また数多くのタイマを使用
した場合にも、割り込み処理時間が長くかかってしまい
、システム全体としては応答が悪くなるという欠点があ
る。
In the conventional timer management method described above, a single processor manages the wear timer directly to rough 1 using an interrupt handler, so if the timer is set to a short interval, the number of timer interrupts increases and interrupt processing time may be long or long. Also, when a large number of timers are used, it takes a long time to process interrupts, and the system as a whole becomes less responsive.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のソフトウェアタイマ管理方式は、主プロセッサ
とは独立したタイマ管理専用のプロセッサを有し、それ
ぞれのプロセッサ間でタイマ情報に関するデータの交換
手段を有している。
The software timer management system of the present invention has a processor dedicated to timer management that is independent of the main processor, and has means for exchanging data regarding timer information between the respective processors.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明のソフトウェアタイマ管理方式の構成図
である。第1図において、主プロセッサ1は、タイマ管
理用プロセッサ2に接続されており、主プロセッサ上で
動作中のラフ1〜ウエアによりタイマ処理要求が牛した
場合、タイマのタイムアウト値及び動作中のタスクID
を伴いタイマ処理要求をタイマ管理用プロセッサに与え
る。タイマ管理用プロセッサは、このタイマ処理要求に
より対応する1つの管理ブロックを与えられたタイムア
ウト値・タスクIDを伴い生成しタイマ管理待ち行列に
登録する。タイマ管理用プロセッサはタイマ割り込みが
発生する度に各管理フロックのタイムアウト値を滅し、
その値が0になった時に管理ブロックをタイマ管理待ち
行列から削除し、主プロセッサに対してタイムアウトと
なったタスクIDを報告する。この様な動作を行うこと
により主プロセッサは、一定時間間隔の単純な割り込み
動作から解放される。
FIG. 1 is a block diagram of the software timer management system of the present invention. In FIG. 1, a main processor 1 is connected to a timer management processor 2, and when a timer processing request is made by rough 1 to software running on the main processor, the timeout value of the timer and the running task ID
A timer processing request is given to the timer management processor. The timer management processor generates one management block corresponding to this timer processing request with the given timeout value and task ID, and registers it in the timer management queue. The timer management processor clears the timeout value of each management block every time a timer interrupt occurs,
When the value becomes 0, the management block is deleted from the timer management queue and the task ID that has timed out is reported to the main processor. By performing such operations, the main processor is freed from simple interrupt operations at fixed time intervals.

〔発明の効果〕〔Effect of the invention〕

以」二説明したように本発明は、ソフトウェアタイマの
管理を独立した専用のプロセッサで行うことにより、主
プロセッサの割り込みに対する負荷を相対的に低く抑え
ることかでき、またソフトウェアタイマ管理用プロセッ
サ側では、主な管理要因がタイマ割り込みのみと単純化
され、単一プロセッサでは対応できなかったような短い
時間間隔でのタイマ管理が可能となり、システム全体と
しては今まて対応できなかったような厳しいリアルタイ
ム処理にも対応が可能になるという効果かある。
As explained above, in the present invention, by managing the software timer with an independent dedicated processor, it is possible to keep the interrupt load on the main processor relatively low. , the main management factor is simplified to only timer interrupts, making it possible to manage timers at short time intervals that could not be handled by a single processor, and for the entire system to handle harsh real-time tasks that were previously impossible to handle. This has the effect of making it possible to handle processing as well.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例のソフトウェアタイマ管理
方式を示す構成図である。 ]・・・主プロセッサ、2・・・タイマ管理用プロセッ
サ。
FIG. 1 is a block diagram showing a software timer management system according to an embodiment of the present invention. ]...Main processor, 2...Timer management processor.

Claims (1)

【特許請求の範囲】[Claims] リアルタイムシステムにおけるタイマ管理において、プ
ロセッサのタイマ割り込みによる負荷を軽減させるため
に、主プロセッサとは独立したタイマ管理専用のプロセ
ッサを持ち、それぞれのプロセッサ間でタイマ情報に関
するデータの交換手段を有することを特徴とするソフト
ウェアタイマ管理方式。
In timer management in a real-time system, in order to reduce the load caused by timer interrupts on the processor, it has a processor dedicated to timer management independent of the main processor, and has a means for exchanging data regarding timer information between each processor. Software timer management method.
JP1212237A 1989-08-18 1989-08-18 Software timer control system Pending JPH0375808A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1212237A JPH0375808A (en) 1989-08-18 1989-08-18 Software timer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1212237A JPH0375808A (en) 1989-08-18 1989-08-18 Software timer control system

Publications (1)

Publication Number Publication Date
JPH0375808A true JPH0375808A (en) 1991-03-29

Family

ID=16619238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1212237A Pending JPH0375808A (en) 1989-08-18 1989-08-18 Software timer control system

Country Status (1)

Country Link
JP (1) JPH0375808A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6717800B2 (en) 2001-04-06 2004-04-06 Funai Electric Co., Ltd. Shield plate mounting apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6717800B2 (en) 2001-04-06 2004-04-06 Funai Electric Co., Ltd. Shield plate mounting apparatus

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