JPH037407A - Output circuit - Google Patents

Output circuit

Info

Publication number
JPH037407A
JPH037407A JP1142568A JP14256889A JPH037407A JP H037407 A JPH037407 A JP H037407A JP 1142568 A JP1142568 A JP 1142568A JP 14256889 A JP14256889 A JP 14256889A JP H037407 A JPH037407 A JP H037407A
Authority
JP
Japan
Prior art keywords
current
circuit
differential amplifier
amplifier circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1142568A
Other languages
Japanese (ja)
Inventor
Akira Kageyama
章 影山
Hideaki Obara
小原 英明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP1142568A priority Critical patent/JPH037407A/en
Publication of JPH037407A publication Critical patent/JPH037407A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce the current consumption and to attain a stable circuit by connecting a resistor to a differential amplifier in place of a current source supplying its operating current to the differential amplifier circuit. CONSTITUTION:A differential amplifier circuit 6 to which a resistor R2 is connected in place of the use of a constant current source is employed for the output circuit. When a voltage at an output terminal 5 changes negatively (less than Vcc/2), an emitter level of transistors(TRs) Q2, Q3 is decreased and a voltage across the resistor R2 is increased and a circuit I2 flowing thereto is increased. Moreover, when the output is changed positively (more than Vcc/2), the emitter level of the TRs Q2, Q3 is increased and the current I2 is decreased. When the voltage at the output terminal 5 changes positively in this way (no large base current is required for a TR Q7), the current I2 is decreased. Then no undesired current flows, resulting in decreasing the current consumption and the differential amplifier circuit 3 is turned off through the decrease in the current I2 and the possibility of adverse effect such as oscillation of the differential amplifier circuit 3 on other circuits is precluded and the stability of the circuit is improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、演算増幅器の出力回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an output circuit for an operational amplifier.

〔従来の技術〕[Conventional technology]

この種の出力回路として、第3図に示す回路がある。こ
の回路は、ベースが入力端子1に接続される入力トラン
ジスタQl、そのトランジスタQ1によって制御される
トランジスタQ2〜Q5と定電流源2からなる差動増幅
回路3、定電流源4、その定電流源4、差動増幅回路3
及び入力トランジスタQ1によってプッシュプル動作す
る出力トランジスタQ6、Q7、アイドリング電流調整
用のダイオードD1、トランジスタQ2の飽和防止用の
抵抗R1からなる。
As this type of output circuit, there is a circuit shown in FIG. This circuit consists of an input transistor Ql whose base is connected to an input terminal 1, a differential amplifier circuit 3 consisting of transistors Q2 to Q5 controlled by the transistor Q1, and a constant current source 2, a constant current source 4, and the constant current source. 4. Differential amplifier circuit 3
It also includes output transistors Q6 and Q7 that operate in push-pull mode using the input transistor Q1, a diode D1 for adjusting idling current, and a resistor R1 for preventing saturation of the transistor Q2.

この回路は、差動増幅回路3と出力トランジスタQ7が
ボルテージホロワ接続され、従ってトランジスタQ2の
ベース電圧がトランジスタQ3のベースに、つまり出力
端子5に現れる。
In this circuit, the differential amplifier circuit 3 and the output transistor Q7 are connected in a voltage follower manner, so that the base voltage of the transistor Q2 appears at the base of the transistor Q3, that is, at the output terminal 5.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところで、この回路では、トランジスタQ7のベース電
流が定電流源2から供給されることになるが、このベー
ス電流は出力端子5からの最大吸込み電流を供給するに
充分でなければならない。
Incidentally, in this circuit, the base current of the transistor Q7 is supplied from the constant current source 2, and this base current must be sufficient to supply the maximum sink current from the output terminal 5.

つまりこの定電流源2の電流値■、は少なくともこのベ
ース電流を供給できる値でなければならないが、定電流
源の性質上そこから供給される電流は常に一定の値の電
流であり、トランジスタQ7の非動作時でも同様である
In other words, the current value of constant current source 2 must be at least a value that can supply this base current, but due to the nature of constant current sources, the current supplied from it is always a constant value current, and transistor Q7 The same applies even when the unit is not operating.

従って、トランジスタQ7の最大吸込み動作以外の時は
無駄な電流を供給していることになり、不経済であった
。また、出力端子5が負側(Vcc/2以下)から正側
(Vcc/2以上)に変化した際にも定電流源2によっ
て差動増幅回路3が動作を継続するので回路に発振等の
悪影響を及ぼす虞があった。
Therefore, when the transistor Q7 is not in its maximum suction operation, a wasteful current is supplied, which is uneconomical. Further, even when the output terminal 5 changes from the negative side (Vcc/2 or less) to the positive side (Vcc/2 or more), the differential amplifier circuit 3 continues to operate by the constant current source 2, so that oscillations etc. There was a risk of adverse effects.

本発明はこのような点に鑑みてなされたものであり、そ
の目的は消費電流を低減すると共に、回路の安定化を達
成した出力回路を提供することである。
The present invention has been made in view of these points, and its purpose is to provide an output circuit that reduces current consumption and achieves circuit stability.

〔課題を解決するための手段〕[Means to solve the problem]

このために本発明は、正側出力トランジスタとの組合せ
でブツシュプル動作を行う負側出力トランジスタと、該
負側出力トランジスタとの組合せでボルテージホロワ回
路を構成する差動増幅回路とを含む出力回路において、
上記差動増幅回路に動作電流を供給する電流源を抵抗で
構成した。
To this end, the present invention provides an output circuit including a negative output transistor that performs a push-pull operation in combination with a positive output transistor, and a differential amplifier circuit that configures a voltage follower circuit in combination with the negative output transistor. In,
A current source that supplies an operating current to the differential amplifier circuit was configured with a resistor.

また、上記差動増幅回路の上記電流源に接続される差動
接続の2個のトランジスタのエミッタに各別の抵抗を直
列接続することができる。
Further, different resistors can be connected in series to the emitters of two differentially connected transistors connected to the current source of the differential amplifier circuit.

〔実施例〕〔Example〕

以下、本発明の実施例について説明する。第1図はその
一実施例の出力回路を示す図である。第3図と同一のも
のには同一の符号を付した。本実施例では、第3図にお
ける定電流源2に代えて抵R2を接続した差動増幅回路
6を使用する。
Examples of the present invention will be described below. FIG. 1 is a diagram showing an output circuit of one embodiment. Components that are the same as those in FIG. 3 are given the same reference numerals. In this embodiment, a differential amplifier circuit 6 to which a resistor R2 is connected is used in place of the constant current source 2 in FIG. 3.

従って、出力端子5の電圧が負側(Vcc/2以下)に
変化した場合、トランジスタQ2、Q3のエミッタ電位
が下がって抵抗R2の両端の電圧が高くなり、そこを流
れる電流I2が増大する。
Therefore, when the voltage at the output terminal 5 changes to the negative side (below Vcc/2), the emitter potential of the transistors Q2 and Q3 decreases, the voltage across the resistor R2 increases, and the current I2 flowing therein increases.

また、出力が正側(Vcc/2以上)に変化した場合は
、トランジスタQ2、Q3のエミッタ電位が上がり、電
流■2は減少する。
Furthermore, when the output changes to the positive side (Vcc/2 or higher), the emitter potentials of the transistors Q2 and Q3 rise, and the current 2 decreases.

このように、出力端子5の電圧が正側に変化する(トラ
ンジスタQ7に大きなベース電流を必要としない。)場
合には電流I2が減少するので、不必要な電流は流れず
消費電流を減少させることができる。また、この電流1
2が減少することにより差動増幅回路3はオフの状態と
なり、この差動増幅回路3が他の回路に発振等の悪影響
を及ぼす虞がなくなり、回路の安定性の向上につながる
In this way, when the voltage at the output terminal 5 changes to the positive side (transistor Q7 does not require a large base current), the current I2 decreases, so unnecessary current does not flow, reducing current consumption. be able to. Also, this current 1
2 is reduced, the differential amplifier circuit 3 is turned off, and there is no possibility that the differential amplifier circuit 3 will have an adverse effect such as oscillation on other circuits, leading to improvement in the stability of the circuit.

ここで、消費電流の減少について考察する。第3図で示
した回路では、トランジスタQ7を最大に駆動するに必
要なベース電流11は、その時の出力端子5から吸い込
む電流をI。、トランジスタQ8の電流増幅率をh2o
とすると、I * −In / hrE・=(1)とな
る、そして、定電流源2の電流I、は(11式の電流I
mと同じに設定され、これは出力に関係なく流れる。
Here, we will consider the reduction in current consumption. In the circuit shown in FIG. 3, the base current 11 required to drive the transistor Q7 to the maximum is the current I drawn from the output terminal 5 at that time. , the current amplification factor of transistor Q8 is h2o
Then, I*-In/hrE・=(1), and the current I of constant current source 2 is (current I of equation 11)
is set equal to m, which flows regardless of the output.

一方、本実施例の回路では、第3図の回路と同様の駆動
能力を持たせるには、抵抗R2を流れる電流I2に、 Itり1゜/hFE            ・・・(
2)のように、(11式と同様の電流が必要となるが、
これはトランジスタQ7を最大駆動する時のみ流れる電
流となる。
On the other hand, in the circuit of this embodiment, in order to have the same driving ability as the circuit of FIG.
As in 2), the same current as in equation 11 is required, but
This current flows only when the transistor Q7 is driven to the maximum.

ここで、定常状態における電流を比較してみると、第3
図の回路では、常に電流11が流れるが、本実施例の回
路では、 It = (Vcc−(Vstt +Vcc/ 2) 
) /R2”’ V cc/ 2  V mcs   
      ・・・(3)となる。vmtzはトランジ
スタQ3のベース・エミッタ間電圧である。よって、定
常状態における必要電流比ΔIは、 ΔI = (to / )iri)   (Vcc/ 
2  V!lE3 )・・・(4)と なり、この分だけ電流が減少することになる。
Here, when comparing the current in steady state, the third
In the circuit shown in the figure, a current 11 always flows, but in the circuit of this embodiment, It = (Vcc-(Vstt +Vcc/2)
) /R2''' V cc/ 2 V mcs
...(3). vmtz is the base-emitter voltage of transistor Q3. Therefore, the required current ratio ΔI in steady state is ΔI = (to / )iri) (Vcc/
2V! lE3 )...(4), and the current decreases by this amount.

第2図は別の実施例の出力回路を示す図である。FIG. 2 is a diagram showing an output circuit of another embodiment.

この実施例では、トランジスタQ2、Q3のエミッタと
抵抗R2との間に、別の抵抗R3、R4を直列接続した
差動増幅回路7を使用している。
This embodiment uses a differential amplifier circuit 7 in which other resistors R3 and R4 are connected in series between the emitters of transistors Q2 and Q3 and resistor R2.

この回路によれば、差動増幅回路7の利得が下がり、更
に回路の安定化を図ることができる。
According to this circuit, the gain of the differential amplifier circuit 7 is reduced, and further stabilization of the circuit can be achieved.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、出力電圧に応じ
て差動増幅回路の動作電流が変化し、消費電流の低減化
及び回路の安定化を達成することができるという利点が
ある。
As described above, the present invention has the advantage that the operating current of the differential amplifier circuit changes depending on the output voltage, thereby reducing current consumption and stabilizing the circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の出力回路の回路図、第2図
は別の実施例の同回路図、第3図は従来の同回路図であ
る。 ■・・・入力端子、2・・・定電流源、3・・・差動増
幅回路、4・・・定電流源、5・・・出力端子、6.7
・・・差動増幅回路。
FIG. 1 is a circuit diagram of an output circuit according to one embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment, and FIG. 3 is a conventional circuit diagram. ■...Input terminal, 2... Constant current source, 3... Differential amplifier circuit, 4... Constant current source, 5... Output terminal, 6.7
...Differential amplifier circuit.

Claims (2)

【特許請求の範囲】[Claims] (1)、正側出力トランジスタとの組合せでプッシュプ
ル動作を行う負側出力トランジスタと、該負側出力トラ
ンジスタとの組合せでボルテージホロワ回路を構成する
差動増幅回路とを含む出力回路において、上記差動増幅
回路に動作電流を供給する電流源を抵抗で構成したこと
を特徴とする出力回路。
(1) In an output circuit including a negative output transistor that performs push-pull operation in combination with a positive output transistor, and a differential amplifier circuit that configures a voltage follower circuit in combination with the negative output transistor, An output circuit characterized in that a current source for supplying an operating current to the differential amplifier circuit is constituted by a resistor.
(2)、上記差動増幅回路の上記電流源に接続される差
動接続の2個のトランジスタのエミッタに各別の抵抗を
直列接続したことを特徴とする特許請求の範囲第1項記
載の出力回路。
(2) According to claim 1, each resistor is connected in series to the emitters of two differentially connected transistors connected to the current source of the differential amplifier circuit. Output circuit.
JP1142568A 1989-06-05 1989-06-05 Output circuit Pending JPH037407A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1142568A JPH037407A (en) 1989-06-05 1989-06-05 Output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1142568A JPH037407A (en) 1989-06-05 1989-06-05 Output circuit

Publications (1)

Publication Number Publication Date
JPH037407A true JPH037407A (en) 1991-01-14

Family

ID=15318353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1142568A Pending JPH037407A (en) 1989-06-05 1989-06-05 Output circuit

Country Status (1)

Country Link
JP (1) JPH037407A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010028277A (en) * 2008-07-16 2010-02-04 New Japan Radio Co Ltd Output circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010028277A (en) * 2008-07-16 2010-02-04 New Japan Radio Co Ltd Output circuit

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