JPH0373500A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To make it possible to easily confirm the using state of a redundancy cell line or row from the external by providing the semiconductor storage device with a redundancy cell using state detecting means, a data output preventing means and a test signal generating means. CONSTITUTION:When the test signal generating means 1C generates a test signal FDE for setting up a test mode state, the data output preventing means 1B prevents stored data from being outputted to the external. The detecting means 1A detects whether the redundancy cell group is used or not based upon a signal indicating the information of a storage element storing a defective address and the addresses of a redundancy cell group and the test signal and sends the detection signal to an output buffer, and at the time of using the detection signal, the corresponding address of the cell group including the defective cell is also detected by the detecting means 1A. Consequently, the using state of the redundancy cell group can be easily confirmed from the external.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device in which a group of redundant cells is H.

(Prior Art) In a semiconductor memory device in which memory cells are arranged in rows and columns, in general, in order to improve manufacturing yield, even if there is a defective cell in the row or column, a defective cell is replaced in the row or column. A plurality of redundant cell rows or columns, that is, redundant cell groups, are provided to replace the defective cell row or column with the redundant cell row or column.

FIG. 7 shows a semiconductor memory device that performs the above-mentioned replacement. This semiconductor memory device has m redundant cell rows Z1. ...Zl
have. Through the address buffer 71, the address A1. . . . Ao is sent to redundant cell row selection circuit 72 and row decoder 73. This address human power As-・
. . , when An indicates a cell row other than the defective cell row Xp in the memory cell array, only the row decoder 73 operates and the address input A1. ...The cell row indicated by An is selected. In contrast, address human-powered AI...
When All indicates the defective cell row XN, the redundant cell row selection circuit 72 operates to stop the operation of the row decoder 73 that selects the defective cell rows X and 11. A command signal SPE is sent to the row decoder 73, and a selection signal SP is output for selecting a corresponding cell row Z of the redundant storage cell row 77 in which the defective cell row XI is to be replaced.

The configuration of this redundant cell row selection circuit 72 is shown in FIG. This redundant cell row selection circuit 72 has m row selection circuits SRj (j-1, . . . river) and one OR circuit 85, as shown in FIG. This row selection circuit SR, addresses A1. . . . The selection signal SP, which selects the redundant cell row Z based on An, is J
It is a circuit that outputs J outputs, and has (n+1) polysilicon fuses Fj, Flj'...
...has Foj.

For this reason, when the redundant cell row 2 is to replace the defective cell row Xi, the Bolin Rifcon fuse F of the row selection path SR is blown by a laser in advance. In addition, polysilicon fuse F1j (i-1,...nl j
-1,...m), the polysilicon fuse F is blown and the redundant cell row Z has χIJ
J
an address A + indicating the corresponding defective cell row X;
...When the value of bit A1 of ρ A is "0", it is fused by the γ-me laser.

By doing this, when the address of the defective cell 41XO is input, the signal 5PEj in the row selection circuit SR is
SAISEj (i-1,-n) are all “1”,
The redundant cell row Z corresponding to this defective cell row Xp by 1.3 is selected.The value of the selection i=SP becomes "1" and the row selection circuit SR, or J
J et al. will be output. The OR circuit 85 operates based on m selection signals SP- (j=1...n) and a stop command signal SPE that stops the operation of the row decoder.
Output.

As described above, the corresponding redundant cell row Z is selected instead of the defective cell row Xn. In addition, in the row selection circuit SR, (j=1...m), the signal SPE is generated when the polysilicon fuse F is blown.
The signal AiFJ ('-', . . . n) is a signal indicating whether or not the polysilicon fuse FIj is blown.

Further, some of the above-mentioned conventional semiconductor devices are provided with a determination circuit as shown in FIG. 9 for externally determining whether or not a redundant cell row has been used. It is assumed that the polysilicon fuse F of this determination circuit is blown by a laser at the same time as the aforementioned polysilicon fuse is blown when a redundant cell is used. And this i111
1 constant is the address pin of any one of the address bins into which At, . . . An is input, for example A1.
It shall be connected to the pad 91 of. By shifting in this way, the address pin A to which the determination circuit is connected
Whether or not a redundant cell row is being used can be externally determined at t-11 by whether a leakage current flows to the address pin A when a predetermined voltage is applied to the address pin A.

(Problem to be Solved by the Invention) However, when the above-mentioned determination circuit is used, it is difficult to determine externally which redundant cell row is used and what is the address of the defective cell row corresponding to the redundant cell row used. This was extremely inadequate for failure analysis during the development of semiconductor memory devices.

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a conductive memory device that allows the use status of redundant cell rows or columns to be known from the outside.

[Structure of the invention]

(F stage for solving the problem) The present invention provides a method for selecting a cell group containing the defective cell when a defective cell is included in the memory cells arranged in a matrix. In a semiconductor memory device that switches to and selects a redundant cell group that has been switched to a redundant cell group that has been switched, and stores the address of the redundant cell group that has been switched and the address of a cell group that includes the corresponding defective cell in a nonvolatile memory element, the semiconductor memory device is in a test mode state. Test to generate t=°Test 1: When the number is generated manually and the normal mode state is set, the data stored in the memory cell is outputted to the outside via the output pad, and the test mode state is set. A data output prevention means for preventing the stored data from being outputted to the outside when
It detects whether the redundant cell group is used or not based on the signal indicating the redundant cell group and the test signal, and sends a detection signal to the output pad, and also sends the address of the cell group including the corresponding defective cell when the redundant cell group is used. The present invention is characterized in that it includes a detection means for detecting.

(Function) According to the semiconductor memory device of the present invention configured as described above, an address input signal, a signal indicating information on a memory element storing a defective address and an address of a redundant cell group, and a test signal are used. Whether or not the redundant cell group is used is detected by the detection-f stage, and a detection signal is sent to the output buffer, and when the redundant cell group is used, the address of the cell group containing the defective cell corresponding to χ is also detected by the detection means. detected by.

This allows the usage status of the redundant cell group to be easily known from the outside.

(Embodiment) A first embodiment of a semiconductor memory device according to the present invention will be described with reference to FIGS. 1 to 3. The semiconductor memory device of this first embodiment is the semiconductor memory device shown in FIG.
A, a data output prevention circuit IB, and a test signal generation circuit IC are newly provided (see FIG. 1).

Note that the redundant cell row selection circuit 72 of the semiconductor memory device shown in FIG. 7 has m row selection circuits SR, (
j−L...m), and each j] selection circuit sRj is located in the center.
Since (J −1, . . . m) has n+1 polysilicon fuses, the semiconductor memory device of this embodiment has m(n+1) bonosilicon fuses. Then, these nl(n+1) polysilicon fuses are numbered from rth1 to m(n+1) as shown in FIG. 3, and each polysilicon fuse PFk (
signal F Dk(k-1,...m (n+1)
)) is internally jl). Detection circuit I
A is m(n+1) NAND circuits NAk(k 1.
+ = m (n+1)), AND circuit AN1, and N
OT circuit NOT l, OR circuit OR1, AND circuit AN2, PMO5) transistor TPt, NMOS)
It has a transistor TN1. Each NAND circuit NA
h (k-1,...m (n+1)) operates based on 0 human input signals BIk'...Bak and a signal FDk that indicates 5R whether or not the polysilicon fuse PFk is blown And operation C1 is AND circuit A
Send to N1. Here a is 2 a-1< m (
It is an integer that satisfies n+ 1 )≦2. Each NAND
Assume that the i-th input BIk of the circuit NAk (k-1,·m (n +1)) is selected from the i-th bit A of the addresses A1, . . . A, or the value of 61.

Then, for a certain specific k, the values of 0 input signals Blk'...Bffk of the NAND circuit NAk are all "1".
When taking the value of “, other NAND circuits NA, (j k k
) is selected so that the human input signal B1゜...B - (j4k)ifI does not become 1''. Then, for a specific polysilicon fuse PFkl: and for a specific human input signal BIk'
. . . When Bak is manually input via the address bin, the output of the NAND circuit N A k is ``(J'' and t, so that another human input signal is input (11 becomes ``1'').

AND circuit AN, is m (n+1)Z NAND circuit N
It operates based on the output of Ak (k-1, -m (n+1)), and the operation signal is sent to the OR circuit OR and the AND circuit AN.
Send to 2. The OR circuit OR, operates based on the test signal FDE sent from the test signal generation circuit IC, which will be described later, via the NOT circuit NOT, and the output of the AND circuit AN1, and sends the operating signal to the gate of the transistor TPl (PMO8). Send. AND circuit AN2 receives test signal FD
It operates based on the output of E and the AND circuit AN, and sends an operation signal to the NMO3h transistor TN.

The drain of the PMO5+ transistor TP and the drain of the NMOS transistor are connected, and this connected intermediate node is connected to an output pad D that outputs stored data.

A weight voltage V is connected to the source of the PMOS transistor 'r P , and a source of the transistor C TN is grounded.

On the other hand, the data output prevention circuit IB includes a NOT circuit NOT, an OR circuit OR2, an AND circuit ANa, and a PMO.
5) Transistor TP2 and 8MO5) Transistor T N
2.

The OR circuit OR2 receives the inverted signal OE of the signal OE sent from the output enable bin and the NOT circuit N0T2.
The PMOS transistor T1) operates based on the data output sent from the sense amplifier via the PMOS transistor T1).
Send to gate 2.

AND circuit A N 3 connects signal OE and NOT circuit N0T.
It operates based on the data output sent from the sense amplifier via the NMOS transistor TN.
Send to gate 2.

PMOS transistor TP2 and NMOS transistor T
N2 is connected in series, and its peak note is output pad D.
. connected to ut. Note that the source of the PMOS transistor TP2 is connected to the transistor 7Ii11Iλ', and the C source of the transistor TN2 is grounded.

The test signal generation circuit IC generates a test signal FDE for putting the 21' conductor memory device of the embodiment into a test mode for detecting the usage status of redundant cells, and is used for address inputs A, . . . One address human input signal (11-α+1...n)! is connected to the pad 21 of the other control bin, and the PMOS transistor T
P 3 and 8MO5) transistor TN and NOT
It has circuits N0T3 and N0T4 (see FIG. 2).

PMO9) transistor T P s and NMO8I transistor T Na are connected in series, and a power supply voltage V is applied to each gate. When a high voltage higher than the power supply voltage V is applied to the pad 21C, the C PMOS transistor becomes conductive, and a value of 1' is tested from the intermediate node where the PMO3I-transistor TP and the NMOS transistor TN3 are connected through the NOT circuits N0T3 and N0T4. Signal FDE is output.

Next, the operation of the first embodiment will be explained. Now, Porin Rico>
It is assumed that the fuse PF is blown. First, the value of the signal OE is set to "0" from the outside, and a voltage C higher than the power supply voltage V is applied to the pad 21. Then, in the data output prevention circuit 1B, the NMOS transistor T N 2 and the PMOS
The transistor T P 2 becomes non-conductive, and the data sent from the sense amplifier is not output to the outside via the output pad Dout.

Further, the value of the test signal FDE output from the test signal generation circuit IC becomes "1".

Next, address bin AJ, ...Aa (your value is '()'
Or apply a voltage that gives a signal of 1°. At this time, the address (, No. 4 B11°...B (Zl
When inputted manually, the output of the other NAND circuit NAj (j arrow 1) is "1". Therefore, the output of the AND circuit AN is "0". On the other hand, the value of the test signal FDH is "]"゛ζ Because it is N
The output of the OT circuit NOT is “0”! Therefore, OR circuit O
The output of R, is 0m.2), AND□ circuit A
The output of N2 becomes 0'. Then, PMO8) transistor TPl becomes conductive or NMO9) transistor TN becomes non-conductive, and the output pad D becomes conductive. ut becomes a high potential. Note that when the polysilicon fuse PF is not blown, the above-mentioned specific address manual signal B,...Bal
A11 Dressing bin A1. . . . Even if input via Aa, all NAND AND circuits AND1. Since the output of -m (n+1) becomes 1'', the output pad D.uL becomes a low potential.

In this way, rn (n+1) polysilicon fuses P Fk (k - L = m (n + 1))
II.
(2) This makes it possible to easily know the usage status of redundant cell rows from the outside, which is very effective for failure analysis.

A second embodiment of the semiconductor memory device according to the present invention will be described with reference to FIG. The conductive memory device of this second embodiment is a semiconductor device 1a shown in FIG. 7, which includes a redundant cell usage state detection circuit (hereinafter referred to as "detection 1" path 2A), a data output prevention circuit 2B, A test signal generation circuit (not shown) is newly provided.The detection circuit 2A has m(n
+1) AND circuits ANDk(k-1, -m (n+
1)), OR circuit OR, and PMOS transistor TP
41 and T P 42 and NMO5I-transistor N
MO3) transistors TN and TN42 and NOT
It is equipped with an OR circuit ORT4□. Each AND circuit AND.

is 0 input signals BlK, .
1 and sends an operating signal to the OR circuit OR.

OR circuit OR is m (n+1) AND circuits ANDk
(k-1,...m (n"1)), and sends an operating signal to each gate of the PMOS transistor TP and the NMO5h transistor TN4I (transistor TI)4. , T
P TN and T N 42 are connected in series. Then, the power supply voltage V is applied to the source of the transistor TP41, and the transistor T N 4 ? The C source of is grounded. Also, transistor TP4□
For example, a signal FD which is an inversion of the test signal FDE generated from the test signal generation circuit shown in FIG.
E is added, and a test signal FDE is added to the gate of the transistor T N 42. The output of the series circuit consisting of transistors TP41, TP42, TN and TN4□ is outputted to the outside from an intermediate node between transistors TP42 and TN41 via NOT circuit N0T4□.

The data output prevention circuit 2B is a PMOS transistor TP
43, TP44, and NMOS transistor T N
4a and T N 44 are connected in series. A power supply voltage V is applied to the drain side of the transistor TP43, and a C source side of the transistor TN44 is grounded. In addition, transistor TP4
No. 2 0E, which is an inverted version of the signal OE sent out from the output enable bin, is added to the gate of transistor TN44, and signal OE is added to the gate of transistor TN44. A data output signal sent from the four sense amplifiers is added to each gate of the transistors TP and TN43. In addition, the output of the data output prevention circuit 11 and the second circuit 2B is
It is output to the outside via the NOT circuit N0T4□.

Next, the operation of the second embodiment will be explained. Now, the explanation [11
It is assumed that the polysilicon fuse PF is blown to make it 1 iB. First, set the value of f6 OE to "0" from the outside, and set the value to "0" from the test signal generation circuit.
1" test No. 1° FDE is made constant. Then, in the data output rib 11 circuit 2B, the transistor TP
And T N 44 becomes semi-conductive 3, and the data sent from the sense amplifier is not outputted to the outside via the output pad D.

Next, address bin A1. ...The value of Aa is 0” or “1”
When the address signal B11゜...Bal is input manually, the output of the AND circuit AND becomes ``1#'' for a specific address input signal. The output of the AND circuit ANDj (j41) becomes O° regardless of whether or not the polysilicon fuse PF, (j41) is blown, that is, regardless of the value of the signal FD, (j41).

Therefore, the output of the OR circuit OR becomes "1", and the transistor T N 41 becomes conductive. -)), ja FDE
Since the value of is "1", the transistor TN42 is also conductive, so that the transistors TP and TN
The potential of the intermediate node between i and □ becomes "0". Therefore, the value "1" is passed through the NOT circuit N0T41.
The signal is outputted via the output pad D.

Note that when the polysilicon fuse PF1 is not blown, the above-mentioned specific address manual signal B11. ...B
Even if a1 is input manually via address bin AI, . . . Aa, all AND circuits AND, (k-1, . . . m(n
Since the output of +1)) is "O", the output bat D of u and shi. The potential level of 1 becomes "0".

In this way, it is possible to easily determine whether or not m (n+1) polysilicon fuses PFk (lc-1, -m (n+1)) are blown.
This makes it easy to know from the outside the ooze used in the redundant cell row, which is very effective for failure analysis.

A third embodiment of the semiconductor memory device according to the present invention will be described with reference to FIG. The semiconductor memory device of the third embodiment includes a redundant cell usage state detection circuit (hereinafter referred to as a detection circuit) 3A, a data output prevention circuit 3B, and a test circuit. A signal generation circuit (not shown) is provided.

The four detection paths 3A are PMO3) transistors TP5. , T
P52, and NMOS transistor TN5. , T
It includes a series circuit in which N s 2 are connected in series, and a NOT circuit N0T51. A signal FDE, which is an inverted version of the test signal FDE generated from the test signal generation circuit shown in FIG. 2, is added to the gate of the transistor TP5, and a test signal FDE is added to the gate of the transistor TNs2. There is.

Also, transistors TP52 and TN5. Stop the operation of the row decoder for each gate of 1. A stop command signal SPE is added. Then, transistors T P 51, T P 52, TN5 . , and T N
The output of the series circuit consisting of 52 is the transistor TP5.
From the intermediate node between ゜ and TN5□ N0TIi1 path N0T5
Output to the outside via □.

The data output prevention circuit 3B is a PMOS transistor TP
53, TP54, and NMO5) transistor TN53
, TN, are connected in series. A signal OE is added to the gate of the transistor TP53,
A signal OE is added to the gate of the transistor TN54. Further, data f3 sent from the sense amplifier is added to each gate of the transistors TP54 and T N 5a.

Next, the operation of the third embodiment will be explained. First, the value of the signal OE is set to ``0'' from the outside, and the test signal FDE having the value ``11'' is generated from the test signal generation circuit. Then, similarly to the second embodiment, transistors TP and T
N54 becomes non-conductive, and the data sent from the 3 sense amplifier is sent to the output pad DoU.
It will not be output to the outside via t.

Next, address inputs Ai, . . . Ao are applied manually via address pins AI-. Then, when this manually entered address indicates a defective cell row, the signal SP
Since the value of E is “1”, N0TI! ! l road N0T5□
The value of the output data outputted through is "1".

In this way, the address of the defective cell row can be known externally q(
becomes possible.

A fourth embodiment of the semiconductor memory device according to the present invention will be described with reference to FIG. The semiconductor memory device of this embodiment has a number of output bins greater than the number m of m redundant cell rows, and has a redundant cell usage state detection circuit (hereinafter referred to as a detection circuit) 4A for each redundant cell row. , (j−1,・
...m) and the data output prevention circuit 4B, (j-1,
...m). Each detection circuit 4A
j has the same 1# value as the detection circuit 3A shown in FIG. 5, and a selection signal SF3 for selecting the redundant cell row Zj is used instead of the human input signal SPE. Further, each data output prevention circuit 4Bj has the same configuration as the data output prevention circuit shown in FIG. The outputs are individual output pads D. Output via ut.

By doing this, when the address of a defective cell row is entered manually, it is possible to know which redundant cell row this defective cell row will be replaced with.

Although the above embodiments have been described with reference to redundant cell rows, the usage status of redundant cell columns can be easily known from the outside in the same way.

[Effect of light]

As described above, according to the present invention, the usage status of redundant cell rows or columns can be easily known from the outside.

This figure is a circuit diagram showing the configuration of the redundant cell row selection circuit shown in FIG. 7, and FIG. 9 is a circuit diagram showing a determination circuit for externally determining whether or not a redundant cell row is used.

IA: Redundant cell usage status detection circuit, IB: Data output prevention circuit, IC: Test signal generation circuit.

[Brief explanation of drawings]

Claims (1)

[Claims] When there is a defective cell in memory cells arranged in a matrix, when selecting a cell group including the defective cell, switching to a redundant cell group provided separately from the memory cells is provided. At the same time, a test signal is generated to enter a test mode state in a semiconductor memory device in which a non-volatile memory element stores the address of a switched redundant cell group and the address of a cell group including a corresponding defective cell. and a test signal generating means for outputting the data stored in the memory cell to the outside via an output pad when in the normal mode state, and preventing the stored data from being output to the outside when in the test mode state. a data output prevention means for detecting whether or not the redundant cell group is used based on an address input signal, a signal indicating information of the storage element storing a defective address and an address of the redundant cell group, and the test signal. A semiconductor memory device characterized in that it is provided with a detection means that sends a detection signal to the output pad and also detects an address of a cell group including a corresponding defective cell when in use.