JPH0373420U - - Google Patents

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Publication number
JPH0373420U
JPH0373420U JP13462289U JP13462289U JPH0373420U JP H0373420 U JPH0373420 U JP H0373420U JP 13462289 U JP13462289 U JP 13462289U JP 13462289 U JP13462289 U JP 13462289U JP H0373420 U JPH0373420 U JP H0373420U
Authority
JP
Japan
Prior art keywords
ceramic
laminated
end surface
films
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13462289U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13462289U priority Critical patent/JPH0373420U/ja
Publication of JPH0373420U publication Critical patent/JPH0373420U/ja
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の積層セラミツクのチツプ型コ
ンデンサを示めす図面、第２図はその平面図、第
３図は本考案の他の実施例、第４図は従来例、第
５図はその平面図である。 １……積層セラミツクのチツプ型コンデンサ、
２……セラミツク膜、３……内部電極、４……外
部電極、５……プリント絶縁基板、６……回路パ
ターン、７……別の回路パターン。 Fig. 1 is a drawing showing a multilayer ceramic chip capacitor of the present invention, Fig. 2 is a plan view thereof, Fig. 3 is another embodiment of the present invention, Fig. 4 is a conventional example, and Fig. 5 is the same. FIG. 1... Multilayer ceramic chip capacitor,
2... Ceramic film, 3... Internal electrode, 4... External electrode, 5... Printed insulating board, 6... Circuit pattern, 7... Another circuit pattern.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] セラミツク膜と内部電極を交互に積層し、その
後圧着、焼成、外部電極形成を行う積層セラミツ
クコンデンサにおいて、複数個の前記積層セラミ
ツク膜の最下端面或いは最上端面に前記セラミツ
ク膜よりも誘電率の低い誘電体層を添着して一体
構成する積層セラミツクのチツプ型コンデンサ。 In a laminated ceramic capacitor in which ceramic films and internal electrodes are alternately laminated, and then pressure bonded, fired, and external electrodes are formed, the lowermost end surface or the uppermost end surface of the plurality of laminated ceramic films has a dielectric constant lower than that of the ceramic film. A multilayer ceramic chip capacitor that is integrally constructed with a dielectric layer attached.
JP13462289U 1989-11-20 1989-11-20 Pending JPH0373420U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13462289U JPH0373420U (en) 1989-11-20 1989-11-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13462289U JPH0373420U (en) 1989-11-20 1989-11-20

Publications (1)

Publication Number Publication Date
JPH0373420U true JPH0373420U (en) 1991-07-24

Family

ID=31681947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13462289U Pending JPH0373420U (en) 1989-11-20 1989-11-20

Country Status (1)

Country Link
JP (1) JPH0373420U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015065414A (en) * 2013-08-30 2015-04-09 太陽誘電株式会社 Multilayer ceramic capacitor
JP2018088534A (en) * 2012-07-20 2018-06-07 サムソン エレクトロ−メカニックス カンパニーリミテッド． Laminated chip electronic component, board for mounting the same, and packing unit thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018088534A (en) * 2012-07-20 2018-06-07 サムソン エレクトロ−メカニックス カンパニーリミテッド． Laminated chip electronic component, board for mounting the same, and packing unit thereof
JP2015065414A (en) * 2013-08-30 2015-04-09 太陽誘電株式会社 Multilayer ceramic capacitor

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