JPH0372682A - Non-volatile semiconductor memory and its manufacture - Google Patents

Abstract

PURPOSE:To realize electric erasing without increasing the leak current between a source region and a semiconductor substrata, by constituting a source region or a drain region in a three-fold structure at an overlapping part with a floating gate electrode, which structure is composed of a high concentration (n<+>) n-type semiconductor outer layer, a low concentration (n<->) n-type semiconductor middle layer, and a high concentration (n<++>) n-type semiconductor inner layer whose concentration is higher than the outer layer. CONSTITUTION:A source region 7 has a three-fold structure at the part different from a floating gate electrode 3, which structure is composed of the following; an outer layer 73 composed of a high concentration (n<+>) n-type semiconductor region, a middle layer 72 composed of a low concentration (n<->) p-type semiconductor region, and an inner layer 71 composed of a high concentration (n<++>) n-type semiconductor region whose concentration is higher than that of the outer layer 73. A drain region 8 has a two-fold structure at the part overlapping with the floating gate electrode 3, which structure is composed of the following; an outer layer 82 composed of a high concentration (p<+>) p-type semiconductor region and an inner layer 81 composed of a very high concentration (n<++>) n-type semiconductor region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to non-volatile semiconductor memories, and more particularly to electrically programmable and erasable semiconductor memories, so-called EEP-
It relates to technology that is effective when applied to ROM, for example 2.
The present invention relates to a technology that is effective for use in flash-type EEP-ROMs having a layered gate structure.

[Prior art] Conventional non-volatile semiconductor memories of this type have, for example,
As shown in the figure, a floating gate electrode 3 is formed on a p-type (first conductivity type) silicon semiconductor substrate with a first gate insulating film 2 interposed therebetween, and a second gate electrode is formed on the floating gate electrode 3. A control gate electrode 5 formed through the gate insulating film 2 and a control gate electrode 5 formed across the channel region 6 under the floating gate electrode 3.
type (second conductivity type) source region 7 and train region 8
By applying a write voltage or an erase voltage, memory information is written or erased (for example, IEDM 85 pp616-61).
9. A 5INGLE TRANSISTOREE
PROM CELI, AND ITS IMPL
EMENTATIONIN A 512K EE
(See P-ROM (1985)).

Writing in the above-mentioned nonvolatile semiconductor memory is performed by applying a positive voltage (for example, 12 V) to the control gate electrode 5;
This is performed by applying a positive voltage (for example, -6V) to the drain D (or source S) side. In this case, hot electrons are injected into the first gate insulating film 2 from the drain D (or source) side, thereby accumulating negative charges in the floating gate FG.

Further, erasing is performed by applying a positive high voltage erasing voltage (for example, 12 V) to the source (or drain) S side. In this case, electrons are tunnel-emitted from the floating gate FG to the source S side, thereby releasing the charges accumulated in the floating gate FG.

[Problems to be Solved by the Invention] However, the inventors have found that the above-mentioned technique has the following problems.

That is, in the nonvolatile semiconductor memory mentioned above,
In order to shorten the erasing time, it is effective to make the gate insulating film 2 thinner and to increase the impurity concentration in the source region to increase the electric field strength between the source region and the floating gate electrode 3.

If the electric field strength is large, the tunnel current increases and the discharge of the accumulated charge in the floating gate electrode 3 is accelerated, thereby shortening the erasing time.

However, when the gate insulating film 2 is made thinner, when a relatively high erase voltage is applied between the source region 7 and the floating gate electrode 3, the portion of the source region 7 on the semiconductor substrate 1 side becomes depleted due to the strong electric field.
n) state, and due to this depletion state, electrons tunnel into the source region (interband tunneling), thereby generating holes. These holes flow to the semiconductor substrate l side, causing a leakage current between the source region 7 and the substrate 1.

The magnitude of this leakage current is, for example, when the gate insulating film 2 is 1
If the oxide film has a thickness of about 0 nm and the erase voltage applied to the source region 7 is about 12 V, it will be 10-8 A or more per memory element. For this reason,
For example, in an LM bit EEP-ROM, the total leakage current is 10-2 A or more. Such a large leakage current causes the problem of significantly increasing wasteful power consumption, but even more problematic is the generation of erase voltage inside the semiconductor memory in order to operate with a single power supply voltage of 5V. This means that it becomes impossible in terms of current capacity.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for shortening the erasing time of an electrically erasable nonvolatile semiconductor memory without increasing leakage current between a source region and a semiconductor substrate.

Another object of the present invention is to provide a technique for shortening the erasing time of an electrically erasable nonvolatile semiconductor memory by increasing the withstand voltage between the source region and the semiconductor substrate.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, the source (or drain) region is at least overlapped with the floating gate electrode.
An outer layer consisting of a high concentration (n+) n-type semiconductor region, an intermediate layer consisting of a low concentration (n-) n-type semiconductor region, and an n-type semiconductor region having at most a higher concentration (n++) than the outer layer. It has a triple structure with an inner layer consisting of

[Operation] According to the above-described means, first, the n of the semiconductor region of the inner layer is
The high type concentration suppresses depletion in the floating gate electrode side portion of the source region. Thereby, the electric field strength between the source region and the floating gate electrode can be increased, and the tunnel region for erasing can be smoothly increased.

Furthermore, since the n-type concentration of the semiconductor region of the intermediate layer is low, the depletion layer tends to expand in this portion. Thereby, the breakdown voltage between the source region and the semiconductor substrate can be increased.

Holes are generated due to depletion in a part of the intermediate layer consisting of the high-concentration (n+) n-type semiconductor region and the low-concentration semiconductor region in the inner layer. Outflow to the semiconductor substrate side is prevented by the outer layer consisting of.

This achieves the objective of shortening the erasing time of an electrically erasable nonvolatile semiconductor memory without increasing leakage current between the source region and the semiconductor substrate.

[Examples] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

In each figure, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows the main parts of a nonvolatile semiconductor memory according to an embodiment of the present invention.

The nonvolatile semiconductor memory partially shown in the figure is configured as an EEP-ROM with a two-layer gate structure, and first, a first gate is placed on a p-type (first conductivity type) silicon semiconductor substrate 1. A floating gate electrode 3 formed through an insulating film 2 and this floating gate electrode 3
A control electrode 5 formed on the top via the second gate insulating film 4 and an n-type (second conductivity type) formed sandwiching the channel region 6 under the bloating gate electrode 3.
A source region 7 and a drain region 8 form an electrically writable and erasable memory element.

Here, the source region 7 has an outer layer 73 made of a highly doped (n+) n-type semiconductor region and an intermediate layer made of a lightly doped (n-) p-type semiconductor region in a portion different from the floating gate electrode 3. 72 and an inner layer 71 consisting of an n-type semiconductor region with a higher concentration (n++) at most than the outer layer 73.

On the other hand, in the portion overlapping with the floating gate electrode 3, the drain region 8 has an outer layer 82 made of a p-type semiconductor region with a high concentration (p+) and an inner layer 81 made of an n-type semiconductor region with a concentration of at most (n++). It has a double structure.

In the non-volatile semiconductor memory having the above element structure, firstly, the n-type concentration of the semiconductor region forming the inner layer 71 of the source region 7 is set to the maximum concentration (n++), so that the source region 7 and the floating Depletion on the side of the gate electrode 3 is suppressed. Thereby, the electric field strength between the source region 7 and the floating gate electrode 3 can be increased, and the tunnel current for erasing can be smoothly increased.

In addition, n of the semiconductor region forming the intermediate layer 72 of the source region 7
Since the type concentration (n-) is low, the depletion layer tends to expand in this portion. As a result, the source area 7
The breakdown voltage between the semiconductor substrate 1 and the semiconductor substrate 1 can be increased.

In this case, the intermediate layer 72 made of a low concentration semiconductor region
generates a hole due to depletion, but this hole is
Outflow to the semiconductor substrate side 1 is prevented by the outer layer 73 made of a highly concentrated (n+) n-type semiconductor region.

This makes it possible to shorten the electrical erasing time of the nonvolatile semiconductor memory without increasing the leakage current between the source region 7 and the semiconductor substrate 1.

FIG. 2 shows a first embodiment of the main part of the method for manufacturing the nonvolatile semiconductor memory shown in FIG.

In the figure, first, as shown in (A), low concentration (p
-), a first group insulation film 2 made of a silicon oxide film, a floating gate electrode 3, a second gate insulation film 4, and a control gate electrode 5 are sequentially stacked on a p-type silicon semiconductor substrate 1 of A gate electrode having a two-layer structure is formed by overlappingly cutting this stacked body by selective etching.

Thereafter, an outer layer 71 made of a high concentration (n+) n-type semiconductor region is formed in a portion that will become the source region 7 by ion implantation of an impurity imparting n-conductivity such as phosphorus. This n
The formation of the type semiconductor region is carried out in a self-aligned manner using the overlapping two-layer gate electrodes 3 and 5 as a mask. In this case, in order to cause the outer layer 7 to deeply penetrate under the gate electrode 3, ion implantation may be performed at a relatively high energy, for example, 200 keys, from an oblique direction of, for example, about 45 degrees.

11- Next, as shown in (B), the outer layer 7 is ion-implanted with an impurity imparting P conductivity such as boron into the outer layer 71 and the portion that will become the drain region 8.
An intermediate layer 72 consisting of a low concentration (n-) n-type semiconductor region formed by diluting n-conductivity with p-conductivity is formed inside the drain region 8. An outer layer 82 consisting of a P-type semiconductor region is formed. The n-type semiconductor region 71 and the p-type semiconductor region 82 are also formed in a self-aligned manner using the two layers of gate electrodes 3 and 5 as masks.

After this, as shown in (C), the intermediate layer 7 of the source region 7 is
Inner JWs 71 and 81 made of n-type semiconductor regions with a concentration of at most (n ++) are formed by ion implantation of n-conductivity imparting impurities such as arsenic into the outer layer 82 of the drain region 8 and the outer layer 82 of the drain region 8, respectively. The selective formation of the inner layers 71 and 81 is also performed in a self-aligned manner using the two layers of gate electrodes 3 and 5 as masks.

Further, as shown in (D), sidewall spacers 91 are formed on the two-layer gate electrodes 3 and 5 which have been overlapped 2- by a known method, and this sidewall spacer 91 is used as a part of the mask. By self-alignment, each inner layer 71 .
n-type semiconductor regions 711 and 81 for making contact with the source and drain electrodes, respectively.
↓1 is formed at high concentration (n+).

By going through the steps described above, a nonvolatile semiconductor memory having an element structure as shown in FIG. 1 can be obtained.

FIG. 3 shows a second embodiment of the main part of the method for manufacturing the nonvolatile semiconductor memory shown in FIG.

In the figure, first, as shown in (A), low concentration (p
A first gate insulating film 2 made of a silicon oxide film, a floating gate electrode 3, a second gate insulating film 4, and a control gate electrode 5 are sequentially laminated on a p-type silicon semiconductor substrate 1'' (2). A gate electrode having a two-layer structure is formed by cutting the body overlappingly by selective etching.

Thereafter, a portion of the semiconductor substrate that will become the source region 7 is selectively dug down by etching.

Next, as shown in FIG. 7B, a highly concentrated (n+) n-type semiconductor region is formed by ion implantation in the portion dug out by etching, thereby forming the outer layer 73.
form.

Thereafter, as shown in (C), a low concentration (n-) n-type silicon semiconductor is selectively epitaxially grown on the outer layer 73 formed, thereby forming the intermediate layer 73.
172 is formed.

Further, as shown in FIG. 3D, in the source region 7, an inner layer 71 of an n-type semiconductor region with a concentration of at most (n ++) is formed by ion implantation in the semiconductor formed by epitaxial growth.

In the drain region 8, after forming an outer layer 82 of a high concentration (P+) n-type semiconductor region, an inner layer 81 of a high concentration (n'') n-type semiconductor region is formed.

In the manner described above, a nonvolatile semiconductor memory having the element structure shown in FIG. 1 can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, a configuration may be adopted in which an erase voltage is applied to the drain D side. In addition, MOSFET that constitutes the memory element
may be configured as a p-channel type. In the above explanation, the invention made by the present inventor was mainly applied to the EEP-ROM with a two-layer gate structure, which is the field of application that formed the background of the invention, but the invention is not limited thereto. Gate structure EP-,-ROM
It can also be applied to

[Effects of the Invention 1 The effects obtained by typical inventions disclosed in this application are briefly explained below.

5 In other words, it is possible to shorten the erasing time of an electrically erasable nonvolatile semiconductor memory without increasing the leakage current between the source or drain region and the semiconductor substrate and improving the withstand voltage. It will be done.

[Brief explanation of drawings]

FIG. 1 is an abbreviated sectional view showing essential parts of a nonvolatile semiconductor memory according to an embodiment of the present invention, and FIG. 2 is a first embodiment of a method for manufacturing a nonvolatile semiconductor memory having the element structure shown in FIG. 1. 3 is an abbreviated sectional view showing the main parts of a second embodiment of the method for manufacturing a nonvolatile semiconductor memory having the element structure shown in FIG. 1, and FIG. 4 is an abbreviated sectional view showing the main parts of a conventional FIG. 2 is an abbreviated cross-sectional view showing essential parts of a nonvolatile semiconductor memory. 1... p-type (first conductivity type) silicon semiconductor substrate,
2...First gate insulating film, 3...Floating gate electrode, FG...Floating gate,
4...Second gate insulating film, 5...Control electrode, CG...Control gate, 6
...Channel area, 7...Source area, S...
... Source, 71 ... Inner layer consisting of an n-type semiconductor region with at most concentration (n++), 711 ... N-type semiconductor region for making contact with the electrode, 72 ... Low concentration (n-) intermediate layer consisting of an n-type semiconductor region, 73.
... Outer layer consisting of a high concentration (nl) n-type semiconductor region, 8... Train region, D... Drain, 81
...Inner layer, 811...N-type semiconductor region for making contact with electrode, 82...Outer layer, 91
...Side wall spacer.

Claims (1)

[Claims] 1. A floating gate electrode formed on a semiconductor substrate of a first conductivity type via a gate insulating film, and a floating gate electrode of a second conductivity type formed sandwiching a channel region under the floating gate electrode. A nonvolatile semiconductor memory in which an electrically writable and erasable memory element is formed by a source region and a drain region, wherein the source (or drain) region has a high concentration concentration in a portion overlapping with the floating gate electrode. a nonvolatile material comprising: an outer layer consisting of a second conductivity type semiconductor region; an intermediate layer consisting of a low concentration second conductivity type semiconductor region; and an inner layer consisting of a second conductivity type semiconductor region having at most a concentration semiconductor. 2. A floating gate electrode formed on a semiconductor substrate of a first conductivity type via a gate insulating film, and a source region and a drain region of a second conductivity type formed across a channel region under the floating gate electrode. A method for manufacturing a non-volatile semiconductor memory in which an electrically writable and erasable memory element is formed by a step of forming a semiconductor region; a step of forming a low concentration first conductivity type semiconductor region by diffusing a first conductivity type imparting impurity into the second conductivity type semiconductor region; 1. A method of manufacturing a nonvolatile semiconductor memory, comprising: forming a semiconductor region of a second conductivity type with a high concentration within the semiconductor memory. 3. A floating gate electrode formed on a first conductivity type semiconductor substrate via a first gate insulating film, and a second conductivity type source region formed across a channel region under the floating gate electrode. A method for manufacturing a non-volatile semiconductor memory in which an electrically writable and erasable memory element is formed by an electrically writable and erasable memory element and a drain region, the method comprising an etching step of selectively digging out a portion of the semiconductor substrate that will become the source (or drain) region. a step of forming a high concentration second conductivity type semiconductor region in the portion dug by this etching step; and selectively epitaxially growing a low concentration second conductivity type semiconductor region on the second conductivity type semiconductor region. 1. A method of manufacturing a nonvolatile semiconductor memory, comprising: a step of forming a semiconductor region of a second conductivity type with a high concentration within a semiconductor region formed by this epitaxial growth.