JPH0371859A - Thermal head - Google Patents

Thermal head

Info

Publication number
JPH0371859A
JPH0371859A JP1208258A JP20825889A JPH0371859A JP H0371859 A JPH0371859 A JP H0371859A JP 1208258 A JP1208258 A JP 1208258A JP 20825889 A JP20825889 A JP 20825889A JP H0371859 A JPH0371859 A JP H0371859A
Authority
JP
Japan
Prior art keywords
control
block
odd
recording
image signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1208258A
Other languages
Japanese (ja)
Inventor
Tetsuichiro Yamamoto
哲一郎 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1208258A priority Critical patent/JPH0371859A/en
Publication of JPH0371859A publication Critical patent/JPH0371859A/en
Pending legal-status Critical Current

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  • Fax Reproducing Arrangements (AREA)

Abstract

PURPOSE:To make it possible to minimize feed irregularities even in continuously variable recording by providing even/odd-number control elements for image selection and block control terminals for block selection as a drive circuit for semi-conductor switching elements which control the energization of thermal resistors of a thermal head. CONSTITUTION:Printing energy required for recording is provided by controlling transistors 3, 4 and thereby controlling the energization time of thermal resistors 1, 2. In this case, the transistors 3, 4 are controlled by control circuits 5, 6, even/odd-number control elements 7, a block control element 8 and image signal input terminals 9, 10. In addition, image signal input terminals 9, 10 are constituted so that the control circuits 5, 6 allow recording by an image signal from a shift register 11, if the content of the shift register 11 is black pixels when a latch signal is connected from a latch signal terminal 12. Thermal resistors 1, 2 can be controlled so that they record data selectively by selecting the thermal resistors 1, 2 using the even/odd-number control terminals 7 and allowing a record permitting signal to be connected from the block control terminal 8.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はサーマルヘッドンこ関し、特にサーマルヘッド
の駆動回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thermal head, and more particularly to a drive circuit for a thermal head.

〔従来の技術〕[Conventional technology]

従来のサーマルヘッドでは、発熱抵抗体列な複数のブロ
ックに分割■7通電をブロック単位に行っていた。
Conventional thermal heads are divided into multiple blocks, each consisting of a row of heat-generating resistors, and energization is applied to each block.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

L述した従来のサーマルヘッドでは、同時に通電する連
続した複数個の発熱抵抗体をブロック単位と1−1複数
ブロツクの通電を順次、時系列的に行う為、記録紙の走
行が連続可変の場合、記録の送りムラを生じやすいとい
う欠点があった。また、消費電力軽減の為、画信号を間
引いて印字率を下げる等の処理も、容易に由来ないとい
う欠点があった。
In the conventional thermal head mentioned above, the continuous heating resistors that are energized at the same time are energized block by block and 1-1 multiple blocks sequentially and time-sequentially, so when the running of the recording paper is continuously variable. However, this method has the disadvantage that uneven recording tends to occur. Another disadvantage is that it is not easy to carry out processing such as thinning out image signals to lower the printing rate in order to reduce power consumption.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のサーマルヘッドは、−列に配列した発熱抵抗体
と、前記発熱抵抗体の各々に対し通電を制御する為に設
けた半導体スイッチ素子と、前記半導体スイッチ素子を
個々に制御する為に設けた制御回路部と、前記前記制御
回路部に対し前記各半導体スイッチ素子(前記各発熱抵
抗体)の偶数列とで分割して通電する為に設けた偶/奇
制御端子と、前記半導体スイッチ素子を複数個ずつブロ
ック単位に分割して通電する為に設けたブロック制御端
子とを有する。
The thermal head of the present invention includes heating resistors arranged in a row, a semiconductor switch element provided to control energization to each of the heat generating resistors, and a semiconductor switch element provided to individually control the semiconductor switch elements. a control circuit section, an even/odd control terminal provided for dividing and energizing the control circuit section between even-numbered rows of each of the semiconductor switch elements (each of the heat generating resistors), and the semiconductor switch element. It has a block control terminal provided for dividing into a plurality of blocks and energizing them.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は、本発明の一実施例の一部を示す回路図であり
、第n番目及び第n+1番目の発熱抵抗体部を代表して
表している。(但し、n=2m:mは整数) 第n番目及び第n+1番目の発熱抵抗体】、2は、トラ
ンジスタ(半導体スイッチ素子)3,4と直列に接続さ
れており、トランジスタ3,4を制御することで前記発
熱抵抗体1,20通電時間を制御し、記録に必要な印字
エネルギーを与える。
FIG. 1 is a circuit diagram showing a part of an embodiment of the present invention, in which the n-th and (n+1)-th heating resistor sections are representatively shown. (However, n=2m: m is an integer) The n-th and n+1-th heating resistors], 2 are connected in series with transistors (semiconductor switch elements) 3 and 4, and control the transistors 3 and 4. By doing so, the energization time of the heating resistors 1 and 20 is controlled, and printing energy necessary for recording is provided.

このとき、前記トランジスタ3,4は、制御回路5.6
、偶/奇制御端子7、プロ、り制御端子8、及び画信号
入力端子9,10によって制御される。
At this time, the transistors 3 and 4 are connected to the control circuit 5.6.
, an even/odd control terminal 7, an output control terminal 8, and image signal input terminals 9 and 10.

tた。画信号入力端子9,1oは、シフトレジスタ11
の画信号をラッチ信号端子12よりラッチ信号が入力さ
れた時、シフトレジスタ11の内容が黒画素の場合に、
制御回路5,6が記録可能状態となるように構成されて
いる。尚、シフトレジスタ11には外部より画信号を入
力する為に、画信号入力端子13と、画信号入力端子1
3と、画信号転送りロック入力端子14とを設けである
It was. The image signal input terminals 9 and 1o are connected to the shift register 11.
When a latch signal is input from the latch signal terminal 12, if the content of the shift register 11 is a black pixel,
The control circuits 5 and 6 are configured to be in a recordable state. Note that the shift register 11 has an image signal input terminal 13 and an image signal input terminal 1 in order to input an image signal from the outside.
3 and an image signal transfer lock input terminal 14.

したがって、本駆動回路では、偶/奇制御端子7によっ
て発熱抵抗体1、あるいは2を選択し、ブロック制御端
子8から記録許可信号を入力することにより、発熱抵抗
体1、あるいは2が選択的に記録動作となる制御が可能
である。すなわち、ブロック分割印字と同時にブロック
内での偶数画素、奇数画素の分割印字が制御可能な構成
となっている。
Therefore, in this drive circuit, heating resistor 1 or 2 is selected by using even/odd control terminal 7, and by inputting a recording permission signal from block control terminal 8, heating resistor 1 or 2 is selectively selected. It is possible to control the recording operation. That is, the configuration is such that it is possible to control block division printing and division printing of even-numbered pixels and odd-numbered pixels within a block at the same time.

第2図は、本発明の実施例の全体構成図である。FIG. 2 is an overall configuration diagram of an embodiment of the present invention.

発熱抵抗体列21 (第1図の前記発熱抵抗体l。Heating resistor row 21 (the heating resistor l in FIG. 1).

2に相当)はトランジスタ・アレイ22(第1図のトラ
ンジスタ3,4に相当)と各々直列に接続されている。
2) are each connected in series with a transistor array 22 (corresponding to transistors 3 and 4 in FIG. 1).

トランジスタ・アレイ22は個々のトランジスタに対す
るトランジスタ制御部23(第1図の制御回路5,6に
相当)により画素単位で個々に0N10FF制御される
。トランジスタ制御部23は偶/奇制御端子24、ブロ
ック制御端子25.26からの入力信号、及びシフトレ
ジスタ27からの画信号により制御される。すなわち、
画信号は転送ブジック入力端子3oからの転送りロック
に同期してシフトレジスタ27に画信号入力端子28か
ら外部より入力され、ラッチ信号端子29からのラッチ
信号によりトランジスタ制御部23にセットされる。同
時に、トランジスタ制御部23は、偶/奇制御端子24
により偶数画素あるいは奇数画素が指定される。次に、
ブロック制御端子25あるいは26から記録許可信号が
入力されることで、該当ブロックの黒画素に相当するト
ランジスタがON状態となり発熱抵抗体が通電状態とな
り、記録紙に記録することになる。(本図ではブロック
分割数を奇数・偶数の2ブロツクとしたときの例である
。) 第3図は、第2図のサーマルヘッドを駆動するためのタ
イミング図の一例である。本図は、偶数画素(奇数画素
)を第一ブロック、第ニブロックの順に、続いて奇数画
素(偶数画素)を第一ブロック、第ニブロックの順に印
字して1ラインを記録する場合の一例を示している。こ
のとき、従来のサーマルヘッドで4ブロツクで分割印字
した場合と記録電流の最大値が変わらないことは容易に
わかる。
The transistor array 22 is individually 0N10FF controlled for each pixel by a transistor control section 23 (corresponding to the control circuits 5 and 6 in FIG. 1) for each transistor. The transistor control section 23 is controlled by input signals from an even/odd control terminal 24, block control terminals 25 and 26, and an image signal from a shift register 27. That is,
The image signal is externally input to the shift register 27 from the image signal input terminal 28 in synchronization with the transfer lock from the transfer logic input terminal 3o, and is set in the transistor control section 23 by a latch signal from the latch signal terminal 29. At the same time, the transistor control section 23 controls the even/odd control terminal 24
An even numbered pixel or an odd numbered pixel is specified. next,
When a recording permission signal is input from the block control terminal 25 or 26, the transistor corresponding to the black pixel of the block is turned on, the heating resistor is energized, and recording is performed on the recording paper. (This figure shows an example in which the number of block divisions is two, odd and even blocks.) FIG. 3 is an example of a timing diagram for driving the thermal head of FIG. 2. This figure is an example of recording one line by printing even-numbered pixels (odd-numbered pixels) in the order of the first block and second block, and then printing the odd-numbered pixels (even-numbered pixels) in the order of the first block and the second block. It shows. At this time, it is easy to see that the maximum value of the recording current is the same as when printing is performed in four blocks using a conventional thermal head.

なお、本発明の実施例では半導体スイッチ素子(トラン
ジスタアレイ22)と制御回路(トランジスタ制御部2
3)と偶/奇制御端子とブロック制御端子とを集積化し
駆動回路としてサーマルヘッドに搭載している。
In addition, in the embodiment of the present invention, a semiconductor switch element (transistor array 22) and a control circuit (transistor control section 2
3), even/odd control terminals, and block control terminals are integrated and mounted on the thermal head as a drive circuit.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、サーマルヘッドの発熱抵
抗体の通電を制御する半導体スイッチ素子(トランジス
タ)の駆動回路として、画素選択の偶/奇制御端子とブ
ロック選択のブロック制御端子とを有している為、 (1)連続可変の記録においても送りムラが軽減できる
制御が可能である。
As described above, the present invention has an even/odd control terminal for pixel selection and a block control terminal for block selection as a drive circuit for a semiconductor switch element (transistor) that controls the energization of a heating resistor of a thermal head. (1) Control that can reduce feeding unevenness even in continuously variable recording is possible.

(2)記録の画質を劣化させることなく記録時の最大電
流を小さくできる。
(2) The maximum current during recording can be reduced without deteriorating the image quality of recording.

(3)画信号に対して1画素毎の間引き処理が容易にで
きる。
(3) The image signal can be easily thinned out on a pixel by pixel basis.

という効果がある。There is an effect.

1.2・・・・・・発熱抵抗体、3,4・・・・・・半
導体スイッチ素子、5,6・・・・・・制御回路部、7
,24・・・・・偶/奇制御端子、8,25.26・・
・・・・ブロック制御端子、9,10・・・・・・画信
号入力端子、11゜27・・・・・・シフトレジスタ、
12.29・・・・・・ラッチ信号端子、13.28・
・・・・・画信号入力端子、14゜30・・・・・・転
送りロック入力端子、15.31・・・・・・インバー
タ、16.32・・・・・・記録電源、21・・・・・
・発熱抵抗体列、22・・・・・・トランジスタ・アレ
イ、23・・・・・・トランジスタ制御部。
1.2... Heat generating resistor, 3, 4... Semiconductor switch element, 5, 6... Control circuit section, 7
, 24...Even/odd control terminal, 8, 25.26...
...Block control terminal, 9,10... Image signal input terminal, 11゜27... Shift register,
12.29... Latch signal terminal, 13.28.
... Image signal input terminal, 14°30 ... Transfer lock input terminal, 15.31 ... Inverter, 16.32 ... Recording power supply, 21.・・・・・・
- Heating resistor array, 22...transistor array, 23...transistor control section.

Claims (2)

【特許請求の範囲】[Claims] (1)一列に配列した発熱抵抗体と、前記発熱抵抗体の
各々に対し通電を制御する為に設けた半導体スイッチ素
子と、前記各半導体スイッチ素子(前記各発熱抵抗体)
を個々に制御する為に設けた制御回路部と、前記制御回
路部に対し前記各半導体スイッチ素子(前記各発熱抵抗
体)の偶数列と奇数列とで分割して通電する為に設けた
偶/奇制御端子と、前記各半導体スイッチ素子(前記各
発熱抵抗体)を複数個ずつのブロック単位に分割して通
電する為に設けたブロック制御端子とを有することを特
徴とするサーマルヘッド。
(1) Heat generating resistors arranged in a row, a semiconductor switch element provided to control energization to each of the heat generating resistors, and each of the semiconductor switch elements (each of the heat generating resistors)
a control circuit section provided to individually control the semiconductor switch elements (heating resistors); / A thermal head characterized by having an odd control terminal and a block control terminal provided for dividing each of the semiconductor switching elements (each of the heating resistors) into a plurality of blocks and energizing them.
(2)前記半導体スイッチ素子と前記制御回路部と前記
偶/奇制御端子と前記ブロック制御端子とを集積化し駆
動回路としてサーマルヘッドに搭載することを特徴とす
る特許請求の範囲第(1)項記載のサーマルヘッド。
(2) Claim (1) characterized in that the semiconductor switch element, the control circuit section, the even/odd control terminal, and the block control terminal are integrated and mounted on the thermal head as a drive circuit. Thermal head listed.
JP1208258A 1989-08-11 1989-08-11 Thermal head Pending JPH0371859A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1208258A JPH0371859A (en) 1989-08-11 1989-08-11 Thermal head

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1208258A JPH0371859A (en) 1989-08-11 1989-08-11 Thermal head

Publications (1)

Publication Number Publication Date
JPH0371859A true JPH0371859A (en) 1991-03-27

Family

ID=16553262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1208258A Pending JPH0371859A (en) 1989-08-11 1989-08-11 Thermal head

Country Status (1)

Country Link
JP (1) JPH0371859A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5349623A (en) * 1991-10-14 1994-09-20 Mitsubishi Denki Kabushiki Kaisha Driving circuit for exothermic resistors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5349623A (en) * 1991-10-14 1994-09-20 Mitsubishi Denki Kabushiki Kaisha Driving circuit for exothermic resistors

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