JPH0371394U - - Google Patents

Info

Publication number
JPH0371394U
JPH0371394U JP13381489U JP13381489U JPH0371394U JP H0371394 U JPH0371394 U JP H0371394U JP 13381489 U JP13381489 U JP 13381489U JP 13381489 U JP13381489 U JP 13381489U JP H0371394 U JPH0371394 U JP H0371394U
Authority
JP
Japan
Prior art keywords
performance
time difference
data
storage means
performance data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13381489U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13381489U priority Critical patent/JPH0371394U/ja
Publication of JPH0371394U publication Critical patent/JPH0371394U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本考案の1実施例の全体構成図、第
2図は、スイツチ部3の各スイツチの状態を表す
図、第3図aは、演奏データRAM8の構成図、
第3図bは、ワーキングRAM7の構成図、第4
図は、時間差データの説明図、第5図は、TEM
POスイツチ押下時の動作フローチヤート、第6
図は、再生モードの動作フローチヤートである。 1……鍵盤部、2……押鍵検出および発音割当
て回路、3……スイツチ部、4……スイツチ検出
回路、5……CPU、6……プログラムROM、
7……ワーキングRAM、8……演奏データRA
M、9……タイマー部、10……テンポ値表示部
、11……テンポ値変換テーブル、12……楽音
発生回路、13……D/A変換器、14……増幅
器、15……スピーカ。
FIG. 1 is an overall configuration diagram of one embodiment of the present invention, FIG. 2 is a diagram showing the states of each switch of the switch section 3, and FIG. 3a is a configuration diagram of the performance data RAM 8.
FIG. 3b is a block diagram of the working RAM 7,
The figure is an explanatory diagram of time difference data, and Figure 5 is a TEM
Operation flowchart when pressing the PO switch, No. 6
The figure is an operation flowchart of playback mode. 1...Keyboard section, 2...Key press detection and sound generation assignment circuit, 3...Switch section, 4...Switch detection circuit, 5...CPU, 6...Program ROM,
7... Working RAM, 8... Performance data RA
M, 9...Timer unit, 10...Tempo value display unit, 11...Tempo value conversion table, 12...Music tone generation circuit, 13...D/A converter, 14...Amplifier, 15...Speaker.

Claims (1)

【実用新案登録請求の範囲】 演奏者に楽曲を演奏させる演奏手段と、 該演奏手段より得られる演奏データを記憶する
ための複数の記憶領域からなる演奏データ記憶手
段と、 前記演奏データ記憶手段の前記任意の複数の記
憶領域から演奏データを順次読み出して自動演奏
を行う場合の該各記憶領域に対応する各楽曲パー
トの開始時点の時間差を演奏時間差データとして
記憶する演奏時間差データ記憶手段と、 前記演奏者に前記演奏手段を介して演奏を行わ
せ、それにより得られる演奏データを前記演奏デ
ータ記憶手段の任意の記憶領域に選択的に記憶さ
せる演奏データ書き込み手段と、 前記各記憶領域毎の演奏時間差データを演奏者
に設定させ、前記演奏時間差データ記憶手段に書
き込む演奏時間差データ書込手段と、 前記演奏データ記憶手段から該記憶手段の所望
の記憶領域の演奏データを順次読み出して自動演
奏を行い、その場合に該記憶手段の各記憶領域か
ら最初の演奏データを読み出すときのタイミング
を前記演奏時間差データ記憶手段に記憶されてい
る対応する前記演奏時間差データに基づいて遅延
させて、自動演奏を行う自動演奏手段と、 を有することを特徴とする自動演奏装置。
[Claims for Utility Model Registration] Performance means for causing a performer to play a piece of music; performance data storage means comprising a plurality of storage areas for storing performance data obtained from the performance means; and the performance data storage means. Performance time difference data storage means for storing, as performance time difference data, the time difference between the start points of each music part corresponding to each storage area when performance data is sequentially read from the arbitrary plurality of storage areas and automatic performance is performed; Performance data writing means for causing a performer to perform through the performance means and selectively storing performance data obtained thereby in an arbitrary storage area of the performance data storage means; and performance data for each of the storage areas. performance time difference data writing means for causing a performer to set time difference data and writing it into the performance time difference data storage means; and performance data in a desired storage area of the performance data storage means being sequentially read out from the performance data storage means for automatic performance. In that case, automatic performance is performed by delaying the timing when reading the first performance data from each storage area of the storage means based on the corresponding performance time difference data stored in the performance time difference data storage means. An automatic performance device comprising: automatic performance means;
JP13381489U 1989-11-17 1989-11-17 Pending JPH0371394U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13381489U JPH0371394U (en) 1989-11-17 1989-11-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13381489U JPH0371394U (en) 1989-11-17 1989-11-17

Publications (1)

Publication Number Publication Date
JPH0371394U true JPH0371394U (en) 1991-07-18

Family

ID=31681204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13381489U Pending JPH0371394U (en) 1989-11-17 1989-11-17

Country Status (1)

Country Link
JP (1) JPH0371394U (en)

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